Abstract: Systems and methods are disclosed herein for selectively compensating for a specific Intermodulation Distortion (IMO) product(s) of an arbitrary order in a transmitter system. In some embodiments, a method of compensating for one or more specific IMO products in a concurrent multi-band transmitter system comprises generating an IMO correction signal for a specific IMO product as a function of two or more frequency band input signals for two or more frequency bands of a concurrent multi-band signal, the IMO product being an arbitrary order IMD product. The method further comprises frequency translating the IMD correction signal to a desired frequency that corresponds to a Radio Frequency (RF) location of the specific IMO product and, after frequency translating the IMO correction signal to the desired frequency, utilizing the IMO correction signal to compensate for the specific IMO product.

Abstract: A circuit arrangement for filtering an electric current, wherein the circuit arrangement is arranged between a power source providing the electric current and a load; and the electric current includes a first current component and a second current component. The circuit arrangement includes a first circuit arranged to receive and filter the first current component, a current control device arranged to receive and regulate the second current component so as to provide a regulated current to the load, and a control circuit arranged to provide a control signal to the current control device so as to control regulation of the second current component. The control circuit is further arranged to detect one or more operation parameters associated with the current control device, and to determine the control signal based on the one or more detected operation parameters.

Abstract: A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage.

Abstract: An amplifier having orthogonal tuning elements is provided. In one embodiment, an amplifier comprises an input amplifier stage having a first tuning element used to control a first performance criteria of the amplifier; an output amplifier stage operatively coupled to the first amplifier stage; a bias circuit operatively coupled to the second amplifier stage and having a second tuning element used to control a second performance criteria of the amplifier; and wherein the first tuning element operates substantially independent of the second tuning element.

Abstract: A current sensor to be connected in series with a power semiconductor device between a voltage supply terminal and ground. The current sensor includes a first terminal to be coupled to the power semiconductor device, a second terminal to be coupled to one of the voltage supply terminal and ground, and a current mirror. The current mirror includes a first MOSFET and a second MOSFET each having a source, a drain, and a gate. The source of the first MOSFET is connected to the source of the second MOSFET and to the second terminal, the drain of the first MOSFET is connected to the first terminal, and the gate of the first MOSFET is connected to the gate of the second MOSFET.

Abstract: Embodiments described herein relate to an improved circuit technique in a rail-to-rail input stage circuit utilizing non-complementary differential pairs with bias control designed to maintain a constant transconductance “gm” throughout an input common mode voltage range. The rail-to-rail input stage circuit comprises a first differential pair circuit, a level-shifted differential pair circuit coupled with the first differential pair circuit, and a constant transconductance generation circuit coupled with the level-shifted differential pair circuit. The constant transconductance generation circuit is configured to control the bias current conducting in the level-shifted differential pair circuit based on current conducting in the first differential pair circuit to maintain a constant transconductance in the rail-to-rail input stage circuit.

Abstract: This disclosure describes a circuit implementation providing the functions necessary to implement an isolated I2C bidirectional port. The technique implements a current source as a pull up device on at least one side of the isolation system. The circuit manages and communicates bidirectional data across an isolation barrier. A method of communicating bidirectional signals and an I2C acknowledge (ACK) or clock stretching through an isolation channel is disclosed.

Abstract: The invention relates to a two stage class AB operational amplifier for driving a load, comprising at least an input stage comprising differential input terminals and an output terminal to provide a driving signal. In addition, the operational amplifier comprises an output stage comprising a first and second input terminals operatively associated to the input stage to be driven on the basis of said driving signal and a driving circuit operatively interposed between said input stage and the output stage. The operational amplifier is characterized in that the driving circuit comprises a first portion comprising at least one resistor operatively connected between a first reference potential via a first circuitry block comprising a PMOS transistor and a second reference potential via a second circuitry block comprising a NMOS transistor.

Abstract: A differential amplifier comprising a first upper device and a first lower device series coupled between two power supplies and a second upper device and a second lower device series coupled between the two power supplies. A first DC voltage enables the first upper device and the second upper device and a second DC voltage regulates current flow in the first lower device and the second lower device. An AC signal component is coupled to the first upper device and the second lower device while the AC signal complement is coupled to the first lower device and the second upper device. Separate RC networks couple the AC signals to their respective device. A first and second output signal forms between the upper device and the lower device, respectively. All the devices are same channel type.

Abstract: Described embodiments include a level shifter that provides a voltage level shift to applied signals, the amount of voltage shift being accurately controlled and independent of PVT. The level shifter has first transistor configured as a voltage follower with the gate coupled to an input terminal of the shifter and the source coupled to a node, a diode-connected transistor coupled between the node and an output terminal of the circuit, a first controlled current source coupled to the node, and a second controlled current source coupled to the output terminal. A controller receives a bandgap-stabilized voltage, squares the stabilized voltage to produce a control signal that controls the first and second controlled current sources. The voltage shift is proportional to a digitally-controlled scale factor (K) times the stabilized voltage. The ratio of the current from the first current source to the second current source is (K+1)/K.

Abstract: A differential amplifier comprising a first upper device and a first lower device series coupled between two power supplies and a second upper device and a second lower device series coupled between the two power supplies. A first DC voltage enables the first upper device and the second upper device and a second DC voltage regulates current flow in the first lower device and the second lower device. An AC signal component is coupled to the first upper device and the second lower device while the AC signal complement is coupled to the first lower device and the second upper device. A first output signal between the first upper device and the first lower device. Separate RC networks couple the AC signals to their respective device. A first and second output signal forms between the upper device and the lower device, respectively. All the devices are same channel type.

Abstract: A signal amplifier including a transformer with a primary winding and a secondary winding, an oscillator circuit driven by an input signal establishing in the primary winding an oscillating signal amplified by the secondary, and a rectifier circuit responsive to the secondary winding configured to convert the amplified oscillating signal to an amplified version of the input signal.

Abstract: A charge storage circuit for a pixel comprises a charge storage node. First and second series-connected transistors (8,10) are provided for selectively isolating the charge storage node from a first voltage input (9,SL) for supplying a data voltage. The circuit is provided with a voltage follower circuit for replicating a voltage at the charge storage node (12) at another node in the circuit thereby to reduce the drain-source voltage across the second transistor (10). The first transistor forms part of the voltage follower circuit.

Abstract: A differential drive circuit includes at least a first or second drive system. The first drive system has first and second field effect transistors, first and second resistors, and first and second circuits controlling the source voltages of the first and second field effect transistors to equal first and second drive target voltages, the first and second field effect transistors having sources connected to a power potential via the first and second resistors, respectively. The second drive system has third and fourth field effect transistors, third and fourth resistors, and third and fourth circuits controlling the source voltages of the third and fourth field effect transistors to equal third and fourth drive target voltages, the third and fourth field effect transistors having sources connected to a reference potential via the third and fourth resistors, respectively. A common-mode voltage is driven to form a constant differential signal across a load resistance.

Abstract: A power supply includes: a switching amplifier including an input and an output, the amplifier input being adapted to be powered by an electrical power source; a transformer including a primary and a secondary winding on a magnetic core, the number of winding turns being chosen to limit magnetization levels to avoid magnetic saturation while maximizing winding spacing, the transformer primary winding being in communication with the amplifier output; a rectification system in communication with the transformer secondary winding, the rectification system providing a DC power output; and a controller. The controller monitors the DC power output and adjusts the switching amplifier in response to the monitoring to provide a desired power output characteristic.

Abstract: Methods and systems for reducing parasitic capacitance of a buffer for an electric circuit are disclosed and may include coupling a gate of a first transistor to a first differential input of the buffer via a first capacitor, coupling a gate of a second transistor to a second differential input of the buffer via a second capacitor. The first and second transistors may be biased by a common mode output of a direct current (DC) voltage source for the buffer. The common mode output of the DC voltage source may be directly coupled to at least one differential output of the buffer via an inductor. The first transistor and the second transistor may comprise NMOS transistors and/or PMOS transistors. The DC voltage source may comprise a PMOS transistor and/or an NMOS transistor.

Abstract: An AC differential connection assembly between a trans-impedance amplifier and a post amplifier for burst mode receiving comprising means for coupling a differential output of the trans-impedance amplifier to a differential input of the post amplifier, the means for coupling comprises a coupling capacitor assembly; and a switching circuit coupled across the differential input of the post amplifier, the switching circuit having an ‘on’ state with low impedance and an ‘off’ state with high impedance; wherein during burst mode receiving, the switching circuit is in the ‘off’ state and the coupling capacitor assembly having a time constant to maintain a stable DC level such that a payload is received accurately by the differential input of the post amplifier; and during an idle period, the switching circuit is in the ‘on’ state and the coupling capacitor assembly having a time constant to recover a DC level of the differential output of the trans-impedance amplifier.

Abstract: An operation amplifier (op-amp) and a circuit for providing dynamic current thereof are disclosed. The circuit can be applied to any current op-amp. The circuit comprises two transistors which are simultaneously or non-simultaneously turned on as the input signals respectively received by the first input and the second input of the op-amp get a transition, namely, as the op-amp is in the transient state, so as to increase the bias current at the first input terminal or/and the second input terminal of the op-amp by a dynamic current. Therefore, not only the internal slew rate of the op-amp can be accelerated by the circuit of the present invention, but also the power consumption of the op-amp can not be increased by the circuit of the present invention as the op-amp in the steady state.

Abstract: A method of implementing a transistor circuit comprises coupling first and second transistors in parallel, wherein the first transistor has a channel length corresponding to a peak in the transistor's voltage threshold curve arising from reverse short channel effects, and the second transistor has a longer channel length and, therefore, a lower threshold voltage. Exploiting reverse short channel effects in this manner enables the implementation of “composite” transistor circuits that exhibit improved linearity.

Abstract: A method for tuning a filter is provided. The method includes: enabling a VCO circuit, wherein at least a portion of the VCO circuit is selected from the filter; generating an oscillation signal by the VCO circuit according to a driving signal; comparing the oscillation signal with a reference signal and generating a comparison result; and adjusting the driving signal according to the comparison result.

Abstract: A current sensor senses the current at a sense transistor and generates an output current that is an accurate proportional representation of the current at the sense transistor. Furthermore, the sensed current is relatively independent of the resistive load of the feedback path at feedback control module to which it is applied. In one embodiment, the feedback control module uses the sensed current in a DC-DC voltage converter to regulate a voltage. The current sensor employs a pair of operational amplifiers to match a voltage at a current electrode of a transistor that generates the output current to a voltage at a current electrode of the sense transistor, such that an effective resistance of the transistor generating the output current is significantly higher than the resistive load of the feedback control module, thereby ensuring that the output current is relatively independent of the resistive load of the feedback control module.

Abstract: A level shifter includes a first level shift module for producing a shifted signal by adjusting a direct current (DC) level of an input signal by a first bias voltage having a first polarity. A second level shift module produces an output signal by adjusting a DC level of the shifted signal by a second bias voltage having a second polarity. The first polarity is opposite to the second polarity and the sum of the first bias voltage and the second bias voltage is a non-zero voltage.

Abstract: A memory device having a differential buffer is disclosed. In some embodiments, the memory device includes a differential buffer having a differential pair that is configured to receive input signals and generate output signals. In one embodiment, the differential buffer of the memory device includes adjustment circuitry coupled to the differential pair to enable adjustment of the amount of current dissipated by the differential buffer. Other memory devices, differential buffers, and methods are also disclosed.

Abstract: The present invention relates to a frequency-independent voltage divider in which a compensation structure (10) for compensating a distributed parasitic capacitance of a resistor arrangement (20) is arranged between the resistor arrangement (20) and a substrate (50). Thereby, the compensation structure (10) shields the resistor arrangement (20) partly from the substrate (50), and thus shields the parasitic capacitance. This allows for an improved compensation.

Abstract: An operation amplifier (op-amp) and a circuit for providing dynamic current thereof are disclosed. The circuit can be applied to any current op-amp. The circuit comprises two transistors which are simultaneously or non-simultaneously turned on as the input signals respectively received by the first input and the second input of the op-amp get a transition, namely, as the op-amp is in the transient state, so as to increase the bias current at the first input terminal or/and the second input terminal of the op-amp by a dynamic current. Therefore, not only the internal slew rate of the op-amp can be accelerated by the circuit of the present invention, but also the power consumption of the op-amp can not be increased by the circuit of the present invention as the op-amp in the steady state.

Abstract: A method for tuning a filter is provided. The method includes: enabling a VCO circuit, wherein at least a portion of the VCO circuit is selected from the filter; generating an oscillation signal by the VCO circuit according to a driving signal; comparing the oscillation signal with a reference signal and generating a comparison result; and adjusting the driving signal according to the comparison result.

Abstract: An output buffer circuit includes an input stage of which one end receives an input voltage and the other end receives an output voltage; a class AB output stage that increases a current flowing in the output stage when the difference between the input and output voltages is larger than 0; a floating current source that biases the class AB output stage; a summing circuit that is connected to the input stage, the floating current source, and the class AB output stage so as to sum up the current supplied from the input stage and the internal current supplied from the floating current source; and an offset compensating circuit that is connected to the input stage and is composed of a plurality of switching elements and resistors so as to detect an offset voltage to compensate.

Abstract: A differential receiver circuit receives a differential input signal including first and second input signals (DP, DM) and generates a single-ended output signal. The receiver circuit includes first and second comparators that receive the differential input signal and generate respective first and second differential output signals. A current summer is connected to the first and second comparators and receives the first and second differential output signals and generates a third differential output signal. A differential to single-ended converter is connected to the current summer and receives the third differential output signal and generates the single-ended output signal. The differential input signal varies from a ground voltage level to an external reference voltage level (VUSB), while the first and second comparators are made with devices that operate at an internal reference voltage level that is lower than the external reference voltage level.

Abstract: A tuning method and a tuning apparatus for tuning a filter are disclosed. The tuning method includes: configuring the filter as a VCO; utilizing the VCO to generate an oscillation signal according to a driving signal; comparing a frequency of the oscillation signal with a reference frequency to generate a comparison result; converting the comparison result into the driving signal in order to establish a feedback mechanism. Therefore, the inner components such as the gm and capacitance inside the VCO are completely tuned when the VCO generates an oscillation signal having a wanted frequency. Since the VCO is inside the filter and the components of the filter and the VCO are similar, the driving signal can be utilized to make the filter operate in a desired center frequency under a well-designed relationship between the frequency of the oscillation signal and the center frequency.

Abstract: A versatile, programmable, low-cost transmit line driver is provided. The line driver includes a digital-to-analog converter that receives a digital input and provides an analog output. The line driver is reconfigurable between the voltage mode of operation.

Abstract: Provided are a method and system for controlling impedance in a transconductance amplifier. A system includes a first transconductance amplifier and a second transconductance amplifier configured to control electrical characteristics associated with the first transconductance amplifier. An operational amplifier is provided and has at least one input port connected to the second transconductance amplifier. Also included is a first digital to analog converter (DAC) connected to receive a current signal from the operational amplifier.

Abstract: A clock signal preamplifier comprises complementary pairs of differentially coupled transistors, with an output signal coupled to an inverter further comprising a totem-pole arrangement of complementary MOSFET transistors. The input signal to the preamplifier is typically sinusoidal, and the output signal is rectangular. Preferably, the differentially coupled transistors are bipolar, and a pair of diode clamper circuits with bipolar transistors is preferably coupled to the complementary pairs of differentially coupled transistors. A reference voltage source is coupled to the control terminals of the clamper transistors. A reference voltage source, which preferably comprises a totem-pole arrangement of complementary MOSFET transistors with its output node is coupled to its input node, provides a reference voltage for the diode clamper circuits.

Abstract: A wideband low noise amplifier (LNA) includes a correction circuit added to compensate for third order intermodulations. A version of the third order nonlinearities created in the main LNA is created in an auxiliary, low power scaled version of the LNA, phased appropriately using a current mirror, and subtracted from the main signal path by summing, thus providing a cancellation of the third order intermodulation (IM) terms in the main signal path leaving a signal remaining which is significantly more spectrally pure than the signal produced by the LNA before correction.

Abstract: Methods and systems for reducing parasitic capacitance of a buffer for an electric circuit are disclosed herein. Aspects of the method may comprise coupling a gate of a first transistor to a first differential input of the buffer and coupling a gate of a second transistor to a second differential input of the buffer. The first and second transistors may be biased by a common mode output of a direct current (DC) voltage source for the buffer, where the common mode output of the DC voltage source may be coupled to the gate of the first transistor and the gate of the second transistor. The first transistor and the second transistor may comprise NMOS transistors and/or PMOS transistors. The DC voltage source may comprise a PMOS transistor and/or an NMOS transistor.

Abstract: The present technique relates to a method and apparatus for operating a differential buffer. In the differential buffer, a first stage may include a differential pair configured to receive input signals and generate output signals. The first stage may also include adjustment circuitry coupled to the differential pair and configured to adjust an amount of current dissipated by the differential buffer. Further, a second stage may include current pulse circuitry coupled to the differential pair and the adjustment circuitry, wherein the current pulse circuitry is configured to generate a current pulse that is coincident with the switching of the differential pair. Finally, the second stage may also include grounding circuitry coupled to the current pulse circuitry and the differential pair, wherein the grounding circuitry is configured to receive the current pulse to prevent the output signals from switching during a transition of the output signals.

Abstract: An integrated differential receiver includes a single gate oxide differential receiver and an associated switchable voltage supply circuit. The integrated differential receiver determines the desired receiver supply voltage and selects a supply voltage for the single gate oxide differential receiver. When a lower supply voltage is determined as the desired supply voltage, the integrated differential receiver automatically provides a supply voltage to the single gate oxide differential receiver with a voltage higher than the I/O pad supply voltage and higher than the maximum input signal voltage to increase the speed of operation for the differential receiver. The switchable voltage supply circuit is operatively responsive to a control signal which indicates the desired supply voltage for the I/O pad. In one embodiment, both the single gate oxide differential receiver and the switchable voltage supply circuit are single gate oxide circuits.

Abstract: The two output currents (INP, IN) which are produced by a current source digital/analog converter (DAC) are supplied to the two halves of a symmetrical transimpedance amplifier. The input current (INP, IN) is supplied to a first stage, which is formed by a first transistor (N2), and a potential at the output of the first stage is supplied to a second stage, which is formed by a second transistor (N3), and the output voltage (VOUT, VOUTP) is formed by a potential at the output of the second stage. The output of the second stage is coupled to the output of the first stage through a Miller capacitor (Cm). The output of the transimpedance amplifier is coupled to its input by means of a connecting line which contains a feedback resistor (Rf).

Abstract: Provided is an amplifier circuit having a constant output swing range and a stable delay time, where the amplifier circuit includes a first bias unit, a second bias unit, a comparison unit, and an amplifier unit, and the first bias unit responds to an internal reference signal with a predetermined voltage level and maintains constant the amount of a first current, and the second bias unit receives an external reference signal, responds to a control voltage, and controls the amount of a second current to be the same as the amount of the first current, and the comparison unit compares a voltage level of a first node with a voltage level of a second node, and controls a voltage level of the control voltage according to the comparison result, and the amplifier unit compares a voltage level of an external input signal with a voltage level of the external reference signal, amplifies and outputs a voltage difference between the two compared signals, responds to the control voltage, and controls the amount of a third

Abstract: Methods and circuits for extracting a true mean of two signals are provided. A first amplifier input stage (e.g., an n-type stage) is operated when a mean of the two signals approaches an upper rail voltage. A second amplifier input stage (e.g., a p-type stage) is operated when the mean of the two signals approaches a lower rail voltage. A transitioning circuit controls how much each of the first and the second amplifier input stages contributes to an input of a high-gain amplifier output stage, when the mean of the two signal does not approach either of the rail voltages. An output of the high-gain amplifier output stage is fed back to both the first and second amplifier input stages via a feedback stage, which can be a matched buffer stage.

Abstract: A system for receiving signals (e.g., optical signals) includes an input device, an amplification device, and a feedback device. The amplification device receives a signal from the input device and includes a transimpedance portion. The transimpedance portion includes a first section having a plurality of elements (e.g., resistors and transistors) and a second section having a plurality of elements (e.g., resistors and transistors). One or more of the elements (e.g. transistors or resistors) in the first and second sections are mismatched to introduce a systematic offset in the transimpedance stage, to make the net input referred offset of the amplification device unidirectional. The feedback device (e.g. an integrator) is coupled to an output of the amplification device and an input of the transimpedance portion to provide a unidirectional offset correction to the amplification device for reduced noise enhancement.

Abstract: A pulse amplifier implemented in standard CMOS, comprises a control circuit for controlling a driver stage for driving a class D output stage that comprises a first PMOS-transistor and a first NMOS-transistor with interconnected drain contacts. A driver stage comprises a first driver and a second driver coupled with the output stage. Furthermore, a second NMOS transistor and second to fifth PMOS transistors are provided and interconnected in a way that most of the control signals needed to switch the high voltage output, specifically the drivers, are generated within a low voltage block. These factors contribute to lowering the total power dissipation.

Abstract: A protection circuit for extending the dynamic range of an amplifier circuit is described. Off-chip impedances, such as inductors, cause the output of the circuit to swing above and below the bias voltage. A protection circuit is included, either on-chip or off-chip, to protect the integrated circuit components if there is a fault condition in either of the off-chip impedances.

Abstract: A transistor has variation in a threshold voltage or mobility due to accumulation of factors such as variation in a gate insulating film which is caused by a difference of a manufacturing process or a substrate to be used and variation in a crystal state of a channel formation region. The present invention provides an electric circuit which is arranged such that both electrodes of a capacitance device can hold a voltage between the gate and the source of a specific transistor. Further, the present invention provides an electric circuit which has a function capable of setting a potential difference between both electrodes of a capacitance device so as to be a threshold voltage of a specific transistor.

Abstract: A system for receiving signals (e.g., optical signals) includes an input device, an amplification device, and a feedback device. The amplification device receives a signal from the input device and includes a transimpedance portion. The transimpedance portion includes a first section having a plurality of elements (e.g., resistors and transistors) and a second section having a plurality of elements (e.g., resistors and transistors). One or more of the elements (e.g. transistors or resistors) in the first and second sections are mismatched to introduce a systematic offset in the transimpedance stage, to make the net input referred offset of the amplification device unidirectional. The feedback device (e.g. an integrator) is coupled to an output of the amplification device and an input of the transimpedance portion to provide a unidirectional offset correction to the amplification device for reduced noise enhancement.

Abstract: In a multi-level output circuit, an amplifier circuit amplifies a constant input voltage and outputs the amplified constant input voltage. The multi-level output circuit is capable of selectively outputting signals of different levels by switching the gain of the amplifier circuit by a switch.

Abstract: A transmission channel for a subscriber line interface circuit comprises a front end, tip/ring current-sensing transimpedance stage, containing relatively low valued tip and ring sense resistors coupled in circuit with tip and ring paths of a telecommunication wireline pair. The front end transimpedance stage transforms differential tip and ring input currents sensed by the tip and ring sense resistors into a single ended voltage, which is coupled to a transconductance amplifier filter/gain stage. The filter/gain stage is configured to provide a programmable output impedance, and converts the voltage from the current-sensing transimpedance stage into an output transmission voltage for application to a selected one of a current-sense, voltage-feed, or voltage-sense, voltage-feed telecommunication circuit.

Abstract: A rail-to-rail operational amplifier to extract a true mean of two signals. The amplifier includes a first amplifier input stage adapted to operate when a mean of the two signals is near an upper rail voltage. A second amplifier input stage is adapted to operate when the mean of the two signals is near a lower rail voltage. A transitioning circuit is adapted to control how much each of the first and the second amplifier input stages contributes to an input of a high-gain amplifier output stage. An output of the high-gain amplifier output stage is fed back to both the n-type amplifier input stage and the p-type amplifier input stage via a matched buffer stage.

Abstract: Among the embodiments of the present invention is an apparatus that includes a transistor (30), a servo device (40), and a current source (50). The servo device (40) is operable to provide a common base mode of operation of the transistor (30) by maintaining an approximately constant voltage level at the transistor base (32b). The current source (150) is operable to provide a bias current to the transistor (30). A first device (24) provides an input signal to an electrical node (70) positioned between the emitter (32e) of the transistor (30) and the current source (50). A second device (26) receives an output signal from the collector (32c) of the transistor (30).

Abstract: A differential line driver includes first, second, third and fourth cascode transistors connected in parallel, wherein drains of the first and third transistors are connected to a negative output of the differential line driver, and wherein drains of the second and fourth transistors are connected to a positive output of the differential line driver. First, second, third and fourth switching transistors are connected in series with corresponding first, second, third and fourth cascode transistors and driven by a data signal. First and second compound transistors inputting a class AB operation signal at their gates, wherein the first compound transistor is connected to sources of the first and second switching transistors, and wherein the second compound transistor is connected to sources of the third and fourth switching transistors.

Abstract: A voltage follower comprising a first field-effect transistor (MN1) whose gate forms the input of the voltage follower. Further provided is a second field-effect transistor (MN2) whose drain connected to the gate forms the output of the voltage follower. The sources of the two field-effect transistors (MN1, MN2) are connected to each other and to the drain of a third field-effect transistor (MN3) serving as current source and to the gate of which a predefined bias voltage is applied. The invention employs in addition a fourth field-effect transistor (MN4) whose source-drain path is circuited between the output of the voltage follower and the drain of the third field-effect transistor (MN3) and whose gate is connected to the gate of the third field-effect transistor (MN3). As compared to prior art voltage followers the voltage follower in accordance with the invention comprises a wider voltage range in which it can be put to use. This can be made use of e.g.