Abstract: A differential pair of transistors receives input voltages. Current mirror transistors and cascode transistors are coupled to the differential pair of transistors. The differential pair of transistors is coupled between the cascode transistors and a tail transistor that draws a first bias current from a tail node, the first bias current having a magnitude equal to a product of a total bias current and a constant that is less than one. A first current source transistor draws a second bias current from a node between the differential pair and cascode transistors so the second bias current bypasses one transistor of the differential pair of transistors. The second bias current has a magnitude equal to a product of the total bias current and a value equal to one minus the constant. An output stage is biased by an output at node between the cascode transistors and the current mirror transistors.

Abstract: An amplifier includes a first coil coupled to at least one input node. The amplifier further includes second and third coils. A first terminal of the second coil is coupled to a source terminal of a first transistor, while a second terminal of the second coil is coupled to a source terminal of a second transistor. A third coil includes first and second terminals coupled to gate terminals of the first and second transistors, respectively. Responsive to receiving an input signal, the first coil electromagnetically conveys the signal to the second and third coils.

Abstract: A circuit includes an analog-to-digital converter (ADC). The circuit also includes an analog front end (AFE) having an AFE input and an AFE output. The AFE output is coupled the ADC's input. The AFE includes a programmable gain amplifier (PGA) having a first PGA input and a second PGA input. The PGA includes a first operational amplifier (OP AMP) with first and second OPAMP inputs. The AFE also including a programmable resistance circuit having a first programmable resistance circuit input and first and second programmable resistance circuit outputs. The first programmable resistance circuit input is coupled to the first and second PGA inputs. The programmable resistance circuit includes a resistor network having first and second balance resistances. The first balance resistance is coupled to the first and second OP AMP inputs, and the second balance resistance is coupled to the first and second OP AMP inputs.

Abstract: A semiconductor device includes a differential amplification circuit that outputs differential output signals Vo1 and Vo2, external output terminals PD1 and PD2 to which one of the differential output signals Vo1 and Vo2 and single end signals Vo3 and Vo4 is selectively supplied, switch units SW1 and SW2 that control a conduction state between the external output terminal PD1 and the feedback line and a conduction state between the external output terminal PD2 and the feedback line, respectively, resistance elements R1 and R2 respectively provided in series with the switch units SW1 and SW2, a CMFB circuit that controls a common mode voltage of the differential amplification circuit according to a difference between an intermediate voltage Vcm of the external output terminals PD1 and PD2 in the feedback line and a reference voltage Vref, and a switch unit SW3 that controls to supply a clamp voltage to the feedback line.

Abstract: One example includes a transconductor system. The system includes a first transconductance amplifier that generates a control current in response to a first input voltage. The system also includes a second transconductance amplifier that generates an output signal in response to a second input voltage. The system further includes an intermediate amplifier that generates a control voltage in response to the control current and a third input voltage. The control voltage can be provided to the first and second transconductance amplifiers to set a transconductance of each of the first and second transconductance amplifiers to be approximately equal.

Abstract: Described is an apparatus which comprises: an input sensing stage for sensing an input signal relative to another signal; a decision making circuit, coupled to the input sensing stage, for determining whether the input signal is a logic low or a logic high; and a power management circuit, coupled to the input sensing stage and the decision making circuit, which is operable to monitor a state of the decision making circuit and to disable the input sensing stage according to the monitored state. Described is an apparatus which comprises: a decision making circuit integrated with an input sensing stage, wherein the decision making circuit is operable to pre-charge its internal nodes during a phase of the clock signal; and a latching circuit to latch an output of the decision making circuit.

Abstract: A system for time aligning widely frequency spaced signals includes a digital predistortion (DPD) processor and a power amplifier coupled to the DPD processor and operable to provide a transmit signal at a power amplifier output. The system also includes a feedback loop coupled to the power amplifier output. The feedback loop comprises an adaptive fractional delay filter, a delay estimator coupled to the adaptive fractional delay filter, and a DPD coefficient estimator coupled to the delay estimator.

Abstract: A photoelectric conversion device includes a current consumption circuit configured to consume current such that a difference between a current consumption during a blanking period and a current consumption during a standby period is reduced.

Abstract: A compensation circuit of a power amplifier includes a varactor, a voltage sensor and a control circuit. The varactor is coupled to an input terminal of the power amplifier. The voltage sensor is arranged for detecting an amplitude of an input signal of the power amplifier to generate a detecting result. The control circuit is coupled to the varactor and the voltage sensor, and is arranged for controlling a bias voltage of the varactor to adjust a capacitance of the varactor according to the detecting result.

Abstract: A low noise amplifier includes an amplifier transistor having a source, a gate, and a drain. An input node is coupled to the gate. An output node is coupled to the drain. An inductor is coupled between the gate and the drain.

Abstract: Provided are an output buffer circuit having an amplifier offset compensation function and a source driving circuit including the output buffer circuit. The output buffer circuit may include a plurality of channel amplifiers, each of which is configured to adjust an amount of current flowing through transistors connected to at least one of a non-inverted input terminal and an inverted input terminal of a differential input unit to compensate an amplifier offset, and adjust buffer input voltage signals to generate output voltage signals.

Abstract: A circuit includes an oscillation generation circuit, a distribution circuit, and a transceiver circuit. The oscillation generation circuit is configured to generate a first oscillation signal having a first frequency. The distribution circuit includes a voltage to current stage, a transmission portion and a current to voltage stage. The voltage to current stage is configured to receive the first oscillation signal, and convert the first oscillation signal into a current form. The transmission portion is configured to transmit the first oscillation signal in the current form. The current to voltage stage is configured to receive the first oscillation signal in the current form and generate a second oscillation signal having a sub-harmonic frequency of the first frequency, such as half of the first frequency. The transceiver circuit is configured to operate in a frequency band responsive to the second oscillation signal.

Abstract: A continuous variable gain amplifier includes an attenuator network, a boost network, a first amplifying network, and a second amplifying network, where the attenuator network generates first differential output signals according to an input signal and sends the first differential output signals to the first amplifying network and the second amplifying network; the first amplifying network and the second amplifying network receive one output of the first differential output signals each, and generate a first final output signal and a second final output signal respectively according to an externally input control voltage; and the boost network receives the first final output signal and the second final output signal, generates second differential output signals, and sends a first output and a second output of the second differential output signals to the first amplifying network and the second amplifying network, respectively.

Abstract: An open loop envelope tracking system calibration technique and circuitry are proposed. A radio frequency power amplifier receives a modulated signal. An envelope tracker power converter generates a modulated power amplifier supply voltage for the radio frequency power amplifier based on a control signal derived from the modulated signal. A first output power and a second output power of the radio frequency power amplifier are measured when the control signal is respectively delayed by a first delay period and a second delay period. A sensitivity of the output power of the radio frequency power amplifier is near a maximum near the first delay period and the second delay period. The first delay period and/or the second delay period are adjusted until the first output power substantially equals the second output power. The first delay period and the second delay period are used to obtain a calibrated fine tuning delay offset.

Abstract: Disclosed herein is a power amplifier insensitive to load impedance changes. According to the present invention, the power amplifier comprises a power amplification circuit which amplifies an input signal, an output matching circuit connected to an output terminal of the power amplification circuit to perform impedance matching between the power amplification circuit and an antenna load, and a 4-port coupler connected between the output matching circuit and the antenna load.

Abstract: Some embodiments include apparatus and methods having a clock path with a combination of current-mode logic (CML) based and complementary metal-oxide semiconductor (CMOS) components.

Abstract: A programmable antenna includes a substrate, metallic inclusions, bidirectional coupling circuits, and a control module. The metallic inclusions are embedded within a region of the substrate. The bidirectional coupling circuits are physically distributed within the region and are physically proximal to the metallic inclusions. The control module activates a set of bidirectional coupling circuits, which, when active, the set of interconnects a set of metallic inclusions to provide a conductive area within the region. The conductive area functions an antenna.

Abstract: A driver utilizes selective biasing of the terminal of an operational amplifier to reduce offset in the operational amplifier output. Each operational amplifier input includes a differential input pair of transistors including a NMOS transistor and PMOS transistor. At low and high ends of the input voltage range these transistors are selectively and individually coupled to either a standard input or biased to be on so as to contribute offset for offset compensation. The transistors are biased in a conventional manner for input voltages between the low and high ends of the voltage range.

Abstract: Embodiments of the invention may provide systems and methods for minimizing phase deviation and/or amplitude modulation (AM)-to-phase modulation (PM) conversion for dynamic range, radio frequency (RF) non-linear amplifiers. In order to provide high dynamic range with reduced phase error, embodiments of the invention may utilize two separate paths for processing a signal. In particular, an input signal may be sampled and divided into each path. The first signal path may be used to shape a signal, and in particular, a voltage waveform at the load. The second signal path may be used for generating negative capacitances corresponding to the voltage waveform at the load. By combining the two signals at the load, a high-dynamic range, high-frequency, non-linear amplifier can be achieved that reduces phase error resulting from amplitude fluctuations with a relatively low unity-gain frequency (fT) process.

Abstract: A system to interface analog-to-digital converters to inputs with arbitrary common-modes includes a common-mode voltage amplifier circuit and a PGA circuit connected to the common-mode voltage amplifier circuit. The common-mode voltage amplifier and PGA circuits receive first and second analog input signals. The PGA circuit eliminates the arbitrary common-modes from the first and second analog input signals based on an output of the common-mode voltage amplifier circuit.

Abstract: A variable gain amplifier includes an integrator having an input, an output and a feedback loop connected between the input and output, a plurality of input chains connected in parallel between the amplifier input and the input of the integrator, each input chain including a resistor and a first switch and a plurality of second switches, each second switch connected between an intermediate node between the resistor and first switch of a respective input chain and the feedback loop of the integrator, wherein the resistance of the resistors in the input chains is scaled by a scaling factor with respect to one another and the on-resistances of the first and second switches connected to each intermediate node are scaled by the corresponding scaling factor.

Abstract: Disclosed herein is a power amplifier insensitive to load impedance changes. According to the present invention, the power amplifier comprises a power amplification circuit which amplifies an input signal, an output matching circuit connected to an output terminal of the power amplification circuit to perform impedance matching between the power amplification circuit and an antenna load, and a 4-port coupler connected between the output matching circuit and the antenna load.

Abstract: A known method for parallel two-way symmetrical signal transmission by means of an isolating interface with a differentiating circuit comprising a capacitive barrier is improved. When restarting communication in the selected direction after a longer break, a pilot signal is conducted via the transmitting plates for the communication in the reverse direction and capacitive compensators to one of the receiving plates for communication in the selected direction. Threshold levels for comparisons of the signals of the first and second time derivative are decreased, the capacitance of capacitive compensators is then set to reduce output the output signal and finally communication is reestablished. Transmitting plates for communication in the reverse direction are now connected to the receiving plates for communication in the selected direction through the capacitive compensators with the capacitance adjusted as described above.

Abstract: A method for digital compensation of a nonlinear system comprises identifying a plurality of circuit parameters of a nonlinear system. Each circuit parameter determines a nonlinear response of the nonlinear system. A first circuit parameter is chosen from the plurality of circuit parameters. The first circuit parameter determines a first effect on the nonlinear response. The first effect is at least as large a second effect from a second circuit parameter from the plurality of circuit parameters. At least one stimulus is applied to the nonlinear system. The nonlinear response of the nonlinear system is measured in response to the at least one stimulus. A compensation architecture is synthesized to substantially linearize the nonlinear response. The compensation architecture receives the nonlinear response of the nonlinear system and provides a substantially linear response.

Abstract: A method, amplifier and system are provided for enabling power recovery from a narrow-band antenna when a signal having bandwidth exceeding that of the antenna is utilized. The amplifier provides amplification of a source signal to the antenna and recovery of power stored in the antenna during periods when the impedance of the antenna is negative to enable reverse current through the amplifier to a direct current (DC) power source.

Abstract: A circuit comprises a control line and a two terminal semiconductor device having first and second terminals. The first terminal is coupled to a signal line, and the second terminal is coupled to the control line. The two terminal semiconductor device is adapted to have a capacitance when a voltage on the first terminal relative to the second terminal is above a threshold voltage and to have a smaller capacitance when a voltage on the first terminal relative to the second terminal is below the threshold voltage. The control line is coupled to a control signal and the signal line is coupled to a signal and is output of the circuit. A signal is placed on the signal line and voltage on the control line is modified (e.g., raised in the case of n-type devices, or lowered for a p-type devices). When the signal falls below the threshold voltage, the two terminal semiconductor device acts as a very small capacitor and the output of the circuit will be a small value.

Abstract: An integrated circuit allows for the correction of distortion at an input of a sampling network. The integrated circuit contains a first bootstrap circuit to drive a sampling network transistor and a second bootstrap circuit to separate the back-gate terminal of the transistor from a voltage input by a resistance inserted in series. The presence of the inserted resistance counteracts the effect of the nonlinear back-gate capacitance on the distortion at the input.

Abstract: A signal receiver includes a first input terminal, a second input terminal, a first transistor, a second transistor and a variable load. The first and the second transistors each include a gate electrode, a first electrode and a second electrode. The gate electrode of the first transistor is coupled to the first input signal terminal, the gate electrode of the second transistor is coupled to the second input signal terminal, and the variable load is coupled to the first electrode of the first transistor, where a resistance of the first variable load is adjusted to make a DC level at an output node of the signal receiver keep a constant value.

Abstract: A signal amplifier including a transformer with a primary winding and a secondary winding, an oscillator circuit driven by an input signal establishing in the primary winding an oscillating signal amplified by the secondary, and a rectifier circuit responsive to the secondary winding configured to convert the amplified oscillating signal to an amplified version of the input signal.

Abstract: The invention relates to an arrangement and method for estimating the linear and nonlinear parameters of a model 11 describing a transducer 1 which converts input signals x(t) into output signals y(t) (e.g., electrical, mechanical or acoustical signals). Transducers of this kind are primarily actuators (loudspeakers) and sensors (microphones), but also electrical systems for storing, transmitting and converting signals. The model describes the internal states of the transducer and the transfer behavior between input and output both in the small-and large-signal domain. This information is the basis for measurement applications, quality assessment, failure diagnostics and for controlling the transducer actively. The identification of linear and nonlinear parameters Pl and Pn of the model without systematic error (bias) is the objective of the current invention. This is achieved by using a transformation system 55 to estimate the linear parameters Pl and the nonlinear parameters Pn with separate cost functions.

Abstract: Embodiments of the present invention provide systems, devices and methods for detecting the RMS value of a signal. The RMS detector uses multiple variable-gain stages and internal gain control to generate an RMS output signal based on an arbitrary signal input. This RMS detector significantly reduces the signal swings seen on a squarer within prior art RMS detectors and reduces the detector's dependency on DC offsets at low signal levels and overload errors at high signal levels. The embodiments of the present invention also improve the accuracy of the RMS detector within large dynamic signal ranges by obviating the operation of a squarer in saturation or out of the squaring region. Accordingly, embodiments of the present invention are able to more accurately detect RMS values on a signal, operate over relatively higher signal ranges, and better function within different signal modulation schemes, particularly those with large peak-to-average ratios.

Abstract: An adjustable equalizer that includes a first branch including a low pass filter (LPF) and having a variable gain (?), and a second branch including a high pass filter (HPF) and having another variable gain (?). Outputs of the branches in response to an input signal are summed to produce an equalized output. The equalizer can be implemented using CMOS technology so that the gain parameters ? and ? are independently adjustable and the equalizer is capable of equalizing an input indicative of data having a maximum data rate of at least 1 Gb/s. Typically, the inventive equalizer is embodied in a receiver for use in equalizing a signal, indicative of video or other data, that has propagated over a serial link to the receiver.

Abstract: A switch including a first transistor including a first main terminal connected to a first switch node, a second main terminal connected to a second switch node and a control terminal, the second switch node being connected to a first clean voltage supply, and first control circuitry connected to the control terminal of the first transistor, including a first node connected to the first clean voltage supply, a second node connected to a second voltage level, and a control input node for receiving a first input control signal variable between a supply voltage level and a third voltage level, the first control means arranged to selectively connect the control terminal of the first transistor to one of the first node and the second node based on the first input control signal.

Abstract: A circuit providing a common voltage for a panel of a display includes a first operational amplifier, a second operational amplifier, a third operational amplifier, a capacitor and a switch circuit. The first operational amplifier outputs a first voltage. The second operational amplifier is powered by the first voltage and receives a polarity signal to output a second voltage. The third operational amplifier outputs a third voltage. The capacitor has a first end coupled to an output of the second operational amplifier and a second end coupled to an output of the third operational amplifier. The switch circuit couples the second end of the capacitor to the panel during a normal operation of the display, and couples one of a high constant voltage and a low constant voltage to the panel during a power saving operation of the display.

Abstract: The present invention relates to a gain control circuit, which detects an output signal of a front-end circuit to produce a detection signal. An operation unit performs an accumulation operation to the detection signal and thereby produces an operation signal. In addition, the operation unit also resets the operation unit according to a reset signal. A reset unit produces the reset signal for every predetermined interval of time. A control unit produces a control signal according to the operation signal and a first threshold value for controlling an output gain of the front-end circuit.

Abstract: A mixer having high linearity and an associated transconductor combining programmable gain amplifier and mixer functions are provided. The transconductor includes first and second resistors, a differential amplifier, first and second feedback circuits, and first and second transistors. A differential voltage signal is inputted to first and second input ends of the differential amplifier via the first and second resistors. The first and second feedback circuits are provided between a first output end and the first input end, and a second output end and the second input end of the differential amplifier, respectively. The first output end outputs a first output signal for controlling a first current passing through the first transistor. The second output end outputs a second output signal for controlling a second current passing through the second transistor. The first current and the second current determine a differential current.

Abstract: A power added efficiency optimizer apparatus is provided for measuring and monitoring input and output power of an amplifying device, and adjusting the load impedance seen by the amplifying device so that power added efficiency is maintained at optimum levels. A power added efficiency optimizing device includes a variable load impedance that can be controlled, at least one power detection device located after the load, a difference forming apparatus, and at least one coupling device. The power added efficiency optimizing device provides an ability to maintain an amplifier at peak efficiency in a dynamic way and in the presence of changing electromagnetic load conditions.

Abstract: A full-wave rectifier circuit receives complementary signals and produces a current corresponding to an added value of differential signals at different levels. A voltage comparator performs a comparison between output signals produced and subjected to current addition and voltage conversion by the full-wave rectifier circuit. A timer detects whether an output signal of the voltage comparator is kept in the same state for a predetermined time or more, and produces a signal indicating a result of the detection. A signal detecting circuit that can accurately identify a state of digital signals of a minute amplitude transferred through a pair of complementary signal lines is achieved without complicating manufacturing steps.

Abstract: A comparator comprises a differential amplifier (T1, T2, T8, T9) having differential inputs (IN1, IN2) forming the comparator inputs, and a first and a second amplifier output (f1, f2) forming the comparator outputs of a first comparator stage, wherein the differential amplifier has first (T1, T8) and second (T2, T9) parallel branches. The comparator has a first current source circuit (32) defines a current to be driven through the differential amplifier, a second current source circuit (34) comprising a load driven by the first branch and a third current source circuit (36), comprising a load driven by the second branch. Circuitry (T6,T7) is provided for defining the voltage difference between the first and second amplifier outputs when the differential amplifier is in a stable state providing a differential output. This arrangement drives current through the two branches independently, so that the main transistors in each branch can be kept on to enable rapid response times.

Abstract: A network having a current mirror comprising: a output transistor having a gate electrode for controlling a first current between a first electrode and a second electrode, the first electrode being coupled to a positive reference potential and the second electrode being connected to ground. A second transistor has a gate electrode for controlling a second current between a first electrode and a second electrode of the second transistor. The gate electrodes are connected together to produce the first current and the second current with equal current densities. A first portion of current from a current source is fed to the first electrode of the second transistor and a second portion of current from the current source is fed to a bias voltage producing circuit producing a bias voltage at the gate electrode of the output transistor for tracking variations in the first current passing through the output transistor.

Abstract: A power amplifier circuit that has an inductor and capacitor connected to one end of the output winding of an RF transformer. The other end of the output winding is connected to a resistor that in turn is connected to ground. The transformer has two primary windings. Both primary windings have one end connected to a variable DC voltage supply. The other end of each primary winding is attached to a switch, such as a MOSFET. All three windings are wound around a core. Current flowing from the DC voltage supply to the switches causes a magnetic flux in the core. A voltage is generated on the secondary winding resistor. This voltage is fed back to the switches, controlling on and off timing. In this way the need to measure and record natural frequency is eliminated.

Abstract: A semiconductor device stabilizes an operation of an input buffer. A semiconductor device includes an input potential detection unit, an input buffer, and a current sink unit. The input potential detection unit outputs a detection signal in response to a level of an input signal. The input buffer buffers the input signal by differentially amplifying the input signal through a first current sink unit. The current sink unit receives the detection signal, and in response to the detection signal, performs an auxiliary differential amplifying operation with respect to the input signal buffered by the input buffer.

Abstract: A signal isolator for providing at an output thereof representations of input currents from a source provided in an input conductor supported on a substrate having a bridge circuit suited for electrical connection to a source of electrical energization with a pair of series circuit members electrically connected in parallel with one another supported on a substrate with each series circuit member having a magnetoresistive member electrically connected in series with a current value controller, controlled at a controller terminal, at an output terminal of that controller. Each magnetoresistive members is electrically isolated from the input conductor and has a resistance versus applied external magnetic field characteristic that is substantially linear for at least relatively small externally applied magnetic fields.

Abstract: There is provided a transmitter including a nonlinear input-output conversion characteristic control unit configured to determine a nonlinear input-output conversion characteristic for converting a signal depending on a usage status of a frequency band; an amplitude control unit configured to convert an amplitude of the signal based on the determined nonlinear input-output conversion characteristic; and a transmission power amplification unit configured to amplify power of the signal with the converted amplitude.

Abstract: A channelized amplification system and method for mitigating non-linear amplification effects and controlling spectral re-growth is disclosed. A system includes an input frequency divider for converting a first signal into a plurality of frequency band signals and a plurality of channelized high-efficiency non-linear power amplifiers coupled to the frequency divider. Each of the plurality of frequency band signals occupies a frequency band that is different from one another. The plurality of channelized high-efficiency non-linear power amplifiers receive and amplify the plurality of frequency band signals and produce a plurality of non-linearly amplified signals. The system further includes a frequency combiner coupled to the plurality of channelized high-efficiency non-linear power amplifiers. The frequency combiner combines the plurality of amplified signals and produce a second signal. The system further includes an output band-pass filter coupled to the frequency combiner.

Abstract: An AC differential connection assembly between a trans-impedance amplifier and a post amplifier for burst mode receiving comprising means for coupling a differential output of the trans-impedance amplifier to a differential input of the post amplifier, the means for coupling comprises a coupling capacitor assembly; and a switching circuit coupled across the differential input of the post amplifier, the switching circuit having an ‘on’ state with low impedance and an ‘off’ state with high impedance; wherein during burst mode receiving, the switching circuit is in the ‘off’ state and the coupling capacitor assembly having a time constant to maintain a stable DC level such that a payload is received accurately by the differential input of the post amplifier; and during an idle period, the switching circuit is in the ‘on’ state and the coupling capacitor assembly having a time constant to recover a DC level of the differential output of the trans-impedance amplifier.

Abstract: An apparatus for generating a correction signal for linearizing an output signal of a non-linear element includes a correction signal generator. The correction signal generator is configured to generate a correction signal on the basis of a superposition of a digital reference signal and a superposed output signal. The superposed output signal is based on a superposition of the output signal and an analog reference signal.

Abstract: A semiconductor device stabilizes an operation of an input buffer. A semiconductor device includes an input potential detection unit outputting a detection signal in response to a level of an input signal. An input buffer buffers the input signal by performing a differential amplifying operation through a first current sink unit. A second current sink unit, sharing an output with the input buffer, differentially amplifies the input signal of the input buffer in response to a level of the detection signal.

Abstract: A variable gain amplifying apparatus has an amplifier, one or more first switching elements connected in parallel to the amplifier, and a phase shifter connected in series to the first switching element. The first switching element is enabled if the level of an input signal or an output signal is higher than a predetermined level, and the first switching element is disabled if the level of the input signal or the output signal is equal to or lower than the predetermined level. The amplifier does not operate when the first switching element is enabled, and the amplifier operates when the first switching element is disabled, and the amount of phase shift when the input signal is passed through the amplifier and phase shifter is substantially equal to the amount of phase shift when the input signal is passed through the first switching element.

Abstract: An output circuit includes a differential section configured to amplify an inputted differential signal; a current source section configured to supply a current to the differential section; a load resistance section connected with the differential section; and a control unit configured to set a value of the current from the current source section and a resistance value of the load resistance section based on a signal supplied to the control unit. The output circuit converts the differential signal into an output signal of a different interface level from that of the differential signal and balance-transmits the output signal.