With Differential Amplifier Patents (Class 327/563)
  • Patent number: 12028025
    Abstract: An amplifier with temperature compensation where the amplifier has transistors configured to amplify a received signal to create an amplified signal. The amplifier gain changes over temperature. A gain control circuit, connected to the amplifier, that adjusts the amplifier gain responsive to a gain control signal. A temperature compensation circuit includes numerous elements. A constant current source that generates a constant current which is used to create a constant voltage. A temperature dependent current source that generates a temperature dependent current which is used to create a temperature dependent voltage, such that the temperature dependent current source has an inverse temperature dependance as compared to the amplifier. An operational amplifier compares the constant voltage to the temperature dependent voltage and generates an offset signal which varies over temperature. A gated buffer is configured to receive the offset signal and responsive thereto, selectively modify the gain control signal.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: July 2, 2024
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventor: John R. Francis
  • Patent number: 11967624
    Abstract: Abnormal generation of heat of a power MOSFET is detected to improve the reliability of a semiconductor device. As its means, in a power MOSFET having a drain electrode on the side of a back surface of a semiconductor substrate and a source pad on the side of a main surface of the semiconductor substrate, two gate pads electrically connected to a gate pad connected to a gate electrode of the power MOSFET are formed on the side of the main surface of the semiconductor substrate. Further, there is provided a voltmeter connected in parallel with each of two current paths which connect the two gate pads and a gate driver.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: April 23, 2024
    Assignee: HITACHI, LTD.
    Inventors: Naoki Tega, Digh Hisamoto, Takeru Suto
  • Patent number: 11843376
    Abstract: A system containing a host and a device having a field-programmable gate array (“FPGA”) is disclosed. The system includes a set of configurable logic blocks (“LBs”), a bus, and a Universal Serial Bus (“USB”) interface. The configurable LBs, in one aspect, are able to be selectively programmed to perform one or more logic functions. The bus contains a P-channel and an N-channel operable to transmit signals in accordance with a high-speed USB protocol. The USB interface is configured to include a first differential comparator operable to identify a logic zero state at the P-channel and a second differential comparator operable to identify a logic zero state at the N-channel.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: December 12, 2023
    Assignee: Gowin Semiconductor Corporation
    Inventor: Grant Thomas Jennings
  • Patent number: 11831287
    Abstract: A method for removing offset in a receiver of an integrated circuit (IC) includes: determining digital codes of differential input voltages of an amplifier in a first receiving lane of the receiver; comparing the digital codes to a digital code corresponding to an optimum common mode voltage (VCM) of the receiver; according to the comparison, determining a bias code for adjusting both the differential input voltages to match the optimum VCM; and inputting the bias code to a bias circuit of the receiver. The first receiving lane of the receiver includes a plurality of amplifiers. The method steps are repeated for each amplifier of the plurality of amplifiers, and then repeated for all receiving lanes of the IC.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: November 28, 2023
    Assignee: Faraday Technology Corp.
    Inventors: Prateek Kumar Goyal, Raghu Nandan Chepuri, Vinod Kumar Jain
  • Patent number: 11668807
    Abstract: A sensor system is disclosed for sensing the position of an object. The system can include a power source and a nullification circuit electrically connected to the power source, the nullification circuit including an output voltage. An electrical medium can be integrated into the nullification circuit, the electrical medium producing a standing wave electric field about the electrical medium when power is supplied from the power source to the electrical medium. The nullification circuit is configured such that the output voltage of the nullification circuit is substantially zero when power is supplied to the electrical medium and the object is not within a predetermined minimum distance from the electrical medium, the output voltage of the nullification circuit having a non-zero value when the object is within the predetermined minimum distance from the electrical medium.
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: June 6, 2023
    Assignee: Tennessee Technological University
    Inventors: Charles W. VanNeste, Charles A. Robinson, Brandon J. Childress
  • Patent number: 11626846
    Abstract: Differential amplifier circuitry including: first and second main transistors of a given conductivity type; and first and second auxiliary transistors of an opposite conductivity type, where the first and second main transistors are connected along first and second main current paths passing between first and second main voltage reference nodes and first and second output nodes, respectively, with their source terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by component input signals of a differential input signal; and the first and second auxiliary transistors are connected along first and second auxiliary current paths passing between first and second auxiliary voltage reference nodes and the first and second output nodes, respectively, with their drain terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by the component input signals of the differential input signal.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: April 11, 2023
    Assignee: SOCIONEXT INC.
    Inventors: Armin Jalili Sebardan, Alistair John Gratrex
  • Patent number: 11509335
    Abstract: A radio frequency (RF) multiplexer circuit is provided. The multiplexer includes a first circuit coupled between a first input terminal and a first output terminal. The first circuit is configured and arranged to transfer a first RF signal coupled at the first input terminal to the first output terminal as a first output signal when a first control signal is at a first logic value. The multiplexer includes a second circuit coupled between a second input terminal and the first output terminal. The second circuit is configured and arranged to transfer a second RF signal coupled at the second input terminal to the first output terminal as a second output signal having a gain higher than the gain of the second RF signal when the first control signal is at a second logic value.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: November 22, 2022
    Assignee: NXP USA, INC.
    Inventor: Yi Yin
  • Patent number: 11476816
    Abstract: An amplifier device and a duplexer circuit are provided. The amplifier device includes a first differential amplifier circuit and a controller. The first differential amplifier circuit includes first and second radio frequency (RF) input terminals, first and second transistors, first and second adjustable capacitor circuits, and first and second RF output terminals. The controller adjusts capacitance values of the first adjustable capacitor circuit of the first differential amplifier circuit and the second adjustable capacitor circuit of the first differential amplifier circuit according to at least one of a characteristic related to a first RF input signal of the first differential amplifier circuit, a characteristic related to the second RF input signal of the first differential amplifier circuit, a matching deviation between the first transistor and the second transistor of the first differential amplifier circuit, and a characteristic of the amplifier device.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: October 18, 2022
    Assignee: RichWave Technology Corp.
    Inventors: Yu-Chun Donald Lie, Chuan-Chen Chao
  • Patent number: 11451201
    Abstract: The present invention is directed to electrical circuits. More specifically, an embodiment of the present invention provides a variable impedance module with a first capacitor coupled to a first input terminal and the second capacitor coupled to a second input terminal. A diode bridge is connected between the input capacitors. The anodes of the top diodes are connected to a supply through a resistor, and the cathodes of the lower diodes are connected to a high-impedance current source. A third capacitor is connected between these two nodes.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: September 20, 2022
    Assignee: MARVELL ASIA PTE LTD.
    Inventors: James Hoffman, Florin Pera
  • Patent number: 11360200
    Abstract: A sensor system is disclosed for sensing the position of an object. The system can include a power source and a nullification circuit electrically connected to the power source, the nullification circuit including an output voltage. An electrical medium can be integrated into the nullification circuit, the electrical medium producing a standing wave electric field about the electrical medium when power is supplied from the power source to the electrical medium. The nullification circuit is configured such that the output voltage of the nullification circuit is substantially zero when power is supplied to the electrical medium and the object is not within a predetermined minimum distance from the electrical medium, the output voltage of the nullification circuit having a non-zero value when the object is within the predetermined minimum distance from the electrical medium.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: June 14, 2022
    Assignee: Tennessee Technological University
    Inventors: Charles W. VanNeste, Charles A. Robinson, Brandon J. Childress
  • Patent number: 11152063
    Abstract: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: October 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chung H. Lam, Scott C. Lewis, Thomas M. Maffitt, Jack Morrish
  • Patent number: 11121687
    Abstract: Disclosed herein is a circuit including a differential amplifier having a pair of input transistors coupled in a differential arrangement between adjustable current sources and receiving input differential signals from a pair of input voltage regulators. The adjustable current sources are configured to source more current to the pair of input transistors than current that is sunk from the pair of input transistors. A first amplifier has inputs coupled to receive differential output voltages from the differential amplifier. A second amplifier has inputs coupled to receive amplified differential output voltages from the first amplifier. A low pass filter has inputs coupled to receive further amplified differential output voltages from the second amplifier and produce final differential output voltages.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: September 14, 2021
    Assignee: STMicroelectronics International N.V.
    Inventors: Riju Biswas, Ratul Mitra
  • Patent number: 11043918
    Abstract: A power amplifier circuit includes a first transistor having an emitter electrically connected to a common potential, a base to which a first high-frequency signal is input, and a collector from which a third high-frequency signal is output; a second transistor having an emitter electrically connected to the common potential, a base to which a second high-frequency signal is input, and a collector from which a fourth high-frequency signal is output; a first capacitance circuit electrically connected between the collector of the second transistor and the base of the first transistor; and a second capacitance circuit electrically connected between the collector of the first transistor and the base of the second transistor.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: June 22, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Satoshi Arayashiki, Satoshi Goto, Yusuke Tanaka
  • Patent number: 10965277
    Abstract: Inter-integrated circuit input circuitry includes a pull-up current circuit and an input circuit. The input circuit includes an output inverter, an input inverter, and a pull-up circuit. The pull-up circuit is coupled to an input of the input inverter, and includes a pull-up transistor and a cascode transistor. The pull-up transistor is coupled to the input of the input inverter. The cascode transistor is coupled to the pull-up current circuit and the pull-up transistor, and configured to isolate the pull-up transistor from capacitance of a conductor coupled to the pull-up current circuit and the input circuit.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: March 30, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Mark Allan Shill
  • Patent number: 10756512
    Abstract: A driving circuit includes a first transistor that includes a first terminal, a second terminal, and a third terminal; a second transistor having a fourth terminal, a fifth terminal, and a sixth terminal; and an output portion that outputs a signal between the second transistor and a second current source to a light emitting element, wherein the first terminal is coupled to a first power source, a signal is input to the second terminal, and the third terminal is grounded through a first current source which is different from the second current source, and the fourth terminal is coupled to a second power source which is the same as or different from the first power source via the second current source, the fifth terminal is coupled to a voltage source or a bias circuit, and the sixth terminal is coupled between the first transistor and the first current source.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: August 25, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Yukito Tsunoda
  • Patent number: 10734985
    Abstract: In certain aspects, a comparator includes a first inverter having an input, an output, and a voltage supply input, wherein the input of the first inverter and the output of the first inverter are coupled together, and the voltage supply input of the first inverter is configured to receive a first compare voltage. The comparator also includes a second inverter having an input, an output, and a voltage supply input, wherein the input of the second inverter is coupled to the output of the first inverter, and the voltage supply input of the second inverter is configured to receive a second compare voltage.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: August 4, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Byron Murphy, Glenn Murphy, Rajeev Jain
  • Patent number: 10615190
    Abstract: A method includes coupling a low gain input of a dual stage comparator to establish a low conversion gain mode. An analog-to-digital (ADC) operation is performed to determine a low gain reset voltage. A low gain input is decoupled in response to a DCG control signal. A high gain input is coupled to establish a high conversion gain mode in response to the DCG control signal. The ADC operation is performed with the high gain input to determine a high gain reset voltage. The ADC operation is performed with the high gain input to determine a high gain signal voltage. The high gain input is decoupled in response to a DCG control signal transition. The low gain input is recoupled in response to the DCG control signal, and the ADC operation is performed with the low gain input to determine a low gain signal voltage.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: April 7, 2020
    Assignee: OmniVision Technologies, Inc.
    Inventor: Hiroaki Ebihara
  • Patent number: 10431608
    Abstract: Example comparators as discussed herein may include a second stage coupled to provide an output in response to an intermediate voltage, a first stage coupled to provide the intermediate voltage in response to an input. The first stage including a pair of cascode devices coupled to a current mirror, a low gain input coupled to inputs of the first stage via first switches, and further selectively coupled to the pair of cascode devices via second switches, and a high gain input coupled to the first and second inputs of the first stage via the first switches, and further selectively coupled to the pair of cascode devices via fourth switches.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: October 1, 2019
    Assignee: OmniVision Technologies, Inc.
    Inventor: Hiroaki Ebihara
  • Patent number: 10305467
    Abstract: A radio frequency switch circuit includes: a radio frequency switch configured to control a radio frequency signal passing between a signal port and an antenna port; a first buffer configured to generate the first control voltage in response to a second control voltage; a second buffer configured to receive a third control voltage and configured to generate the second control voltage in response to the third control voltage; a first power supplier configured to supply a first high voltage to the first buffer and configured to supply a second high voltage to the second buffer; and a second power supplier configured to supply a first low voltage to the first buffer and configured to supply a second low voltage to the second buffer.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: May 28, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Yoo Hwan Kim, Jong Mo Lim, Yoo Sam Na, Hyun Jin Yoo, Hyun Hwan Yoo
  • Patent number: 10305436
    Abstract: A power-efficient neutralized signal amplifier for use in ultra-low power narrowband receiver applications. A neutralized signal amplifier having: an impedance transformation element coupled to an amplifier input and having a differential output; a gain cell, having a differential input and a differential output, the differential input coupled to the differential output of the impedance transformation element and the differential output coupled to the amplifier output; and a neutralization element coupled to the gain cell differential output and cross-coupled to the differential output of the impedance transformation element, where the coupling of the neutralization element to the differential output of the impedance transformation element provides that the input impedance of the neutralized signal amplifier is substantially determined by reflected resistive parasitics of the impedance transformation element.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: May 28, 2019
    Assignee: Sunrise Micro Devices, Inc.
    Inventor: Anthony Kresimir Stampalia
  • Patent number: 9819315
    Abstract: A power-efficient neutralized signal amplifier for use in ultra-low power narrowband receiver applications. A neutralized signal amplifier having: an impedance transformation element coupled to an amplifier input and having a differential output; a gain cell, having a differential input and a differential output, the differential input coupled to the differential output of the impedance transformation element and the differential output coupled to the amplifier output; and a neutralization element coupled to the gain cell differential output and cross-coupled to the differential output of the impedance transformation element, where the coupling of the neutralization element to the differential output of the impedance transformation element provides that the input impedance of the neutralized signal amplifier is substantially determined by reflected resistive parasitics of the impedance transformation element.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: November 14, 2017
    Assignee: SUNRISE MICRO DEVICES, INC.
    Inventor: Anthony Kresimir Stampalia
  • Patent number: 9806686
    Abstract: The present invention is directed to electrical circuits and techniques thereof. More specifically, an embodiment of the present invention provides a variable gain amplifier that includes a first transistor and a second transistor whose gate terminals are coupled to a first input terminal. A first drain terminal of the first transistor and a first source terminal of the second transistor is coupled to a voltage gain control switch. There are other embodiments as well.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: October 31, 2017
    Assignee: INPHI CORPORATION
    Inventor: Guojun Ren
  • Patent number: 9712195
    Abstract: An amplifier includes a gain transistor including a control terminal to receive an input signal. A degeneration inductor is coupled between the first terminal of the gain transistor and ground. A shunt inductor and a capacitor are coupled in series between the control terminal of the gain transistor and ground, and form a filter to attenuate frequencies of the input signal within a frequency range. The degeneration inductor and the shunt inductor form a transformer to provide impedance matching.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: July 18, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Cheng-Han Wang, Conor Donovan, Jesse Aaron Richmond, Jin-Su Ko
  • Patent number: 9691120
    Abstract: The interface circuit is provided with: a differential output circuit in which the output of a potential level of a differential signal stabilizes after a prescribed period from a start signal; and a counter circuit that performs control in such a manner that a data processing operation of a data processing unit is not performed on a signal based on the differential signal during the prescribed period. Thus, a liquid crystal display device that is capable of preventing a distorted video from being displayed in an initial drive period can be achieved.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: June 27, 2017
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Masahiro Imai
  • Patent number: 9692372
    Abstract: A class D audio amplifier provides both an audio output signal and a DC bias voltage to an electrostatic transducer (9). In the amplifier, a modulated sequence of pulses is generated by an input module (1) in response to an input audio signal. The sequence of pulses is amplified by an output module (3) using high speed switching output transistors (4, 5). An output signal is generated by applying a low pass filter (8) to the amplified pulses, and the output signal is provided to the transducer to produce audible output. The amplified sequence of pulses is also used to drive a voltage multiplier module (10) to provide bias voltage for the electrostatic transducer (9). In other embodiments, the bias voltage is provided by a bias voltage module which reverses the bias voltage at intervals, and a phase reverser (13) reverses the phase of the signals fed to the output module (3) simultaneously with reversal of the bias voltage.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: June 27, 2017
    Assignee: Warwick Audio Technologies Limited
    Inventors: Brian Atkins, Duncan Billson, David Hoare
  • Patent number: 9659606
    Abstract: The present invention provides a differential sensing circuit with a dynamic voltage reference for a single-ended bit line memory is disclosed. The exemplary differential sensing circuit comprises: a dynamic voltage reference generating unit and a differential sensing amplifying unit. The dynamic voltage reference generating unit is coupled to an input voltage, and utilized for receiving a setting signal to generate the dynamic voltage reference. The differential sensing amplifying unit is coupled to the single-ended bit line memory and the dynamic voltage reference generating unit, and utilized for receiving at least an input signal from the single-ended bit line memory and the dynamic voltage reference from the dynamic voltage reference generating unit, so as to generate at least an output signal accordingly.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: May 23, 2017
    Assignee: MediaTek Inc.
    Inventors: Shih-Huang Huang, Rei-Fu Huang
  • Patent number: 9536937
    Abstract: When writing a signal current from a current source to a current source circuit, noise occurs in some cases in a wiring through which a current flows, which may cause a potential of the wiring to be outside the normal range. As the potential does not turn back within the normal range easily at this time, writing to the current source circuit is delayed. According to the invention, when the potential becomes outside the normal range due to noise occurring in a wiring through which a current flows when writing a signal current from a current source to a current source circuit, a current is supplied from other than the current source, thereby the potential of the wiring can turn back within the normal range rapidly.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: January 3, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Yu Yamazaki
  • Patent number: 9508759
    Abstract: To reduce adverse effect of variations in threshold voltage. A semiconductor device includes a transistor including a gate connected to one electrode of a capacitor and one terminal of a SW1, a source and a drain one of which is connected to one terminal of a SW2 and one terminal of a SW3 and the other of which is connected to the other terminal of the SW1 and one terminal of a SW4; a first wiring electrically connected to the other terminal of the SW2; a second wiring electrically connected to the other terminal of the SW4; a load including electrodes one of which is connected to one electrode of the capacitor and the other terminal of the SW3; and a third wiring connected to the other electrode of the load.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: November 29, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 9472138
    Abstract: A pixel circuit for use in a display comprising a plurality of pixels is provided. The load-balanced current mirror pixel circuit can compensate for device degradation and/or mismatch, and changing environmental factors like temperature and mechanical strain. The pixel circuit comprises a pixel drive circuit comprising, switching circuitry, a current mirror having a reference transistor and a drive transistor, the reference transistor and the drive transistor each having a first and second node and a gate, the gate of the reference transistor being connected to the gate of the drive transistor; and a capacitor connected between the gate of the reference transistor and a ground potential, and a load connected between the current mirror and a ground potential, the load having a first load element and a second load element, the first load element being connected to the first node of the reference transistor and the second load element being connected to the first node of the drive transistor.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: October 18, 2016
    Assignee: Ignis Innovation Inc.
    Inventors: Arokia Nathan, Kapil V. Sakariya, Peyman Servati, Shahin Jafarabadiashtiani
  • Patent number: 9397614
    Abstract: An apparatus includes a first capacitor, an inductor coupled to the first capacitor, and a second capacitor coupled to the inductor. The second capacitor is coupled to a first output of a differential amplifier.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: July 19, 2016
    Assignee: Qualcomm Incorporated
    Inventors: Saihua Lin, Anup Savla
  • Patent number: 9391598
    Abstract: A sample-and-hold circuit including a transistor and a capacitor is connected to the differential circuit. The sample-and-hold circuit acquires voltage for correcting the offset voltage of the differential circuit by charging or discharging the capacitor through sampling operation. Then, it holds the potential of the capacitor through holding operation. In normal operation of the differential circuit, the output potential of the differential circuit is corrected by the potential held by the capacitor. The transistor in the sample-and-hold circuit is preferably a transistor whose channel is formed using an oxide semiconductor. An oxide semiconductor transistor has extremely low leakage current; thus, a change in the potential held in the capacitor of the sample-and-hold circuit can be minimized.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: July 12, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroki Inoue, Kei Takahashi, Tatsuya Onuki
  • Patent number: 9350421
    Abstract: A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: May 24, 2016
    Assignee: Rambus Inc.
    Inventors: John W. Poulton, Frederick A. Ware, Carl W. Werner
  • Patent number: 9214927
    Abstract: A relaxation oscillator shares charging current and comparator biasing current between just two current sources, thereby relaxing requirements on total supply current. The resulting reduction in power consumption has no adverse effect on the speed and accuracy of the oscillator. A switching arrangement directs charging and biasing currents between the two current sources and two charging capacitors and their associated comparators.
    Type: Grant
    Filed: November 30, 2014
    Date of Patent: December 15, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Zhengxiang Wang
  • Patent number: 9184780
    Abstract: A transceiver includes a power amplifying circuit, a first balance-unbalance circuit, a switchable matching circuit, and a low-noise amplifying circuit. The power amplifying circuit generates differential output signals during a transmitting mode of the transceiver. The first balance-unbalance circuit converts the differential output signals into a single-ended output signal. The switchable matching circuit receives the single-ended output signal on a signal port of the transceiver during the transmitting mode, and converts a single-ended receiving signal on the signal port into a single-ended input signal during a receiving mode of the transceiver. The low-noise amplifying circuit converts the single-ended input signal into a low-noise input signal during the receiving mode.
    Type: Grant
    Filed: April 19, 2015
    Date of Patent: November 10, 2015
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventors: Ti-Ku Yu, Sang Won Son, Chia-Hsin Wu, Tsung-Ming Chen, Wei-Chia Chan
  • Patent number: 9178647
    Abstract: A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: November 3, 2015
    Assignee: RAMBUS INC.
    Inventors: Yohan U. Frans, Hae-Chang Lee, Brian S. Leibowitz, Simon Li, Nhat M. Nguyen
  • Patent number: 9160309
    Abstract: An area efficient baseband filter is disclosed. In an exemplary embodiment, an apparatus includes a current to voltage (I-V) filter configured to receive an input current signal at an input port and generate a filtered output voltage signal at an output port based on a feedback transconductance. The input current signal comprises an input DC current in addition to a signal current. The apparatus also includes a feedback circuit connected between the output port and the input port, the feedback circuit having at least one transistor configured to couple the input DC current to a signal ground and to provide the feedback transconductance for the I-V filter.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: October 13, 2015
    Assignee: Qualcomm Incorporated
    Inventors: Gireesh Rajendran, Rakesh Kumar, Vinod Venugopal Panikkath, Ayush Mittal, Alok Joshi
  • Patent number: 9131179
    Abstract: A solid-state imaging device and a camera system are disclosed. The solid-state imaging device includes a pixel unit and a pixel signal readout circuit. The pixel signal readout circuit includes a plurality of comparators disposed to correspond to a pixel column array, and a plurality of counters. Each counter includes a first amplifier, a second amplifier, and a mirror circuit to from a current mirror in parallel with the second amplifier. The first amplifier includes differential transistors, initializing switches connected between gates and collectors of the differential transistors, and first and second capacitors connected to each of the gates of the differential transistors. The second amplifier includes an initializing switch and a third capacitor. The mirror circuit includes a gate input transistor whose gate is inputted with a voltage sampled by the first amplifier or a voltage sampled by the second amplifier.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: September 8, 2015
    Assignee: Sony Corporation
    Inventor: Kenichi Tanaka
  • Patent number: 9077290
    Abstract: A low-noise amplifier (300) is provided which comprises an input circuit (301) configured to operate with a variable bias current and an impedance boosting circuit (314) electrically connected to the input circuit (301). The impedance boosting circuit (314) comprises at least one switch (316) and at least one tail inductor (318) electrically connected with the at least one switch (316). The low-noise amplifier (300) is configured to activate the impedance boosting circuit (314) if the variable bias current is reduced, and the impedance boosting circuit (314) is configured to increase the input impedance of the low-noise amplifier (300) if the impedance boosting circuit (314) is activated.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: July 7, 2015
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventors: Imad ud Din, Henrik Sjöland
  • Patent number: 8957709
    Abstract: A driver circuit including front and rear amplifiers each powered by the primary and secondary power supplies, where the latter power supply is generated from the former power supply. The rear amplifier includes a cascade transistor whose base bias is provided from the bias source. The bias source provides the base bias to reduce the base current when the primary power supply is active but the secondary power supply is inactive, and to be equal to the primary power supply when two power supplies become active but the rear amplifier is inactive.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: February 17, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Naoki Itabashi, Keiji Tanaka
  • Patent number: 8942313
    Abstract: An open loop envelope tracking system calibration technique and circuitry are proposed. A radio frequency power amplifier receives a modulated signal. An envelope tracker power converter generates a modulated power amplifier supply voltage for the radio frequency power amplifier based on a control signal derived from the modulated signal. A first output power and a second output power of the radio frequency power amplifier are measured when the control signal is respectively delayed by a first delay period and a second delay period. A sensitivity of the output power of the radio frequency power amplifier is near a maximum near the first delay period and the second delay period. The first delay period and/or the second delay period are adjusted until the first output power substantially equals the second output power. The first delay period and the second delay period are used to obtain a calibrated fine tuning delay offset.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: January 27, 2015
    Assignee: RF Micro Devices, Inc.
    Inventors: Nadim Khlat, Karl Francis Horlander
  • Patent number: 8884690
    Abstract: An input buffer receiver circuit for electronic devices (e.g., memory chips) to receive reduced-swing and high bandwidth inputs to provide “buffered” output signals having symmetrical rising and falling delays, and without additional current dissipation over previous receiver circuits, is disclosed. The receiver circuit may include two differential amplifier pair stages (i.e., 4 total differential amplifiers). The first stage of differential amplifiers convert the single-ended input signal to a full-differential signal, which is converted back to a single-ended output signal by the second stage of differential amplifiers. The output of a P-diff first stage may be connected to the input of an N-diff second stage and the output of an N-diff first stage may be connected to the input of a P-diff second stage thereby creating a “cross coupled” structure. Various current saving and biasing methods may also be employed to keep operating current the same or lower than previous designs.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: November 11, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Dong Pan, Timothy B. Cowles
  • Patent number: 8829985
    Abstract: According to one embodiment, a time difference amplifier circuit includes the first amplifier including first positive and negative inputs and first positive and negative outputs, the second amplifier including second positive and negative inputs and second positive and negative outputs, first to fourth wirings, a selection circuit including the first selection element connecting the first or fourth wirings to the second positive input, and the second selection element connecting the second or third wirings to the second negative input, and a control circuit connecting the amplifiers by the first and second wirings or by the third and fourth wirings.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: September 9, 2014
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Kiichi Niitsu, Naohiro Harigai, Masato Sakurai, Haruo Kobayashi
  • Patent number: 8786316
    Abstract: A method and circuit for attenuating positive feedback in a comparator in one embodiment includes an amplifier configured to compare a first input signal with a second input signal and to provide an output based upon the comparison, a non-linear function with a first input operably connected to an output of the amplifier, and a feedback loop operably connected to the output of the non-linear function and to a second input of the non-linear function, the feedback loop including a feedback limiting circuit configured to attenuate a feedback signal to the second input of the non-linear function.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: July 22, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Robert Wolf, Christoph Lang, Xinyu Xing, Sam Kavusi
  • Patent number: 8773174
    Abstract: A rail to rail differential buffer input stage includes n-type and p-type input differential transistor pairs connected in voltage follower configuration to the power supply rails. A reference voltage generator includes a reference differential transistor pair generating a dynamic reference voltage relative to the common mode input voltage. Dummy n-type and p-type transistor pairs have current conducting paths connected in parallel with the input differential pairs and are controlled by the dynamic reference voltage to divert supply rail current away from and deactivate one of the associated input differential pairs when the common mode input voltage is further from the dynamic reference voltage than a threshold value. Both the dummy pairs conduct and both the input differential pairs are activated when the common mode input voltage is closer to the dynamic reference voltage VB than the threshold value so that the overall transconductance of the buffer input stage remains constant.
    Type: Grant
    Filed: December 16, 2012
    Date of Patent: July 8, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yang Wang, Jianzhou Wu, Xiuqiang Xu, Yizhong Zhang
  • Patent number: 8749275
    Abstract: A differential circuit includes a first input part; a second input part; a reference voltage input part, the reference voltage input part being common to form differential pairs; a current source that drives the differential pairs; a current mirror that generates a first output current and a second output current, according to a current that flows through the reference voltage input part according to at least one voltage difference of first and second voltage differences; a first output part that outputs a signal according to the first voltage difference, according to a current that flows through the first input part according to the first voltage difference and the first output current; and a second output part that outputs a signal according to the second voltage difference, according to a current that flows through the second input part according to the second voltage difference and the second output current.
    Type: Grant
    Filed: September 5, 2011
    Date of Patent: June 10, 2014
    Assignee: Mitsumi Electric Co., Ltd.
    Inventor: Fumihiro Inoue
  • Patent number: 8705637
    Abstract: A signal transmission device including: a differential signal transmission unit having two output terminals for outputting a differential signal to a paired signal lines including first and second signal lines; a single-ended signal transmission unit having two output terminals for outputting independent two-channel single-ended signals to the paired signal lines; and a filter unit having first and second common mode filters. One terminal of the differential signal transmission unit and one terminal of the single-ended signal transmission unit are connected to the first signal line via one inductor of the first common mode filter of the filter unit. The other one terminal of the differential signal transmission unit and the other one terminal of the single-ended signal transmission unit are connected to the second signal line via one inductor of the second common mode filter of the filter unit.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: April 22, 2014
    Assignee: Panasonic Corporation
    Inventors: Osamu Shibata, Hiroshi Suenaga
  • Patent number: 8674755
    Abstract: A differential amplifier comprising a first upper device and a first lower device series coupled between two power supplies and a second upper device and a second lower device series coupled between the two power supplies. A first DC voltage enables the first upper device and the second upper device and a second DC voltage regulates current flow in the first lower device and the second lower device. An AC signal component is coupled to the first upper device and the second lower device while the AC signal complement is coupled to the first lower device and the second upper device. Separate RC networks couple the AC signals to their respective device. A first and second output signal forms between the upper device and the lower device, respectively. All the devices are same channel type.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: March 18, 2014
    Assignee: Tensorcom, Inc.
    Inventor: Zaw Soe
  • Patent number: 8659349
    Abstract: A control circuit for use with a four terminal sensor, the sensor having first and second drive terminals and first and second measurement terminals, the control circuit arranged to drive at least one of the first and second drive terminals with an excitation signal, to sense a voltage difference between the first and second measurement terminals, and control the excitation signal such that the voltage difference between the first and second measurement terminals is within a target range of voltages, and wherein the control circuit includes N poles in its transfer characteristic and N?1 zeros in its transfer characteristic such that when a loop gain falls to unity the phase shift around a closed loop is not substantially 2? radians or a multiple thereof, where N is greater than 1.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: February 25, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Colin Lyden, Donal Bourke, Dennis A. Dempsey, Dermot G. O'Keeffe, Patrick Kirby
  • Patent number: RE47461
    Abstract: A differential amplifier circuit includes a first differential transistor pair, a second differential transistor pair, an adder section and an amplifying unit. The first differential transistor pair receives first and second input signals and an output signal as a third input signal, and the second differential transistor pair receives the first and second input signals and the output signal as a fourth input signal. The adder section adds first output signals from the first differential transistor pair and second output signals from the second differential transistor pair, and the amplifying unit amplifies an addition resultant signal from the adder section to output to the first and second differential transistor pairs.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: June 25, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Kouichi Nishimura, Atsushi Shimatani
  • Patent number: RE48576
    Abstract: To reduce adverse effect of variations in threshold voltage. A semiconductor device includes a transistor including a gate connected to one electrode of a capacitor and one terminal of a SW1, a source and a drain one of which is connected to one terminal of a SW2 and one terminal of a SW3 and the other of which is connected to the other terminal of the SW1 and one terminal of a SW4; a first wiring electrically connected to the other terminal of the SW2; a second wiring electrically connected to the other terminal of the SW4; a load including electrodes one of which is connected to one electrode of the capacitor and the other terminal of the SW3; and a third wiring connected to the other electrode of the load.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: June 1, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura