Abstract: An improved integrated circuit conductor layout technique provides lower and upper conductor levels that bound circuit blocks and provide for power supply voltage distribution to the circuitry in the circuit blocks. The lower and upper conductor levels also provide for first and second groups of parallel signal conductors in wiring channels between circuit blocks. An intermediate conductor level is located between the lower and upper conductor levels, and conducts power supply voltages between adjacent circuit blocks. The power supply conductors formed in the intermediate conductor level also serve to isolate the signal conductors in the lower conductor level from the signal conductors in the upper conductor level (and vice-versa) in the wiring channel. This isolation typically improves the design of the integrated circuit by providing more reliable estimates of signal propagation in the wiring channels.

Abstract: A clock distribution network for distributing a clock signal across a VLSI chip. A H-tree is combined with an x-y grid to allow buffering of the clock signal, while minimizing clock skew across the chip. The H-tree distributes a plurality of repower buffer levels above a final repower buffering level. The output of the final level are coupled by the x-y grid to minimizes clock skew caused by the chip and by local loading variations in the circuits.

Abstract: An output driver including pull-up and pull-down output transistors is formed in a silicon substrate. The source and the drain of the pull-up output transistor are formed in a common bulk region of the substrate. A bulk potential control circuit for controlling the voltage of the bulk region, a resistive element and a gate drive control circuit are also formed in the silicon substrate. A layer of interconnect formed over a top surface of the silicon substrate may selectively couple into the output driver circuit one or more of the resistive element between a source of the pull-down output transistor and a reference voltage source, the bulk potential control circuit to control the voltage of the bulk region of the silicon substrate, and the gate drive control circuit to control the rate of change of voltage on the gate of the pull-down transistor as a function of the voltage on this gate.

Abstract: A power semiconductor device (4) has a main current carrying section (4a) with a number of parallel-connected active device cells (5) and a first main electrode (6) coupled to a first terminal (2), a second main electrode (7) connected to a second terminal (3) and a control electrode (8) and a sense current carrying section (4b) with at least one sense cell (5a) similar to the active device cells (5) and having a first main electrode (6) coupled to the first terminals (2) and a second main electrode (9). A current sensing arrangement (10) has a first resistor (R1) coupling the second main electrode (9) of the sense current carrying section (4b) to the second terminal (3), a second resistor (R2) similar to the first resistor (R1) and a current source (11) coupled in series with the second resistor to the second terminal (3) for supplying a reference current (Ir) through the second resistor (R2).

Abstract: A monolithic upconverter integrated circuit is described which performs the first frequency conversion of a dual conversion cable television (CATV) receiver. The upconverter chip includes three functional blocks: a Gilbert type image-rejecting mixer, a phase splitter, and a voltage-controlled oscillator. Mixing is performed by a novel Gilbert type mixer including image-rejection inductors to improve the noise figure of the mixer. A differential circuit topology allows the monolithic upconverter chip to utilize a plastic dual inline batwing package without considerable performance loss. On-chip RF bypass networks, in the form of series RC terminations, also help compensate for the undesirable effects of pin inductances in the dual inline package. A resistor-based DC biasing scheme dramatically reduces power-up latency, allowing faster testing.

Abstract: In order to reduce noise in a controlling circuit including digital circuitry and analog circuitry constructed together on a single CMOS integrated circuit, a regulator is constructed as part of the integrated circuit. A power supply is directly connected to the digital circuitry, and a voltage output of the regulator is supplied to the analog circuitry. The output state of the regulator may be controlled by a switch. Degradation of the performance characteristics of the analog circuitry while the digital circuitry is being operated can be prevented by electrically isolating the power supply to the digital circuitry from the power supply to the analog circuitry. Since the regulator is built into the integrated circuit, the number of externally provided components is thereby reduced, further contributing to the downsizing of an electronic device such as a camera. Furthermore, even when the power supply of the digital circuitry fluctuates greatly, the effects on the analog circuitry are minimized.

Abstract: An integrated circuit device is provided, in which optimization design can be made for a short term to suppress power consumption of the integrated circuit device and improve the maximum operation frequency. First basic cells and second basic cells are disposed in a first direction. The second basic cells are the same in circuit function other than load driving capability as the first basic cells and the same in the cell width in the first direction and relative positions of input and output terminals. The first and second basic cells preferably contain MOS transistors, respectively, whose gate widths in the direction perpendicular to the cell width are made different from each other.

Abstract: A lead frame with separate noisy and quiet V.sub.SS leads terminating in a single pin and separate noisy and quiet V.sub.DD leads terminating in a single pin. Each noisy lead portion has a line width greater than its corresponding quiet lead portion to reduce noise in the quiet lead portion. Further, line lengths of the noisy and quiet lead portions for the V.sub.SS leads are made longer than the noisy and quiet lead portions for the V.sub.DD leads, or in other words the paddle is moved toward the V.sub.SS leads to reduce ground bounce. Additionally, the noisy and quiet leads overlie a floating conductive plane to further reduce inductance.

Abstract: An integrated circuit has at least one input terminal and at least one output terminal, respectively, for receiving and transmitting digital and/or analog signals, being associated with discrete circuit portions of the integrated circuit which implement different logic functions. Advantageously, such terminals are coincident with a single pin, and an electronic circuit is arranged within the integrated circuit to detect the logic state of the pin.

Abstract: Array circuitry formed at a surface of a substrate includes a first conductive layer with M scan lines, a second conductive layer with N data lines, and cell circuitry for a region in which the mth scan line and the nth data line cross. The cell circuitry includes a component with a data lead for receiving signals from or providing signals to the nth data line. A first semiconductor layer of the cell circuitry includes a first line with a channel between a connecting point to the nth data line and a connecting point to the component's data lead. A second semiconductor layer includes a second line extending from a connecting point to the mth scan line and crossing the first line at the channel. The first and second conductive layers and the cell circuitry are formed with electrical connections at the connecting points so that signals on the mth scan line control conductivity of the first line between the nth data line and the data lead. The semiconductor layers can be polysilicon.

Abstract: In a semiconductor device comprising on a semiconductor substrate (41) first and second input buffers (21), first and second input signal connections (25) supplying the input buffers from input signal pads (23) with input signals, respectively, each with a buffer input level, and first and second reference signal connections (29) supplying a reference signal from a reference signal pad (27) to the input buffers with buffer reference levels, respectively, a grounding pad (71) is laid near the reference signal pad and supplied with a ground level for the semiconductor device with a capacitor (73) connected between the semiconductor substrate and each reference signal connection near the reference signal pad and preferably with the reference signal connections laid geometrically parallel to the input signal connections.

Abstract: A semiconductor integrated circuit has a P-type substrate and a plurality of PN-junction isolated islands of N-type, a first one of the islands may contain a power device which during certain periods of operation causes the first island to become forward biassed and to inject electrons into the substrate. Collection of these injected charges by a second island at one side of the injecting island is reduced by a separate protective bipolar transistor formed in a third N-type island. The third island is preferably interposed between the injecting island and the islands to be protected, but may be located anywhere with respect to the injecting transistor. The emitter of the protective transistor is electrically connected to an N-type portion of the first island. The collector of the protective transistor is connected to the P-type isolation-wall portion of the substrate located between the injecting transistor and the small islands to be protected.

Abstract: The present invention provides an apparatus for altering an electrical signal between a first device and a second device. The apparatus includes a support structure or interconnection member having at least two surfaces with a plurality of contacts on each surface. The contacts are arranged in a predesignated pattern to mate with the conductors of each of the devices. In a typical application, the apparatus will be used to connect a microprocessor powered by approximately 3.3 V to a printed circuit board of a system using a power supply of approximately 5.0 V.

Abstract: A bipolar semiconductor integrated circuit for driving a motor and the like wherein a semiconductor pattern and a circuit are so contrived that an erroneous operation will not take place even when a negative potential is applied to the output terminal of the circuit. When a negative potential is applied, there exists a quantitative proportional relationship between a parasitic current of a parasitic transistor and a ratio of the lengths of the collectors. The parasitic current decreases with a decrease in the length of the collector. Therefore, the short side of a transistor in the control circuit is directed to the output transistor to which a negative potential will be applied. By detecting the parasitic current and by adding a current to the constant-current using a current mirror circuit, furthermore, erroneous operation due to parasitism can be completely prevented.

Abstract: The invention concerns an analog amplifier constructed using digital transistors. The digital transistors are those contained in a gate array, and which are used for fabrication of digital devices. The analog amplifier includes an invertor, which contains two cascode amplifiers in series. The analog amplifier also includes a differential amplifier. The invertor is contained within the feedback circuit of the differential amplifier.

Abstract: Power output switching circuit (215) for use in high current and high frequency applications. The output circuit provides a series of geometrically symmetric parallel spaced semiconductor converters (214A, 214B, 216A, 216B) arranged such that the voltage for each semiconductor output device is substantially equal and minimal for each device. In this way, each device exhibits substantially the same impedance, such that circuit performance is largely a function of intrinsic device characteristics, and substantially independent of cross coupling and another external influences.

Abstract: A charge transfer device having an improved signal stage is disclosed. This stage includes a floating region formed in a semiconductor layer and receiving signal charges from a charge transfer stage, a reset drain region formed in the semiconductor layer adjacently to the floating region, a reset gate for resetting the floating drain region in potential to the reset drain region, an absorption region formed in the semiconductor layer adjacently to the reset drain region, a barrier gate supplied with a constant voltage to form a channel region between reset drain region and the adsorption region, and a charge injection source connected to the reset drain region to inject charges thereinto.

Abstract: In a semiconductor device including a clock driver which provides clock signals, a plurality of electronic elements which are operable in timed relation to the clock signals, are provided a plurality of circumferentially-wired, lattice-shaped wiring blocks to which the electronic elements are connected and each of which has a center portion, and an interconnecting wiring pattern connected to the center portion. The interconnecting wiring pattern connects the clock driver with the center portion of each circumferentially-wired, lattice-shaped wiring block so that a distance between the clock driver and each center portion is substantially equal to one another in the center portions.

Abstract: In an electronic system such as an integrated circuit having a number of destination loads such as logic gates, signal is distributed along typically a zero'th level (e.g., polysilicon) electrical transmission line from an input terminal to the destination loads. The characteristics of the signal arriving at the destination loads are improved by (1) inserting an added electrical transmission line, and (2) connecting various nodes of the added electrical transmission line through auxiliary active devices, such as inverters, to various nodes on the zero'th level electrical transmission line. In one attractive arrangement, each of the auxiliary active devices has an electrical-current-drive capability that increases monotonically with the number of nodes intervening between it and the input terminal of the added electrical transmission line.

Abstract: An input cell for a semiconductor chip having an I/O region proximate the edge of the chip and a core region located inside the I/O region. The input cell is located in the I/O region and includes an input pad for receiving an input signal and a multiplexer. The multiplexer receives an input signal from the pad or a boundary scan signal from the core region and selectively provides one signal or the other to the core region.

Abstract: In a communications system having a plurality of stations interconnected by a two-line circuit, in which the two-line circuit consists of a data bus circuit for transmitting a series of data bits between at least one sending station and at least one receiving station of the plurality of stations and a clock bus circuit for transmitting clock signals in synchronism with each of the data bits; the data bus circuit sends a signal or a command requesting the receiving station to enter a standby or an execute state after taking in data supplied, while a logic value on the clock bus circuit is fixed. In more detail, the sending station transmits signals to make at least one of the receiving stations enter the standby state after taking in data and then sends data to another receiving station, after which the sending station sends a signal or command to make both the first and second receiving stations simultaneously enter the execute state.

Abstract: An interface circuit for interfacing between an integrated circuit (IC) on a transmitting side and an IC on a receiving side over a line on a printed circuit board comprises an output circuit implemented in the IC on the transmitting side and composed of a current source for supplying a given current and a switching circuit for cutting off the given current according to a binary signal and delivering the given current as a current signal to the line, and an input circuit implemented in the IC on the receiving side and composed of a transimpedance circuit whose input impedance is equal to the one of the line and which converts the current signal into a voltage signal, and a comparator for identifying the voltage signal relative to a given threshold voltage and reproducing the binary signal. This circuitry makes it possible to provide an interface circuit that can be implemented in a CMOS IC during CMOS processing and operated at a low voltage.

Abstract: An apparatus for enabling an IC pin to function in a dual mode, which apparatus includes a first switch for coupling the IC pin to an input terminal when the IC pin operates in an input mode, and a charging circuit for sourcing current to the IC pin during a charging cycle of a timer mode. The inventive apparatus further includes a discharging circuit for sinking current from the IC pin during a discharging cycle of the timer mode. In one embodiment, the inventive apparatus further includes a comparator for generating an activation signal, the activation signal being activated when a potential at the IC pin equals or exceeds a predefined voltage in the timer mode. In another embodiment, the comparator is disabled during the input mode.

Abstract: An automotive sensor arrangement including an automotive sensor coupled via first and second wires to signal sensor evaluation means, a signal conditioning circuit comprising a first gate means connected to provide a bias operating voltage signal on said first wire to the sensor, a second gate means of similar construction to the first gate means and mounted in the same environment and first gate means, the second gate means being coupled to the second wire of the leas means for receive the voltage signal bears a predetermined relationship to the switching point voltage of the second gate means.

Abstract: An environmental sensor integrated with high current drive device is provided. An environmental sensor is fabricated on a semiconductor substrate using conventional MOS process used for N-well CMOS logic and DMOS power transistors. An N-well is preferably used as a junction etch stop for micromachining of mechanical sensor components. A high voltage P-type region is used to electrically isolate the high current device from the sensor device. By locating the sensor device away from the high current drive device on a common semiconductor substrate, good performance can be achieved from the sensor even while the high current device dissipates a large amount of power.

Abstract: A biasing circuit (30) for an output vertical pnp transistor (10) formed in an integrated circuit and having an outer epitaxial region (20) includes a biasing vertical pnp transistor (33) and a comparator (38). Biasing circuit (30) is electrically connected to the integrated circuit voltage supply and the outer epitaxial region (20) of the output vertical pnp transistor (10) for electrically connecting the outer epitaxial region (20) to the voltage supply when the voltage at an output terminal (23) does not exceed the supply voltage and electrically disconnecting the outer epitaxial region (20) from the voltage supply when the voltage at the output terminal (23) exceeds the supply voltage, whereby improper operation of and damage to the integrated circuit upon the occurrence of an external fault condition is at least minimized.

Abstract: A high speed sampler comprises a meandered sample transmission line for transmitting an input signal, a straight strobe transmission line for transmitting a strobe signal, and a plurality of sampling gates along the transmission lines. The sampling gates comprise a four terminal diode bridge having a first strobe resistor connected from a first terminal of the bridge to the positive strobe line, a second strobe resistor coupled from the third terminal of the bridge to the negative strobe line, a tap connected to the second terminal of the bridge and to the sample transmission line, and a sample holding capacitor connected to the fourth terminal of the bridge. The resistance of the first and second strobe resistors is much higher than the signal transmission line impedance in the preferred system. This results in a sampling gate which applies a very small load on the sample transmission line and on the strobe generator.

Abstract: A multi-chip module is composed of two or more integrated-circuit chips located on a substrate such as a dielectrically coated silicon substrate. The chips are interconnected by means of transmission wiring lines. At least some of the chips contain one or more input buffer circuits, each composed of two branches ("legs"). Each such branch contains, in one embodiment, an n-channel MOS transistor connected in series with a pair of series-connected p-channel MOS transistors--whereby, in each such branch, one of the p-channel MOS transistors is located between (intermediate) the other of the p-channel MOS transistors and the n-channel MOS transistor of that same branch. On the other hand, in each buffer circuit, the intermediate p-channel MOS transistors of both branches are cross-coupled.

Abstract: An integrated circuit chip has both digital and analog circuit functions, with one or more islands for isolating the analog functions from noise caused by the digital functions. An island is defined by a surrounding heavily-doped region in the face of the chip. The voltage supplies for an analog island are isolated from the digital supply voltage for high frequencies by using resistive decoupling in series along with capacitive coupling to ground. Similarly, series resistive decoupling and capacitive coupling to ground are employed for the analog input signal lines going to the island. Analog signals generated within the island are coupled to the area outside the island on the chip face by either converting to digital in an A-to-D converter, or by a differential arrangement which accounts for differences that may exist between digital and analog supply voltages.

Abstract: A semiconductor integrated circuit has a parallel conductor transmission line including a plurality of signal paths branching at a node. The signal paths have phase compensation section for obtaining a phase constant of the transfer constant thereof, the phase constant being inversely proportional to the length of the signal paths. The phase compensation section is implemented by covering a microstrip line by a insulator layer having a high dielectric constant or implemented by a second ground conductor disposed opposite to the microstrip conductor with a thin insulator layer of a high dielectric constant. The integrated circuit comprises a plurality of square gate blocks having a plurality of logic gates arranged in an array. A signal source node is connected via respective input signal nodes of the gate blocks to the logic gates in the gate blocks through the respective signal paths having the phase compensation section.

Abstract: Provided on the periphery of a semiconductor chip are a clock input pad 10 and a clock driver 11. Clock pulse generators 13A to 13G are provided to functional blocks 12A to 12F. A clock signal line 14, through which clock signals are transmitted to the clock pulse generators 13A to 13G, is composed of a first clock line 14a extending from the clock driver 14 to the center of the semiconductor chip, and a plurality of second clock lines branching, at the center of the semiconductor chip, from the leading end of the first clock line to extend to the clock pulse generators 13A to 13G respectively.

Abstract: In this invention, in arranging a balance type input terminal group or output terminal group in an integrated circuit, the formation is provided with one terminal for grounding and two signal terminals adjacent to this grounding terminal on both sides. In connecting the output terminal group of the first integrated circuit and the input terminal group of the second integrated circuit with each other in such formation, the grounding terminals themselves and signal terminals themselves are respectively connected in one to one. Further, in the integrated circuit formed as mentioned above, among the bonding wires connecting the balance type input terminal group or output terminal group with an electrode group of an inner chip, the two bonding wires connecting the chip with the signal terminals are wired symmetrically with the bonding wire connecting the chip with the grounding terminal as a center.

Abstract: A trace having a closed periphery interconnect topology. The closed periphery interconnect topology can take the form of a substantially circular, oval, square, or polygon loop. An electrical signal driven onto the trace propagates in both clockwise and counter-clockwise directions around the loop. Series terminations can be implemented to optimize performance by providing better matching.

Abstract: A semiconductor integrated circuit device has a first wire for transmitting a first signal and a second wire adjacent to the first wire, for transmitting a second signal having the stronger probability of having an opposite phase to that of the first signal. A space between the first and second wires is wider than a standard wiring space, to reduce a delay in the operation speed of the device due to wiring capacitance produced between the first and second wires.

Abstract: A semiconductor integrated circuit device includes a plurality of integrated circuit chips and a large-sized integrated circuit element on which the plurality of integrated circuit chips are mounted. The large-sized integrated circuit element includes a logic circuit for electrically interconnecting the integrated circuit chips mounted on it. The logic circuit provided within the large-sized integrated circuit element includes a control circuit for controlling a connection relation between the integrated circuit chips mounted on the large-sized integrated circuit element. Further, the logic circuit includes buffer or latch circuits for relaying signals transmitted between the integrated circuit chips.

Abstract: An output driver circuit capable of driving its data output terminal to a digital logic level high, capable of driving its data output terminal to a digital logic level low, and capable of tristating its data output terminal has an output stage comprising a pullup field effect transistor (FET) and a like-polarity pulldown FET. The two pullup and pulldown FETs are coupled in series between two voltage supply lines. In one aspect of the invention, the output driver comprises a charge rate control circuit which charges the gate of the pulldown FET when the pulldown FET is to be turned on so that the voltage on the gate increases at a first rapid rate and then increases at a second slower rate after the pulldown FET begins to conduct current. In another aspect of the invention, a resistive element is provided between the source of the pulldown FET and a ground voltage supply line.

Abstract: Internal to the transistor, an additional, direct connection is made from the internal collector to the external collector of the transistor by a fixed shunt inductance. The external power supply V.sub.s is applied to the transistor collector through an adjustable external shunt element. The adjustable external shunt element allows the user to finetune the impedance matching circuit such that the transformation ratio of the output matching circuitry is minimized.

Abstract: A composite semiconductor capacitor element, applicable to various kinds of circuits to reduce the influence of parasitic capacitance therein, includes two semiconductor capacitor elements connected in parallel by connecting terminals which have parasitic capacitances to terminals which do not have parasitic capacitances. Alternatively, two such semiconductor capacitor elements are connected in series by connecting terminals which have parasitic capacitances to each other. Hence, parasitic capacitances at the respective terminals are equal to each other. In addition, as compared with a conventional structure wherein a greater number of parasitic capacitances are connected to one terminal than to the other terminal, the parasitic capacitances are smaller at each terminal side.

Abstract: A semiconductor integrated circuit is operative in a plurality of different modes. A plurality of select signals whose number corresponds to modes selected from a plurality of different modes are outputted. In response to the select signals, it is detected whether at least two operation modes are selected simultaneously. If so, a detection signal is outputted. In response to this detection signal, the operation of the semiconductor integrated circuit is stopped. Further, in response to the select signal, the semiconductor integrated circuit is activated in a mode by means of a predetermined select signal of these select signals. Further, in response to these select signals, the selected mode can be detected.

Abstract: A device including a MOS power transistor, and a temperature sensor including a bipolar transistor integrated in the MOS transistor and having its emitter and collector connected directly to the source and gate terminals respectively of the MOS transistor. Parallel to the base-emitter junction of the bipolar transistor, there is connected a voltage source for biasing the junction to such a value that the bipolar transistor remains off at room temperature, and absorbs the maximum current supplied by a drive circuit of the MOS transistor at the maximum permissible temperature TUM. At temperature TUM, the bipolar transistor takes over control of the gate-source voltage of the MOS transistor for maintaining thermal feedback of the device at maximum temperature TUM.

Abstract: A monolithically integrated circuit in the packed state has at least one characteristic value and/or at least one function which is able to be varied by applying at least one striking potential to at least two of the standard terminal connections leading to the outside of the integrated circuit.

Abstract: An integrated circuit chip has terminals comprising an input terminal, an output terminal to be connected to a load, a power supply terminal to be connected to the positive terminal of a power supply, and a ground terminal to be connected to ground potential (car body). A ground-side common line is associated with the internal circuitry of the integrated circuit chip, and a current-limiting resistor is connected between the ground-side common line and the ground terminal. A diode is connected in parallel with the resistor to limit a surge voltage. The diode is connected with its anode connected to the ground-side common line and its cathode connected to the ground terminal.

Abstract: An integrated circuit having an adjusting component and an adjustable thyristor allows an especially small chip surface to be used. The integrated circuit has a control unit, by means of which the adjusting component is irreversibly switched. The thyristor is designed as a planar component.

Abstract: A bipolar transistor is provided in which the base-emitter junctions do not traverse the base but terminate inside the top surface of the base. The transistor has long emitter perimeter available for current flow and more than two emitter sides (e.g., three sides) available for current flow, which allows obtaining a low base resistance, a low emitter resistance, a low collector resistance, a low base-collector capacitance, and a small size.

Abstract: A selectable timing delay system which provides for delaying an input signal a specified length of time within a specified tolerance wherein the range and resolution of the selectable timing delay system are so specified that the selected delay within the selected tolerance is obtainable regardless of the relative speed of the integrated circuit chips used in forming the selectable timing delay system.

Abstract: Integrated circuits in which a phase difference between the external and internal clocks can be reduced by decreasing transistor stages from the input of an external clock to the output of an internal clock drive stages and also noise can be reduced which is generated when the clock driver drives at a high speed the internal clock having a heavy load and the noise can be prevented from propagation to other portions to avoid having a bad effect on other circuits, and further the internal clock having the same phase can be supplied to each part of the chip even at a high operating frequency by minimizing skew of the internal clock signal on the chip and still further a demand current can be reduced by eliminating a passing current of the internal clock signal driver.

Abstract: A method and semiconductor structure are provided for intermixing circuits of two or more different cell classes, such as standard cells and gate array cells, on a common chip or substrate with minimum gound rule separation between adjacent cells of different classes. Cell locations are defined with given boundaries and contiguously arranged on the surface of a semiconductor chip, and then either standard cell type or gate array type circuits are formed within any of the cell locations to provide a structure for balancing chip density and performance versus hardware turn-around-time.

Abstract: A system for reducing power in electronic systems blocks current paths by electrically isolating idle, targeted devices through switching off the various device's entire sets of pins from the rest of the electronic system. Solid state switches are connected to every pin of a targeted device. In one logic state a control signal will turn the switches on and thereby connect the targeted device to the remainder of the system. In another logic state, the control signal will isolate the targeted device.