Integrated Structure Patents (Class 327/564)
  • Patent number: 11009407
    Abstract: According to one embodiment, a semiconductor device 1 includes a temperature sensor module 10 that outputs a non-linear digital value with respect temperature and a substantial linear sensor voltage value with respect to the temperature, a storage unit 30 that stores the temperature, the digital value, and the sensor voltage value, and a controller 40 that calculates a characteristic formula using the temperature, the digital value, and the sensor voltage value stored in the storage 30, in which the temperature, the digital value, and the sensor voltage value stored in the storage unit 30 include absolute temperature under measurement of absolute temperature, the digital value at the absolute temperature, and the sensor voltage value at the absolute temperature.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: May 18, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masanori Ikeda, Tadashi Kameyama
  • Patent number: 10971636
    Abstract: A photoelectric detection structure, a manufacturing method therefor, and a photoelectric detector. The photoelectric detection structure includes: a base substrate; an electrode strip, which is located on the base substrate; a semiconductor layer, which is located at a side of the base substrate that faces the electrode strip; an insulating layer, which is located between the electrode strip and the semiconductor layer, the insulating layer including a thickness-increased portion, and the thickness-increased portion being located on at least one edge of the electrode strip.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: April 6, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Zhanjie Ma
  • Patent number: 10886921
    Abstract: Examples described herein generally relate to multi-chip devices having stacked chips. In an example, a multi-chip device includes a chip stack including a base chip and two or more overlying chips overlying the base chip. Neighboring chips of the chip stack are connected to each other. The chip stack includes identification generation connections and circuits configured to generate a unique identification of each overlying chip based on a relative position of the respective overlying chip with reference to the base chip. The chip stack includes a communication channel from the base chip to each overlying chip. Each overlying chip includes comparison and enable/disable logic (CEDL) communicatively coupled to the communication channel. The CEDL is configured to compare a target identification of data received by the respective overlying chip to the unique identification of the respective overlying chip and responsively enable or disable a recipient circuit of the respective overlying chip.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: January 5, 2021
    Assignee: XILINX, INC.
    Inventors: Vijay Kumar Koganti, Anil Kumar Kandala, Santosh Yachareni
  • Patent number: 10734196
    Abstract: Provided is an impedance matching device for matching an impedance between a high-frequency power source and a load. The impedance matching device pertaining to the present invention is provided with: a matching circuit having variable capacitors, a capacitance of which is adjusted by an ON/OFF operation of a plurality of switches; a switch control unit for performing control for causing states of the switches of the variable capacitors to coincide with a target state in order to adjust the capacitance of the variable capacitors; and a switch state evaluation unit for evaluating whether a switch is in a state requiring suppression of a temperature increase. The switch control unit is configured so that when the switch state evaluation unit evaluates that a switch of the variable capacitors is in a state requiring suppression of a temperature increase, control is performed for suspending changing of a switch state of the switch for a set period and suppressing a temperature increase in the switch.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: August 4, 2020
    Assignee: DAIHEN Corporation
    Inventors: Tatsuya Morii, Masayuki Nakahama
  • Patent number: 10573718
    Abstract: A vertical, high-voltage MOS transistor, which has a source region, a body contact region, and a number of trenches structures with field plates, and a method of forming the MOS transistor increase the on-state resistance of the MOS transistor by reducing the trench pitch. Trench pitch can be reduced with metal contacts that simultaneously touch the source regions, the body contact regions, and the field plates. Trench pitch can also be reduced with a gate that increases the size of the LDD region.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: February 25, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Christopher Boguslaw Kocon, Simon John Molloy, John Manning Savidge Neilson, Hideaki Kawahara
  • Patent number: 10243621
    Abstract: Tightly-coupled near-field transmitter/receiver pairs are deployed such that the transmitter is disposed at a terminal portion of a first conduction path, the receiver is disposed at a terminal portion of a second conduction path, the transmitter and receiver are disposed in close proximity to each other, and the first conduction path and the second conduction path are discontiguous with respect to each other. In some embodiments of the present invention, close proximity refers to the transmitter antenna and the receiver antenna being spaced apart by a distance such that, at wavelengths of the transmitter carrier frequency, near-field coupling is obtained. In some embodiments, the transmitter and receiver are disposed on separate substrates that are moveable relative to each other. In alternative embodiments, the transmitter and receiver are disposed on the same substrate.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: March 26, 2019
    Assignee: Keyssa, Inc.
    Inventor: Gary D. McCormack
  • Patent number: 9996126
    Abstract: The present application is directed at pin programming od controllers for power converters and provides for the programming of a plurality of different controller parameters using a single programming resistor. The value of the programming resistor is used as a pointer to select a table storing a plurality of different settings for the controller.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: June 12, 2018
    Assignee: ROHM Powervation Limited
    Inventors: Karl Rinne, Antoin Russell
  • Patent number: 9871020
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to intelligent through silicon via sharing in 3D-IC integrated structures and methods of manufacture. The structure includes: a plurality of stacked dies each containing at least one macro device; and a layer structure positioned between the plurality of stacked dies which comprises a control structured to route signals between the at least one macro device of a first stacked die and the at least one macro device of a second stacked die of the plurality of stacked dies.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: January 16, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sebastian T. Ventrone, Sudeep Mandal
  • Patent number: 9754902
    Abstract: An integrated circuit including a plurality of first semiconductor strips of a first conductivity type and of second semiconductor strips of a second conductivity type arranged in alternated and contiguous fashion on a region of the second conductivity type, including for each of the first strips: a plurality of bias contacts; for each bias contact, a switch capable of applying a potential on the bias contact; two detection contacts arranged at the ends of the first strip; and a detection circuit having its activation causing the turning off of the switches and the comparison with a threshold of the resistance between the detection contacts.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: September 5, 2017
    Assignee: STMICROELECTRONICS (ROUSSET)
    Inventors: Mathieu Lisart, Nicolas Borrel
  • Patent number: 9590617
    Abstract: A semiconductor device includes a high breakdown voltage, high Gm first transistor and a low breakdown voltage, low Gm second transistor connected in series between first and second nodes, and a low breakdown voltage, high Gm third transistor connected to the second transistor in parallel. When the second transistor is turned on, the first transistor turns on, and furthermore, when the third transistor is turned on, an electrically conducting state is established between the first and second nodes. The second, low breakdown voltage transistor is turned on to turn on the first, high breakdown voltage transistor, and a turn-on time with only limited variation can be achieved.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: March 7, 2017
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kenji Komiya, Shuji Wakaiki, Kohtaroh Kataoka, Masaru Nomura, Yoshiji Ohta, Hiroshi Iwata
  • Patent number: 9401745
    Abstract: A memory device may include an array of closely spaced memory integrated circuits that communicate wirelessly over at least two frequencies using near field coupling.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: July 26, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Mostafa Naguib Abdulla
  • Patent number: 9400308
    Abstract: The systems and method described herein provide efficient (e.g., low power and low area) techniques to track performance in numerous supply domains with heterogeneous circuits that are used in a large system-on-a-chip integrated circuit (SoCs). The heterogeneous circuits can include circuits made with different devices, different cell libraries, and different hard macros that are in different power supply domains. Performance measurements from performance sensors (or process-voltage-temperature (PVT) sensors) that are spread about the SoC are collected and processed to determine voltage levels for each of the supply domains. A single controller can receive can determine voltage levels for a whole SoC. The performance sensors are connected to the controller by a scan chain. The techniques are flexible and can be easily adapted for use in SoCs with different power supply domains and types of circuits.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: July 26, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Jasmin Smaila Ibrahimovic, Mohammad Reza Kakoee, Shih-Hsin Jason Hu
  • Patent number: 9307346
    Abstract: A method and a system for remotely interacting with items in an electric field affected environment for communicating with a computing device is provided. The system includes a host for receiving commands from a computing device and a client for receiving and performing the signals received from the host. The host sends signals via modulated electric field. The client interacts with the items in the environment to determine their presence and location. The client further includes sensing devices and acting devices for sensing the condition of the items and manipulating the items respectively.
    Type: Grant
    Filed: December 25, 2013
    Date of Patent: April 5, 2016
    Inventors: Wolfgang Richter, Faranak Zadeh
  • Patent number: 9295907
    Abstract: A gaming apparatus for interacting with at least one player for playing a game is provided. The gaming apparatus includes a gaming surface and a playing item interacts with the gaming surface through the capacitive coupling. The gaming surface receives power from a battery source and includes a generator for generating AC power, a conducting surface generates alternating electric field, a converter for converting AC power into DC power and a computing element for storing the game instructions.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: March 29, 2016
    Inventors: Wolfgang Richter, Faranak Zadeh
  • Patent number: 9046574
    Abstract: A test circuit for a functional circuit includes a scan chain coupled to the functional circuit, and a controller coupled to the scan chain, for controlling the scan chain to scan a test pattern into the scan chain, and subsequently and repetitively for a multiple number of times launch the test pattern to the functional circuit, capture test data into the scan chain, and restore the test pattern in the scan chain for subsequent launch.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: June 2, 2015
    Assignee: ADVANCED MICRO DEVICES, INC
    Inventors: Grady L. Giles, James A. Wingfield, Atchyuth K. Gorti
  • Patent number: 9041448
    Abstract: Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC)(3DIC) and related method are disclosed. In one embodiment, a single clock source is provided for the 3DIC and distributed to elements within the 3DIC. Delay is provided to clock paths by selectively controllable flip-flops to help provide synchronous operation. In certain embodiments, 3D flip-flop are provided that include a master latch disposed in a first tier of a 3DIC. The master latch is configured to receive a flip-flop input and a clock input, the master latch configured to provide a master latch output. The 3D flip-flop also includes at least one slave latch disposed in at least one additional tier of the 3DIC, the at least one slave latch configured to provide a 3DIC flip-flop output. The 3D flip-flop also includes at least one monolithic intertier via (MIV) coupling the master latch output to an input of the slave latch.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: May 26, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Yang Du, Jing Xie, Kambiz Samadi
  • Patent number: 9041460
    Abstract: A power package is provided comprising a packaged transistor and a driving unit connected to the transistor and adapted to drive the transistor. A control terminal of the transistor is connected to a middle terminal pin of the housing of the transistor and outer terminal pins of the housing are connected to the driving unit and to a voltage level, respectively, wherein the connections are crossing free.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: May 26, 2015
    Assignee: Infineon Technologies AG
    Inventor: Ingo Voss
  • Publication number: 20150130500
    Abstract: The Configurable Vertical Integration [CVI] invention pertains to methods and apparatus for the enhancement of yields of 3D or stacked integrated circuits and herein referred to as a CVI Integrated Circuit [CVI IC]. The CVI methods require no testing of circuit layer components prior to their fabrication as part of a 3D integrated circuit. The CVI invention uses active circuitry to configure the CVI IC as a means to isolate or prevent the use of defective circuitry. CVI circuit configuration method can be predominately described as a large grain method.
    Type: Application
    Filed: August 26, 2014
    Publication date: May 14, 2015
    Inventor: Glenn J. Leedy
  • Patent number: 9030253
    Abstract: Integrated circuit (IC) packages with multiple clock sources are disclosed. A disclosed IC package includes a first die having a first clock source and a first clock tree and a second die having a second clock source and a second clock tree. The first clock source and the second clock source may be coupled to the second clock tree and the first clock tree, respectively, through a plurality of interconnects to form a clock tree network on the IC package. The clock tree network may be operable to be driven by either the first clock source or the second clock source.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: May 12, 2015
    Assignee: Altera Corporation
    Inventor: Tony Ngai
  • Publication number: 20150116031
    Abstract: The present disclosure provides a semiconductor device and an integrated apparatus having the same. The semiconductor device includes a substrate, a buffer layer on the substrate, a compensation area which includes a p-region and a n-region on the buffer layer, and a transistor cell on the compensation area. The transistor cell includes a source region, a body region, a gate electrode and a gate dielectric formed at least between the gate electrode and the body region. The gate dielectric has a thickness in a range of 12 nm to 50 nm.
    Type: Application
    Filed: October 30, 2014
    Publication date: April 30, 2015
    Inventors: Uwe Wahl, Armin Willmeroth
  • Patent number: 9013235
    Abstract: Monolithic three dimensional (3D) flip-flops with minimal clock skew and related systems and methods are disclosed. The present disclosure provides a 3D integrated circuit (IC) (3DIC) that has a flop spread across at least two tiers of the 3DIC. The flop is split across tiers with transistor partitioning in such a way that keeps all the clock related devices at the same tier, thus potentially giving better setup, hold and clock-to-q margin. In particular, a first tier of the 3DIC has the master latch, slave latch, and clock circuit. A second tier has the input circuit and the output circuit.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: April 21, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Pratyush Kamal, Yang Du
  • Publication number: 20150091747
    Abstract: An integrated circuit and a code generating method are described. The integrated circuit includes a plurality of field effect transistors, a plurality of sense-amplifiers, and a processing circuit. Each field effect transistor is configured to represent an address in a mapping table and includes a source, a drain, a channel and a gate. Each sense-amplifier is connected to the drain and configured to sense an electric current from the drain and identify a threshold voltage of the corresponding field effect transistor. The processing circuit is configured to categorize each of the threshold voltages identified by the corresponding sense-amplifiers into a first state and a second state and mark the state of each of the threshold voltages at the corresponding address in the mapping table.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Hiroshi Watanabe
  • Publication number: 20150092777
    Abstract: An integrated circuit, a code generating method, and a data exchange method are described. The integrated circuit includes a plurality of field effect transistors, a plurality of sense-amplifiers, and a processing circuit. Each field effect transistor is configured to represent an address in a mapping table and includes a source, a drain, a channel and a gate. Each sense-amplifier is connected to the drain and configured to sense an electric current from the drain and identify a threshold voltage of the corresponding field effect transistor. The processing circuit is configured to categorize each of the threshold voltages identified by the corresponding sense-amplifiers into a first state and a second state and mark the state of each of the threshold voltages at the corresponding address in the mapping table.
    Type: Application
    Filed: July 21, 2014
    Publication date: April 2, 2015
    Inventor: Hiroshi Watanabe
  • Patent number: 8994223
    Abstract: Disclosed is a self-powering system for electronic circuits by detecting and converting the energy of electric field lines provided from the generator of device in the proximity of the electronic circuit. The harvesting of electric field energy by using means of capacitive coupling (contactless or (in-) direct contact) to field inducing power sources replaces or reduces the need of batteries e.g. for mobile devices, medical sensors, energy efficient circuits (e.g. stand-by) or (near field-) communication devices. A wide range of applications and technical solutions from smart labels, e-ink devices, shutter glasses, or electronic sensors up to electronic devices of any kind, can use the invention's means to power (integrated) circuits microcontrollers, light emitting items (LED) or any circuit where batteries or other power sources can be replaced by the innovation.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: March 31, 2015
    Assignee: R2Z Innovations Inc.
    Inventors: Wolfgang Richter, Faranak Zadeh
  • Patent number: 8981841
    Abstract: A semiconductor integrated circuit includes a plurality of semiconductor chips respectively selected in response to a plurality of chip selection signals, and a chip selection signal generator configured to generate the chip selection signals in response to one first control signal for deciding whether to drive the semiconductor chips and at least one second control signal for selecting at least one semiconductor chip from among the semiconductor chips.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: March 17, 2015
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jae-Bum Ko, Jong-Chern Lee, Sang-Jin Byeon
  • Publication number: 20150061759
    Abstract: A monolithic power switch provides a semiconductor layer, a three dimensional FET formed in the semiconductor layer to modulate currents through the semiconductor layer, and a toroidal inductor with a ceramic magnetic core formed on the semiconductor layer around the FET and having a first winding connected to the FET.
    Type: Application
    Filed: June 9, 2014
    Publication date: March 5, 2015
    Inventor: L. Pierre de Rochemont
  • Patent number: 8970250
    Abstract: Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: March 3, 2015
    Assignee: Tabula, Inc.
    Inventors: Martin Voogel, Jason Redgrave, Trevis Chandler
  • Patent number: 8954125
    Abstract: Low-loss superconducting devices and methods for fabricating low loss superconducting devices. For example, superconducting devices, such as superconducting resonator devices, are formed with a (200)-oriented texture titanium nitride (TiN) layer to provide high Q, low loss resonator structures particularly suitable for application to radio-frequency (RF) and/or microwave superconducting resonators, such as coplanar waveguide superconducting resonators. In one aspect, a method of forming a superconducting device includes forming a silicon nitride (SiN) seed layer on a substrate, and forming a (200)-oriented texture titanium nitride (TiN) layer on the SiN seed layer.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: February 10, 2015
    Assignees: International Business Machines Corporation, The United States of America, as represented by the Secretary of Commerce, The National Institute of Standards
    Inventors: Antonio D. Corcoles Gonzalez, Jiansong Gao, Dustin A. Hite, George A. Keefe, David P. Pappas, Mary E. Rothwell, Matthias Steffen, Chang C. Tsuei, Michael R. Vissers, David S. Wisbey
  • Publication number: 20150033050
    Abstract: A semiconductor integrated circuit and a computing system including the same are provided. The semiconductor integrated circuit includes: an integrated clock gating cell including a clock output node; and clock-based cells each including a clock input node. The clock output node of the integrated clock gating cell and the clock input nodes of the clock-based cells are aligned on a straight line and commonly connected to a clock gating path.
    Type: Application
    Filed: July 25, 2013
    Publication date: January 29, 2015
    Applicant: SAMSUNG ELECTRONICS CO., LTD
    Inventors: Amjad QADAN, Neil PANCHAL
  • Patent number: 8937503
    Abstract: A switch control circuit has a first terminal, a second terminal, a third terminal, a serial-parallel converter, a selector, a driver circuit and a tri-state buffer. The serial-parallel converter converts a serial switching control signal inputted from the third terminal into first parallel switching control signals when the first terminal is at a first power-supply potential. The selector selects either the first parallel switching control signals converted by the serial-parallel converter or second parallel switching control signals inputted into the second and third terminals, depending on the potential of the first terminal. The driver circuit converts potential levels of the first parallel switching control signals or the second parallel switching control signals selected by the selector and generates parallel switching control signals with potential levels capable of switching a switch circuit.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: January 20, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshiki Seshita
  • Publication number: 20140375380
    Abstract: According to a method herein, a portion of an electronic circuit is identified. The electronic circuit comprises logic circuitry. The portion of the electronic circuit is designed in at least two versions. Each of the at least two versions is evaluated using a plurality of operating conditions. The current operating conditions are determined. One version of the at least two versions is identified as a selected version based on the performance under the current operating conditions. The selected version has relatively optimal performance based on at least one of clock frequency, supply voltage, and power limit. The selected version is activated for use in the portion of the electronic circuit. The remaining versions of the at least two versions are deactivated.
    Type: Application
    Filed: June 19, 2013
    Publication date: December 25, 2014
    Inventors: John M. Cohn, David J. Hathaway, Sridhar H. Rangarajan, Diyanesh Babu C. Vidyapoornachary
  • Publication number: 20140368242
    Abstract: Various systems and methods utilizing a digitally controlled oscillator having frequency steps that increase in magnitude as a target output clock frequency increases are described. An integrated circuit in accordance with the disclosure includes a plurality of first transistor units fixedly coupled to an input voltage and a plurality of second transistor units switchably coupled to the first transistor units. An output coupled to the plurality of second transistor units and the plurality of first transistor units conveys an output signal having a frequency dependent on which select ones of the second transistor units are enabled. The plurality of second transistor units include a first switchable transistor unit having a transistor of a first width, a second switchable transistor unit having a transistor of a second width greater than the first width, and a third switchable transistor unit having a transistor of a third width greater than the second width.
    Type: Application
    Filed: June 30, 2013
    Publication date: December 18, 2014
    Inventor: Gregory Alyn Unruh
  • Publication number: 20140368266
    Abstract: A hybrid integrated circuit in a wafer level package for an implantable medical device includes one or more passive component windings formed, at least in part, along one or more routing layers of the package. The windings may be primary and secondary windings of a transformer, wherein all or part of a magnetic core thereof is embedded in a component layer of the wafer level package. If the core includes a part bonded to a surface of the package, that part of the core may be E-shaped with legs extending into the routing layers, and, in some cases, through the routing layers. Routing layers may be formed on both sides of the component layer to accommodate the transformer windings, in some instances.
    Type: Application
    Filed: August 29, 2014
    Publication date: December 18, 2014
    Inventors: Mohsen Askarinya, Mark R Boone, Andreas A Fenner, Lejun Wang, Kenneth Heames
  • Publication number: 20140354350
    Abstract: A self-healing monolithic integrated includes an electronic circuit having a plurality of transistors. At least one sensor is disposed within and electrically coupled to the electronic circuit and configured to sense a performance metric of the electronic circuit. A plurality of actuators is disposed within the circuit. Each actuator of the plurality of actuators has electrically coupled to it a control terminal. The plurality of actuators is configured to perform a selected one of, electrically coupling at least one transistor of the plurality of transistors into the electronic circuit and electrically de-coupling at least one transistor of the plurality of transistors, in response to operation of one of the control terminals to improve the performance metric.
    Type: Application
    Filed: February 10, 2014
    Publication date: December 4, 2014
    Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Steven Bowers, Kaushik Sengupta, Kaushik Dasgupta, Seyed Ali Hajimiri
  • Patent number: 8890600
    Abstract: A programmable device, having an analog component coupled with an analog bus and a digital component coupled with a digital bus together with a set of IO pads, each of which capable of being coupled to a bus line of one segment of the analog bus as well as to at least one digital bus line, and where the analog bus is capable of being used to connect a pair of the IO pads to each other.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: November 18, 2014
    Assignee: Cypress Semicondductor Corporation
    Inventors: Timothy J. Williams, Harold Kutz, David G. Wright, Eashwar Thiagarajan, Warren S. Snyder, Mark E. Hastings
  • Patent number: 8884650
    Abstract: A diode-switch logic circuit of the present invention is configured such that: at least one of paths between a common input-output terminal and respective individual input-output terminals is caused to become a conducting state; control voltages of control terminals are respectively applied to gates of path switching FET stages; logic synthesis voltages of the control voltages of the control terminals are respectively applied to gates of shunt FET stages; and each of the logic synthesis voltages is generated by a logical product of a logical negation of the control voltage applied to one shunt FET stage and a logical sum of the control voltages respectively applied to the remaining shunt FET stages.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: November 11, 2014
    Assignee: Panasonic Corporation
    Inventor: Takahito Miyazaki
  • Publication number: 20140320202
    Abstract: Described herein is an integrated circuit which comprises: a first buffer, with positive trans-conductance, to drive a first signal with first phase; and a second buffer, with negative trans-conductance, to drive a second signal with second phase, wherein the first buffer and the second buffer are cross-coupled to one another.
    Type: Application
    Filed: July 14, 2014
    Publication date: October 30, 2014
    Inventors: SITARAMAN V. IYER, GULUKE TONG
  • Patent number: 8866543
    Abstract: Provided is an integrated circuit (IC) having a stacked structure. The IC includes: a first IC having a power input terminal to which a power supply voltage is applied; and a second IC having a power input terminal connected to a ground terminal of the first IC, having a central node formed as the power input terminal of the second IC and the ground terminal of the first IC are connected to each other and to which a voltage is applied, and having a ground terminal connected to a ground source, wherein the power supply voltage is divided into first and second voltages that are respectively applied to the first and second ICs.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: October 21, 2014
    Assignee: Soongsil University Research Consortium Techno-Park
    Inventors: Chang Kun Park, Ho Yong Hwang
  • Publication number: 20140266417
    Abstract: A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a graphics processing cluster (GPC) chip, and an MCM package configured to include the first processor chip, the GPC chip, and an interconnect circuit. The first processor chip is configured to include a first ground-referenced single-ended signaling interface circuit. A first set of electrical traces fabricated within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit. The GPC chip is configured to include a second single-ended signaling interface circuit and to execute shader programs. A second set of electrical traces fabricated within the MCM package and configured to couple the second single-ended signaling interface circuit to the interconnect circuit. In one embodiment, each single-ended signaling interface advantageously implements ground-referenced single-ended signaling.
    Type: Application
    Filed: August 22, 2013
    Publication date: September 18, 2014
    Applicant: NVIDIA Corporation
    Inventors: William J. Dally, Jonah M. Alben, John W. Poulton, Thomas Hastings Greer, III
  • Publication number: 20140266416
    Abstract: A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a second processor chip, and an MCM package configured to include the first processor chip, the second processor chip, and an interconnect circuit. The first processor chip is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. A first set of electrical traces fabricated within the MCM package and configured to couple the first GRS interface circuit to the interconnect circuit. The second processor chip is configured to include a second GRS interface circuit. A second set of electrical traces fabricated within the MCM package and configured to coupled the second GRS interface circuit to the interconnect circuit.
    Type: Application
    Filed: July 19, 2013
    Publication date: September 18, 2014
    Applicant: NVIDIA Corporation
    Inventors: William J. Dally, Brucek Kurdo Khailany, John W. Poulton, Thomas Hastings Greer, III, Carl Thomas Gray
  • Patent number: 8823053
    Abstract: The semiconductor device includes a plurality of first flat plates containing a material that absorbs an electromagnetic wave at a high frequency. Any of the first flat plates is disposed above the first connecting wire, and any other of the first flat plates is disposed above the second connecting wire.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: September 2, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoko Sakiyama, Kohei Morizuka
  • Patent number: 8810309
    Abstract: A stack package having a plurality of stacked chips includes first voltage dropping units respectively formed in the plurality of chips, the first voltage dropping units are electrically coupled by a first line; second voltage dropping units respectively formed in the plurality of chips, the second dropping units are electrically coupled by a second line; first signal generation units respectively formed in the plurality of chips, each of the first signal generation units is connected to an output node of the first voltage dropping units, respectively; and second signal generation units respectively formed in the plurality of chips, each of the second signal generation units is connected to an input node of the second voltage dropping units, respectively.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: August 19, 2014
    Assignee: SK Hynix Inc.
    Inventors: Dae Woong Lee, Yu Gyeong Hwang, Jae Hyun Son, Tae Min Kang, Chul Keun Yoon, Byoung Do Lee, Yu Hwan Kim
  • Patent number: 8791751
    Abstract: A semiconductor integrated circuit includes a logic circuit having a plurality of operation modes, a power source circuit that generates a power source voltage to be supplied to the logic circuit, a power source wiring that couples the power source circuit and the logic circuit, and a charge control block that holds charges for controlling the voltage of the power source wiring. The power source circuit generates a first power source voltage for causing the logic circuit to operate in a computing mode and a second power source voltage for causing the logic circuit to operate in a sleep mode. The charge control block includes a capacitor, a first switch, and a voltage supply unit that supplies the second power source voltage or a third power source voltage lower than the second power source voltage, to the capacitor.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: July 29, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Makoto Ueki, Naoya Inoue, Yoshihiro Hayashi
  • Patent number: 8786362
    Abstract: A Schottky diode having a current leakage protection structure includes a Schottky diode unit, a first isolation portion and a second isolation portion. The Schottky diode unit is defined in a substrate and includes a metalized anode, an active region having dopants of first conductive type, a cathode and at least one isolation structure. The first isolation portion having dopants of second conductive type is formed between substrate and active region, and the first isolation portion includes a first well disposed beneath active region, and a first guard ring surrounding active region and connecting to the first well. The second isolation portion having dopants of first conductive type is formed between substrate and the first isolation portion, and the second isolation portion includes a second well disposed beneath the first well, and a second guard ring surrounding the first guard ring and connecting to the second well.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: July 22, 2014
    Assignee: United Microelectronics Corporation
    Inventors: An-Hung Lin, Wei-Shan Liao, Bo-Jui Huang, Hong-Ze Lin, Ting-Zhou Yan, Wen-Chun Chang
  • Publication number: 20140177351
    Abstract: A semiconductor device includes a first transistor connected to an internal voltage terminal and a first node at which a first resistance unit is connected. The first resistance unit includes a resistor connected between the first node and a node from which a monitoring voltage is provided for controlling the first transistor. This resistance unit also includes a first resistance adjustment unit connected in parallel with the first resistor. Also included is a second resistance unit having a third resistor connected between the monitor node and a second node which is connected to a ground potential and a second resistance adjustment unit connected in parallel with the third resistor. A comparator comparing the monitor node voltage to a reference is provided with an output terminal connected the first transistor. Also included is a control circuit to control the resistance adjustment units.
    Type: Application
    Filed: September 2, 2013
    Publication date: June 26, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Naoaki KANAGAWA
  • Publication number: 20140176116
    Abstract: A first instance and a second instance of an oscillating circuit are each formed as part of an integrated circuit and are used to monitor degradation over time of one or more portions of the integrated circuit. The first instance of the oscillating circuit is configured to be coupled to a power source during normal operation of the integrated circuit and the second instance is configured to be decoupled from the power source. Over the lifetime of the integrated circuit, the first instance undergoes degradation from use while the second instance of the oscillating circuit remains unpowered, therefore experiencing essentially no use-related degradation. During a testing operation, the second instance can be used as a reference circuit that accurately quantifies use-related degradation of the first instance of the oscillating circuit and, by extension, one or more portions of the integrated circuit.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 26, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Hemant KUMAR, Matthew Raymond LONGNECKER, Brian SMITH
  • Publication number: 20140152383
    Abstract: Three dimensional integrated circuits including semiconductive organic materials are described. In some embodiments, the three dimensional integrated circuits include one or more electronic components that include a semiconductive region formed of one or more semiconductive organic materials. The electronic components of the three dimensional integrated circuits may also include insulating regions formed from organic insulating materials, and conductive regions form from conductive materials. The three dimensional integrated circuits may be formed by an additive manufacturing process such as three dimensional printing. Apparatus and methods for producing and testing three dimensional integrated circuits are also described.
    Type: Application
    Filed: November 30, 2012
    Publication date: June 5, 2014
    Inventors: DMITRI E. NIKONOV, ROBERT L. SANKMAN, RASEONG KIM, JIN PAN
  • Patent number: 8742839
    Abstract: This invention discloses a double Through Silicon Via (TSV) structure, including a first die unit, a first signal path, a second signal path, a receiving unit and a second die unit. The first and the second signal paths respectively include a driving unit and a TSV unit. Each driving unit includes a first end, a second end and a third end. The invention divides the signal paths of the conventional double TSV into two different signal paths by two driving units and the receiving unit having OR gate or NOR gate, to avoid generating the problem of signal degradation from the TSV unit with short defect. The invention further disposes a first switch unit, a second switch unit, a first exchange unit, a second exchange unit, a first VDD keeper and a second VDD keeper, to avoid generating the problems of open defect and leakage current.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: June 3, 2014
    Assignee: National Tsing Hua University
    Inventors: Hsiu-Chuan Shih, Cheng-Wen Wu
  • Patent number: 8742838
    Abstract: The interposer 30 is disposed on an upper surface of the stacked structure 24 formed by stacking a plurality of a DRAM chip 20 and a plurality of a flash memory chip 22. Thus down-size of an entire device is accomplished. A boost converter having an inductor is used as a voltage boost circuit 40. Thus down-size of the entire device is accomplished.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: June 3, 2014
    Assignee: The University of Tokyo
    Inventors: Ken Takeuchi, Tadashi Yasufuku, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai
  • Patent number: 8744368
    Abstract: An apparatus and method are disclosed for providing test mode contact pad reconfigurations that expose individual internal functional modules or block groups in an integrated circuit for testing and for monitoring. A plurality of switches between each functional module switches between passing internal signals among the blocks and passing in/out signals external to the block when one or more contact pads are strapped to input a pre-determined value. Another set of switches between the functional modules and input/output contact pads switch between functional inputs to and from the functional modules and monitored signals or input/output test signals according to the selected mode of operation.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: June 3, 2014
    Assignee: Broadcom Corporation
    Inventors: Love Kothari, James Bennett, Zhongmin Zhang