Integrated Structure Patents (Class 327/564)
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Patent number: 11937349Abstract: Disclosed is a drive circuit for a digital dimming LED light, relating to the LED light drive circuits, which includes a power module and a dimming module corresponding to the LED lights, wherein the dimming module comprises a demodulation unit, a boosting constant voltage unit and a constant current chopper unit, and the power module is used to convert a utility power into DC power and output it to the demodulation unit, and to receive an external dimming signal and modulate and convert it into a digital signal. The demodulation unit is connected to the power module for receiving and demodulating the digital signal, the constant current chopper unit is connected to the demodulation unit, and both the boosting constant voltage unit and the constant current chopper unit are connected with the LED lights, so that the brightness of the LED lights is consistent.Type: GrantFiled: October 27, 2022Date of Patent: March 19, 2024Assignee: Shenzhen Hontech-Wins Electronics Co., LTD.Inventors: Zhihua Zhang, Wencai Wei, Zhenting Fan
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Patent number: 11894174Abstract: In a coil component, a height h1 of a pedestal portion of a resin wall corresponds to the height position of a step portion. In addition, a height of a seed portion corresponds to the plating start position at a time when a winding portion of a coil is plated and grown. The plating start position and the step portion are designed to be close to each other by the height h1 of the pedestal portion and the height h2 of the seed portion satisfying 0.3?h1/h2?10. Accordingly, although the coil component has a configuration in which the resin wall has the step portion, the inside of the step portion is sufficiently filled with a coil conductor, and thus deterioration of characteristics is suppressed.Type: GrantFiled: November 10, 2020Date of Patent: February 6, 2024Assignee: TDK CORPORATIONInventors: Hitoshi Ohkubo, Manabu Ohta, Ryo Fukuoka, Hironori Kimata
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Patent number: 11876518Abstract: An system-on-a-chip (“SoC”) is provided. In some examples, the SoC includes a processor and a plurality of timer circuit blocks including at least a first timer circuit block and a second timer circuit block. Each of the plurality of timer circuit blocks may be selectively coupled by at least one of a first programmable matrix and a second programmable matrix. In some examples, the first programmable matrix may be configured to couple a second trigger input of the first timer circuit block with a first trigger output of the second timer circuit block. In some examples, the second programmable matrix is configured to couple a second fault input of the first timer circuit block with a first fault output of the second timer circuit block.Type: GrantFiled: September 1, 2021Date of Patent: January 16, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Rakesh Hariharan, Sumantha Manoor Madhyastha
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Patent number: 11855619Abstract: An integrated circuit device includes: an integrated circuit module; a first field-effect transistor coupled between the integrated circuit module and a first reference voltage, and controlled by a first controlled signal; and a second field-effect transistor coupled between the integrated circuit module and the first reference voltage; wherein the second field-effect transistor is a complementary field-effect transistor of the first field-effect transistor, and the first field-effect transistor and the second field-effect transistor are configured to generate a second reference voltage for the integrated circuit module according to the first control signal.Type: GrantFiled: January 15, 2020Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tzung-Yo Hung, Pin-Dai Sue, Chien-Chi Tien, Ting-Wei Chiang
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Patent number: 11764756Abstract: A crystal device includes a bearing base, an integrated chip and a conductive adhesive unit. The bearing base includes a conductive seat. The integrated chip includes a principal reference plane facing the conductive seat, and having a first major axis. The conductive adhesive unit has a second major axis and an aspect ratio, and is at least partly disposed between the conductive seat and the integrated chip. The aspect ratio ranges from 1.1 to 1.9. The principal reference plane further has a perpendicular projection straight line defined according to the second major axis. A practical angle is included by the first perpendicular projection straight line and the first major axis, and ranges from 0 degree to 90 degrees.Type: GrantFiled: May 25, 2021Date of Patent: September 19, 2023Assignee: TAI-SAW TECHNOLOGY CO., LTD.Inventors: Cheng-Kang Peng, Kun-Yu Huang, Chi-Yun Chen, Song Tian, Tsung-Pin Yang
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Patent number: 11714128Abstract: The present disclosure discloses a method and an apparatus for testing an artificial intelligence chip test, a device and a storage medium, and relates to the field of artificial intelligence. The specific implementation solution is: the target artificial intelligence chip has multiple same arithmetic units, the method includes: obtaining scale information of the target artificial intelligence chip; determining whether the target artificial intelligence chip satisfies a test condition of an arithmetic unit array level according to the scale information; dividing all the arithmetic units into multiple same arithmetic unit arrays, and performing a DFT test on the arithmetic unit arrays, respectively, if it is determined that the test condition of the arithmetic unit array level is satisfied; performing the DFT test on the arithmetic units, respectively, if it is not determined that the test condition of the arithmetic unit array level is not satisfied.Type: GrantFiled: September 15, 2020Date of Patent: August 1, 2023Inventor: Ziyu Guo
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Patent number: 11675729Abstract: An operation method of a sleep mode of an electronic device includes the following steps. A first sub-module of a first module sends a sleep command to a second sub-module of the first module and a third sub-module and a fourth sub-module of a second module, wherein the first sub-module includes first and second modes, the second sub-module includes third and fourth nodes, the third sub-module includes fifth and sixth nodes, and the fourth sub-module includes seventh and eighth nodes. The second sub-module, the third sub-module and fourth sub-module execute a sleep sequence in sequence to enter a sleep mode according to the sleep command. The first node sends the sleep command to the second node to execute the sleep sequence to enter the sleep mode. The first node sends the sleep command to the first node to execute the sleep sequence to enter the sleep mode.Type: GrantFiled: October 20, 2021Date of Patent: June 13, 2023Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.Inventors: Yixing Mei, Yongfeng Song, Xuemin Zhang, Xiaoliang Ji, Shuai Zhang
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Patent number: 11632081Abstract: Provided are a transmission line module for a rotary traveling wave oscillator (RTWO) and a design method thereof. The transmission line module includes a substrate. The upper surface of the substrate is provided with a grounding metal layer, that is, a metal ground. The metal ground is provided with a rectangular groove. The rectangular groove penetrates front and rear sides of the metal ground along a length direction of the rectangular groove. The thickness of the rectangular groove is the same as the thickness of the metal ground. The rectangular groove is filled with a silicon dielectric plate that has the same shape and size as the rectangular groove. The upper surface of the silicon dielectric plate is provided with two parallel transmission lines along the length direction of the rectangular groove.Type: GrantFiled: September 29, 2022Date of Patent: April 18, 2023Assignee: THE CHINESE UNIVERSITY OF HONG KONG, SHENZHENInventors: Liang Wu, Zehui Kang
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Patent number: 11631469Abstract: An integrated circuit includes a test control circuit, a driving circuit, and a test detection circuit. The test control circuit generates a test command signal and a test address signal corresponding to a test operation. The driving circuit performs the test operation by utilizing a test internal voltage, which is generated based on the test command signal. The test detection circuit compares the test address signal with target address information to output the test internal voltage.Type: GrantFiled: January 12, 2021Date of Patent: April 18, 2023Assignee: SK hynix Inc.Inventor: Seung Hyun Chung
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Patent number: 11500803Abstract: A programmable slave circuit on a communication bus is provided. In a non-limiting example, the communication bus can be a radio frequency front-end (RFFE) bus operating based on a master-slave topology and the programmable slave circuit can be an RFFE slave circuit on the RFFE bus. The programmable slave circuit is configured to receive a high-level command(s) (e.g., a macro word) over the communication bus. A processing circuit in the programmable slave circuit is programmed to generate a low-level command(s) (e.g., a bitmap word) for controlling a coupled circuit(s) based on the high-level command(s). In this regard, it is possible to program or reprogram the processing circuit, for example via over-the-air (OTA) updates, based on the high-level command(s) to be supported, thus making it possible to flexibly customize the programmable slave circuit according to operating requirements and configurations.Type: GrantFiled: September 1, 2020Date of Patent: November 15, 2022Assignee: Qorvo US, Inc.Inventors: Christopher Truong Ngo, Nadim Khlat, Alexander Wayne Hietala
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Patent number: 11488911Abstract: A flip-chip package substrate is provided. A strengthening structure is provided on one side of a circuit structure to increase the rigidity of the flip-chip package substrate. When the flip-chip package substrate is used in large-scale packaging, the flip-chip package substrate can have good rigidity, so that the electronic package can be prevented from warping.Type: GrantFiled: July 31, 2018Date of Patent: November 1, 2022Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Chu-Chin Hu, Shih-Ping Hsu
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Patent number: 11481011Abstract: An input terminal connected to both a terminal of the first device outputting a signal including a period of a low voltage greater than or equal to a predetermined period and a terminal of the second device outputting a periodic signal alternately repeating a high voltage and a low voltage less than the predetermined period via one signal line is included. When a signal input to the input terminal includes a period of a low voltage greater than or equal to the predetermined period, it is determined that a signal output from the first device is input.Type: GrantFiled: March 27, 2020Date of Patent: October 25, 2022Assignee: CASIO COMPUTER CO., LTD.Inventors: Keiichi Nomura, Tsuyoshi Minami, Shuhei Uchida, Toshiya Sakurai, Hideo Suzuki
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Patent number: 11462294Abstract: The low end operating voltage of an integrated circuit is adjusted. Oscillations are counted at a ring oscillator on the integrated circuit over a designated period of clock cycles. Based on the number of oscillations, a prediction model associated with a first set of device degradation data and a second set of static random-access memory (SRAM) low end operating voltage data is used to select a low end operating voltage limit for a processor on the integrated circuit. The low end operating voltage of the processor is set based on the selected low end operating voltage limit. These steps are repeated multiple times during operation of the processor. A method of testing integrated circuits to provide the data employed to produce the prediction model is also provided.Type: GrantFiled: December 14, 2020Date of Patent: October 4, 2022Assignee: Advanced Micro Devices, Inc.Inventors: Ashish Jain, Sriram Sundaram, Samuel Naffziger
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Patent number: 11387226Abstract: This application discloses a chip power supply system, a chip, a PCB, and a computer device. The chip power supply system includes a first printed circuit board (PCB), a chip, a power controller, and an inductor module. The first PCB includes N vias, first ends of the N vias are located at a top layer of the PCB, and second ends of the N vias are located at a bottom layer of the first PCB. The chip is coupled to the top layer of the first PCB through N power supply contacts and the first ends of the N vias. The inductor module is coupled to the chip through M power supply contacts and the second ends of M vias of the N vias. The power controller is coupled to the inductor module through the first PCB, and the power controller is configured to control the inductor module to supply power to the chip.Type: GrantFiled: November 5, 2020Date of Patent: July 12, 2022Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Yadong Bai, Zhijun Qu, Changxing Sun, Haitao Han
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Patent number: 11340831Abstract: A memory system is provided. The memory system includes a memory controller and a data bus electrically coupled to the memory controller. The memory system further includes one or more memory devices communicatively coupled to the memory controller via the data bus, wherein each of the one or more memory devices comprises a read training setting configured to adjust a read output timing of data being sent to the memory controller during read operations from the one or more memory devices.Type: GrantFiled: August 28, 2020Date of Patent: May 24, 2022Assignee: Micron Technology, Inc.Inventors: Yang Lu, Christopher Heaton Stoddard
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Patent number: 11158606Abstract: Dies and/or wafers are stacked and bonded in various arrangements including stacks, and may be covered with a molding to facilitate handling, packaging, and the like. In various examples, the molding may cover more or less of a stack, to facilitate connectivity with the devices of the stack, to enhance thermal management, and so forth.Type: GrantFiled: July 2, 2019Date of Patent: October 26, 2021Assignee: Invensas Bonding Technologies, Inc.Inventors: Guilian Gao, Cyprian Emeka Uzoh, Jeremy Alfred Theil, Belgacem Haba, Rajesh Katkar
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Patent number: 11133804Abstract: An system-on-a-chip (“SoC”) is provided. In some examples, the SoC includes a processor and a plurality of timer circuit blocks including at least a first timer circuit block and a second timer circuit block. Each of the plurality of timer circuit blocks may be selectively coupled by at least one of a first programmable matrix and a second programmable matrix. In some examples, the first programmable matrix may be configured to couple a second trigger input of the first timer circuit block with a first trigger output of the second timer circuit block. In some examples, the second programmable matrix is configured to couple a second fault input of the first timer circuit block with a first fault output of the second timer circuit block.Type: GrantFiled: December 18, 2020Date of Patent: September 28, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Rakesh Hariharan, Sumantha Manoor Madhyastha
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Patent number: 11119640Abstract: An electronic customization system designed to allow an automotive interior to be customizable via a user terminal. The electronic customization system comprises electronic customization displays integrated in corresponding aesthetic/functional components of the automotive interior, and an electronic control unit configured to communicate and cooperate with the user terminal in order to allow the automotive interior to be customizable via the user terminal. The user terminal is configured to expose a graphical user interface configured to allow digital decorative wallpapers to be selectable for display on the electronic customization displays, and to transmit to the electronic control unit data indicative of the selected digital decorative wallpapers. The electronic control unit is configured to receive data indicative of the selected digital decorative wallpapers from the user terminal, and to cause the selected digital decorative wallpapers to be displayed on the electronic customization displays.Type: GrantFiled: January 15, 2019Date of Patent: September 14, 2021Assignee: FCA ITALY S.p.A.Inventors: Silvio Della Vecchia, Taulant Marpepa, Vincenzo Nuara
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Patent number: 11080192Abstract: The storage system includes a first partition which is associated with a first processor and in which the first processor temporarily stores data relating to I/O requests processed by the first processor; and a second partition which is associated with a second processor and in which the second processor temporarily stores data relating to I/O requests processed by the second processor. Each processor independently controls the size of the first partition of the first cache memory and the size of the first partition of the second cache memory, and also independently controls the size of the second partition of the first cache memory and the size of the second partition of the second cache memory.Type: GrantFiled: May 14, 2015Date of Patent: August 3, 2021Assignee: HITACHI, LTD.Inventors: Ryosuke Tatsumi, Shintaro Ito, Masakuni Agetsuma
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Patent number: 11009407Abstract: According to one embodiment, a semiconductor device 1 includes a temperature sensor module 10 that outputs a non-linear digital value with respect temperature and a substantial linear sensor voltage value with respect to the temperature, a storage unit 30 that stores the temperature, the digital value, and the sensor voltage value, and a controller 40 that calculates a characteristic formula using the temperature, the digital value, and the sensor voltage value stored in the storage 30, in which the temperature, the digital value, and the sensor voltage value stored in the storage unit 30 include absolute temperature under measurement of absolute temperature, the digital value at the absolute temperature, and the sensor voltage value at the absolute temperature.Type: GrantFiled: July 23, 2019Date of Patent: May 18, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Masanori Ikeda, Tadashi Kameyama
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Patent number: 10971636Abstract: A photoelectric detection structure, a manufacturing method therefor, and a photoelectric detector. The photoelectric detection structure includes: a base substrate; an electrode strip, which is located on the base substrate; a semiconductor layer, which is located at a side of the base substrate that faces the electrode strip; an insulating layer, which is located between the electrode strip and the semiconductor layer, the insulating layer including a thickness-increased portion, and the thickness-increased portion being located on at least one edge of the electrode strip.Type: GrantFiled: June 8, 2018Date of Patent: April 6, 2021Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventor: Zhanjie Ma
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Patent number: 10886921Abstract: Examples described herein generally relate to multi-chip devices having stacked chips. In an example, a multi-chip device includes a chip stack including a base chip and two or more overlying chips overlying the base chip. Neighboring chips of the chip stack are connected to each other. The chip stack includes identification generation connections and circuits configured to generate a unique identification of each overlying chip based on a relative position of the respective overlying chip with reference to the base chip. The chip stack includes a communication channel from the base chip to each overlying chip. Each overlying chip includes comparison and enable/disable logic (CEDL) communicatively coupled to the communication channel. The CEDL is configured to compare a target identification of data received by the respective overlying chip to the unique identification of the respective overlying chip and responsively enable or disable a recipient circuit of the respective overlying chip.Type: GrantFiled: March 20, 2020Date of Patent: January 5, 2021Assignee: XILINX, INC.Inventors: Vijay Kumar Koganti, Anil Kumar Kandala, Santosh Yachareni
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Patent number: 10734196Abstract: Provided is an impedance matching device for matching an impedance between a high-frequency power source and a load. The impedance matching device pertaining to the present invention is provided with: a matching circuit having variable capacitors, a capacitance of which is adjusted by an ON/OFF operation of a plurality of switches; a switch control unit for performing control for causing states of the switches of the variable capacitors to coincide with a target state in order to adjust the capacitance of the variable capacitors; and a switch state evaluation unit for evaluating whether a switch is in a state requiring suppression of a temperature increase. The switch control unit is configured so that when the switch state evaluation unit evaluates that a switch of the variable capacitors is in a state requiring suppression of a temperature increase, control is performed for suspending changing of a switch state of the switch for a set period and suppressing a temperature increase in the switch.Type: GrantFiled: September 25, 2017Date of Patent: August 4, 2020Assignee: DAIHEN CorporationInventors: Tatsuya Morii, Masayuki Nakahama
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Patent number: 10573718Abstract: A vertical, high-voltage MOS transistor, which has a source region, a body contact region, and a number of trenches structures with field plates, and a method of forming the MOS transistor increase the on-state resistance of the MOS transistor by reducing the trench pitch. Trench pitch can be reduced with metal contacts that simultaneously touch the source regions, the body contact regions, and the field plates. Trench pitch can also be reduced with a gate that increases the size of the LDD region.Type: GrantFiled: November 9, 2016Date of Patent: February 25, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Christopher Boguslaw Kocon, Simon John Molloy, John Manning Savidge Neilson, Hideaki Kawahara
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Patent number: 10243621Abstract: Tightly-coupled near-field transmitter/receiver pairs are deployed such that the transmitter is disposed at a terminal portion of a first conduction path, the receiver is disposed at a terminal portion of a second conduction path, the transmitter and receiver are disposed in close proximity to each other, and the first conduction path and the second conduction path are discontiguous with respect to each other. In some embodiments of the present invention, close proximity refers to the transmitter antenna and the receiver antenna being spaced apart by a distance such that, at wavelengths of the transmitter carrier frequency, near-field coupling is obtained. In some embodiments, the transmitter and receiver are disposed on separate substrates that are moveable relative to each other. In alternative embodiments, the transmitter and receiver are disposed on the same substrate.Type: GrantFiled: August 16, 2017Date of Patent: March 26, 2019Assignee: Keyssa, Inc.Inventor: Gary D. McCormack
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Patent number: 9996126Abstract: The present application is directed at pin programming od controllers for power converters and provides for the programming of a plurality of different controller parameters using a single programming resistor. The value of the programming resistor is used as a pointer to select a table storing a plurality of different settings for the controller.Type: GrantFiled: September 20, 2011Date of Patent: June 12, 2018Assignee: ROHM Powervation LimitedInventors: Karl Rinne, Antoin Russell
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Patent number: 9871020Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to intelligent through silicon via sharing in 3D-IC integrated structures and methods of manufacture. The structure includes: a plurality of stacked dies each containing at least one macro device; and a layer structure positioned between the plurality of stacked dies which comprises a control structured to route signals between the at least one macro device of a first stacked die and the at least one macro device of a second stacked die of the plurality of stacked dies.Type: GrantFiled: July 14, 2016Date of Patent: January 16, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Sebastian T. Ventrone, Sudeep Mandal
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Patent number: 9754902Abstract: An integrated circuit including a plurality of first semiconductor strips of a first conductivity type and of second semiconductor strips of a second conductivity type arranged in alternated and contiguous fashion on a region of the second conductivity type, including for each of the first strips: a plurality of bias contacts; for each bias contact, a switch capable of applying a potential on the bias contact; two detection contacts arranged at the ends of the first strip; and a detection circuit having its activation causing the turning off of the switches and the comparison with a threshold of the resistance between the detection contacts.Type: GrantFiled: March 16, 2016Date of Patent: September 5, 2017Assignee: STMICROELECTRONICS (ROUSSET)Inventors: Mathieu Lisart, Nicolas Borrel
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Patent number: 9590617Abstract: A semiconductor device includes a high breakdown voltage, high Gm first transistor and a low breakdown voltage, low Gm second transistor connected in series between first and second nodes, and a low breakdown voltage, high Gm third transistor connected to the second transistor in parallel. When the second transistor is turned on, the first transistor turns on, and furthermore, when the third transistor is turned on, an electrically conducting state is established between the first and second nodes. The second, low breakdown voltage transistor is turned on to turn on the first, high breakdown voltage transistor, and a turn-on time with only limited variation can be achieved.Type: GrantFiled: April 5, 2012Date of Patent: March 7, 2017Assignee: SHARP KABUSHIKI KAISHAInventors: Kenji Komiya, Shuji Wakaiki, Kohtaroh Kataoka, Masaru Nomura, Yoshiji Ohta, Hiroshi Iwata
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Patent number: 9401745Abstract: A memory device may include an array of closely spaced memory integrated circuits that communicate wirelessly over at least two frequencies using near field coupling.Type: GrantFiled: December 11, 2009Date of Patent: July 26, 2016Assignee: Micron Technology, Inc.Inventor: Mostafa Naguib Abdulla
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Patent number: 9400308Abstract: The systems and method described herein provide efficient (e.g., low power and low area) techniques to track performance in numerous supply domains with heterogeneous circuits that are used in a large system-on-a-chip integrated circuit (SoCs). The heterogeneous circuits can include circuits made with different devices, different cell libraries, and different hard macros that are in different power supply domains. Performance measurements from performance sensors (or process-voltage-temperature (PVT) sensors) that are spread about the SoC are collected and processed to determine voltage levels for each of the supply domains. A single controller can receive can determine voltage levels for a whole SoC. The performance sensors are connected to the controller by a scan chain. The techniques are flexible and can be easily adapted for use in SoCs with different power supply domains and types of circuits.Type: GrantFiled: July 3, 2014Date of Patent: July 26, 2016Assignee: QUALCOMM IncorporatedInventors: Jasmin Smaila Ibrahimovic, Mohammad Reza Kakoee, Shih-Hsin Jason Hu
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Patent number: 9307346Abstract: A method and a system for remotely interacting with items in an electric field affected environment for communicating with a computing device is provided. The system includes a host for receiving commands from a computing device and a client for receiving and performing the signals received from the host. The host sends signals via modulated electric field. The client interacts with the items in the environment to determine their presence and location. The client further includes sensing devices and acting devices for sensing the condition of the items and manipulating the items respectively.Type: GrantFiled: December 25, 2013Date of Patent: April 5, 2016Inventors: Wolfgang Richter, Faranak Zadeh
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Patent number: 9295907Abstract: A gaming apparatus for interacting with at least one player for playing a game is provided. The gaming apparatus includes a gaming surface and a playing item interacts with the gaming surface through the capacitive coupling. The gaming surface receives power from a battery source and includes a generator for generating AC power, a conducting surface generates alternating electric field, a converter for converting AC power into DC power and a computing element for storing the game instructions.Type: GrantFiled: February 19, 2014Date of Patent: March 29, 2016Inventors: Wolfgang Richter, Faranak Zadeh
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Patent number: 9046574Abstract: A test circuit for a functional circuit includes a scan chain coupled to the functional circuit, and a controller coupled to the scan chain, for controlling the scan chain to scan a test pattern into the scan chain, and subsequently and repetitively for a multiple number of times launch the test pattern to the functional circuit, capture test data into the scan chain, and restore the test pattern in the scan chain for subsequent launch.Type: GrantFiled: November 28, 2012Date of Patent: June 2, 2015Assignee: ADVANCED MICRO DEVICES, INCInventors: Grady L. Giles, James A. Wingfield, Atchyuth K. Gorti
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Patent number: 9041460Abstract: A power package is provided comprising a packaged transistor and a driving unit connected to the transistor and adapted to drive the transistor. A control terminal of the transistor is connected to a middle terminal pin of the housing of the transistor and outer terminal pins of the housing are connected to the driving unit and to a voltage level, respectively, wherein the connections are crossing free.Type: GrantFiled: August 12, 2013Date of Patent: May 26, 2015Assignee: Infineon Technologies AGInventor: Ingo Voss
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Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC) (3DIC) and related methods
Patent number: 9041448Abstract: Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC)(3DIC) and related method are disclosed. In one embodiment, a single clock source is provided for the 3DIC and distributed to elements within the 3DIC. Delay is provided to clock paths by selectively controllable flip-flops to help provide synchronous operation. In certain embodiments, 3D flip-flop are provided that include a master latch disposed in a first tier of a 3DIC. The master latch is configured to receive a flip-flop input and a clock input, the master latch configured to provide a master latch output. The 3D flip-flop also includes at least one slave latch disposed in at least one additional tier of the 3DIC, the at least one slave latch configured to provide a 3DIC flip-flop output. The 3D flip-flop also includes at least one monolithic intertier via (MIV) coupling the master latch output to an input of the slave latch.Type: GrantFiled: March 5, 2013Date of Patent: May 26, 2015Assignee: QUALCOMM IncorporatedInventors: Yang Du, Jing Xie, Kambiz Samadi -
Publication number: 20150130500Abstract: The Configurable Vertical Integration [CVI] invention pertains to methods and apparatus for the enhancement of yields of 3D or stacked integrated circuits and herein referred to as a CVI Integrated Circuit [CVI IC]. The CVI methods require no testing of circuit layer components prior to their fabrication as part of a 3D integrated circuit. The CVI invention uses active circuitry to configure the CVI IC as a means to isolate or prevent the use of defective circuitry. CVI circuit configuration method can be predominately described as a large grain method.Type: ApplicationFiled: August 26, 2014Publication date: May 14, 2015Inventor: Glenn J. Leedy
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Patent number: 9030253Abstract: Integrated circuit (IC) packages with multiple clock sources are disclosed. A disclosed IC package includes a first die having a first clock source and a first clock tree and a second die having a second clock source and a second clock tree. The first clock source and the second clock source may be coupled to the second clock tree and the first clock tree, respectively, through a plurality of interconnects to form a clock tree network on the IC package. The clock tree network may be operable to be driven by either the first clock source or the second clock source.Type: GrantFiled: May 30, 2012Date of Patent: May 12, 2015Assignee: Altera CorporationInventor: Tony Ngai
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Publication number: 20150116031Abstract: The present disclosure provides a semiconductor device and an integrated apparatus having the same. The semiconductor device includes a substrate, a buffer layer on the substrate, a compensation area which includes a p-region and a n-region on the buffer layer, and a transistor cell on the compensation area. The transistor cell includes a source region, a body region, a gate electrode and a gate dielectric formed at least between the gate electrode and the body region. The gate dielectric has a thickness in a range of 12 nm to 50 nm.Type: ApplicationFiled: October 30, 2014Publication date: April 30, 2015Inventors: Uwe Wahl, Armin Willmeroth
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Monolithic three dimensional (3D) flip-flops with minimal clock skew and related systems and methods
Patent number: 9013235Abstract: Monolithic three dimensional (3D) flip-flops with minimal clock skew and related systems and methods are disclosed. The present disclosure provides a 3D integrated circuit (IC) (3DIC) that has a flop spread across at least two tiers of the 3DIC. The flop is split across tiers with transistor partitioning in such a way that keeps all the clock related devices at the same tier, thus potentially giving better setup, hold and clock-to-q margin. In particular, a first tier of the 3DIC has the master latch, slave latch, and clock circuit. A second tier has the input circuit and the output circuit.Type: GrantFiled: August 28, 2013Date of Patent: April 21, 2015Assignee: QUALCOMM IncorporatedInventors: Pratyush Kamal, Yang Du -
Publication number: 20150091747Abstract: An integrated circuit and a code generating method are described. The integrated circuit includes a plurality of field effect transistors, a plurality of sense-amplifiers, and a processing circuit. Each field effect transistor is configured to represent an address in a mapping table and includes a source, a drain, a channel and a gate. Each sense-amplifier is connected to the drain and configured to sense an electric current from the drain and identify a threshold voltage of the corresponding field effect transistor. The processing circuit is configured to categorize each of the threshold voltages identified by the corresponding sense-amplifiers into a first state and a second state and mark the state of each of the threshold voltages at the corresponding address in the mapping table.Type: ApplicationFiled: September 27, 2013Publication date: April 2, 2015Applicant: PHISON ELECTRONICS CORP.Inventor: Hiroshi Watanabe
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Publication number: 20150092777Abstract: An integrated circuit, a code generating method, and a data exchange method are described. The integrated circuit includes a plurality of field effect transistors, a plurality of sense-amplifiers, and a processing circuit. Each field effect transistor is configured to represent an address in a mapping table and includes a source, a drain, a channel and a gate. Each sense-amplifier is connected to the drain and configured to sense an electric current from the drain and identify a threshold voltage of the corresponding field effect transistor. The processing circuit is configured to categorize each of the threshold voltages identified by the corresponding sense-amplifiers into a first state and a second state and mark the state of each of the threshold voltages at the corresponding address in the mapping table.Type: ApplicationFiled: July 21, 2014Publication date: April 2, 2015Inventor: Hiroshi Watanabe
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Patent number: 8994223Abstract: Disclosed is a self-powering system for electronic circuits by detecting and converting the energy of electric field lines provided from the generator of device in the proximity of the electronic circuit. The harvesting of electric field energy by using means of capacitive coupling (contactless or (in-) direct contact) to field inducing power sources replaces or reduces the need of batteries e.g. for mobile devices, medical sensors, energy efficient circuits (e.g. stand-by) or (near field-) communication devices. A wide range of applications and technical solutions from smart labels, e-ink devices, shutter glasses, or electronic sensors up to electronic devices of any kind, can use the invention's means to power (integrated) circuits microcontrollers, light emitting items (LED) or any circuit where batteries or other power sources can be replaced by the innovation.Type: GrantFiled: September 22, 2011Date of Patent: March 31, 2015Assignee: R2Z Innovations Inc.Inventors: Wolfgang Richter, Faranak Zadeh
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Patent number: 8981841Abstract: A semiconductor integrated circuit includes a plurality of semiconductor chips respectively selected in response to a plurality of chip selection signals, and a chip selection signal generator configured to generate the chip selection signals in response to one first control signal for deciding whether to drive the semiconductor chips and at least one second control signal for selecting at least one semiconductor chip from among the semiconductor chips.Type: GrantFiled: September 20, 2011Date of Patent: March 17, 2015Assignee: Hynix Semiconductor Inc.Inventors: Jae-Bum Ko, Jong-Chern Lee, Sang-Jin Byeon
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Publication number: 20150061759Abstract: A monolithic power switch provides a semiconductor layer, a three dimensional FET formed in the semiconductor layer to modulate currents through the semiconductor layer, and a toroidal inductor with a ceramic magnetic core formed on the semiconductor layer around the FET and having a first winding connected to the FET.Type: ApplicationFiled: June 9, 2014Publication date: March 5, 2015Inventor: L. Pierre de Rochemont
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Patent number: 8970250Abstract: Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data.Type: GrantFiled: November 1, 2012Date of Patent: March 3, 2015Assignee: Tabula, Inc.Inventors: Martin Voogel, Jason Redgrave, Trevis Chandler
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Patent number: 8954125Abstract: Low-loss superconducting devices and methods for fabricating low loss superconducting devices. For example, superconducting devices, such as superconducting resonator devices, are formed with a (200)-oriented texture titanium nitride (TiN) layer to provide high Q, low loss resonator structures particularly suitable for application to radio-frequency (RF) and/or microwave superconducting resonators, such as coplanar waveguide superconducting resonators. In one aspect, a method of forming a superconducting device includes forming a silicon nitride (SiN) seed layer on a substrate, and forming a (200)-oriented texture titanium nitride (TiN) layer on the SiN seed layer.Type: GrantFiled: July 28, 2011Date of Patent: February 10, 2015Assignees: International Business Machines Corporation, The United States of America, as represented by the Secretary of Commerce, The National Institute of StandardsInventors: Antonio D. Corcoles Gonzalez, Jiansong Gao, Dustin A. Hite, George A. Keefe, David P. Pappas, Mary E. Rothwell, Matthias Steffen, Chang C. Tsuei, Michael R. Vissers, David S. Wisbey
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Publication number: 20150033050Abstract: A semiconductor integrated circuit and a computing system including the same are provided. The semiconductor integrated circuit includes: an integrated clock gating cell including a clock output node; and clock-based cells each including a clock input node. The clock output node of the integrated clock gating cell and the clock input nodes of the clock-based cells are aligned on a straight line and commonly connected to a clock gating path.Type: ApplicationFiled: July 25, 2013Publication date: January 29, 2015Applicant: SAMSUNG ELECTRONICS CO., LTDInventors: Amjad QADAN, Neil PANCHAL
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Patent number: 8937503Abstract: A switch control circuit has a first terminal, a second terminal, a third terminal, a serial-parallel converter, a selector, a driver circuit and a tri-state buffer. The serial-parallel converter converts a serial switching control signal inputted from the third terminal into first parallel switching control signals when the first terminal is at a first power-supply potential. The selector selects either the first parallel switching control signals converted by the serial-parallel converter or second parallel switching control signals inputted into the second and third terminals, depending on the potential of the first terminal. The driver circuit converts potential levels of the first parallel switching control signals or the second parallel switching control signals selected by the selector and generates parallel switching control signals with potential levels capable of switching a switch circuit.Type: GrantFiled: November 21, 2013Date of Patent: January 20, 2015Assignee: Kabushiki Kaisha ToshibaInventor: Toshiki Seshita
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Publication number: 20140375380Abstract: According to a method herein, a portion of an electronic circuit is identified. The electronic circuit comprises logic circuitry. The portion of the electronic circuit is designed in at least two versions. Each of the at least two versions is evaluated using a plurality of operating conditions. The current operating conditions are determined. One version of the at least two versions is identified as a selected version based on the performance under the current operating conditions. The selected version has relatively optimal performance based on at least one of clock frequency, supply voltage, and power limit. The selected version is activated for use in the portion of the electronic circuit. The remaining versions of the at least two versions are deactivated.Type: ApplicationFiled: June 19, 2013Publication date: December 25, 2014Inventors: John M. Cohn, David J. Hathaway, Sridhar H. Rangarajan, Diyanesh Babu C. Vidyapoornachary