Abstract: The invention relates to a current regulator having the following features: a first semiconductor body (1; 1?) having a first and second terminal contact (11, 12), a transistor (T) having a control terminal and a load path, which is integrated in the semiconductor body (1; 1?) and the load path of which runs between the terminal contacts (11, 12) of the semiconductor body, a current measuring resistor (22), which is at least partly formed by a section of the load path of the transistor, an evaluation and drive circuit (3), which is connected to the current measuring resistor (22) and which is designed to drive the transistor depending on a voltage across the measuring resistor (22).

Abstract: A power line control circuit of a semiconductor device in which a width of a power line can be selectively controlled. The power line control circuit of the semiconductor device according to the present invention can selectively control the width of the power line employing the dummy power line. It is therefore possible to easily change the width of the power lines and to reduce the manufacturing cost and the manufacturing time depending on the formation of the power lines. Furthermore, the power line control circuit of the semiconductor device according to the present invention can selectively control the width of the power lines, if appropriate. Accordingly, mesh of optimized power lines can be provided. Furthermore, more stabilized product characteristics can be secured and the yield of semiconductor memory devices can be enhanced.

Abstract: An IC chip has a series regulator built therein. A battery voltage is applied to an input pin. An output of a transistor constituting the series regulator occurs at an output pin via an output pad. A feedback signal derived from an output voltage occurs at an end of a voltage division resistor via a feedback pad. Diodes connect the output pad and the feedback pad.

Abstract: A highly integrated radio front-end module. In one embodiment a semiconductor substrate is processed with various circuit components in the substrate, as well as interconnections for the various circuit components, embedding the circuit components into the substrate. One or more circuit components may be further connected with a separate integrated circuit, the separate integrated circuit bonded to the semiconductor substrate via contact points processed into the substrate.

Abstract: A radio frequency integrated circuit (RFIC) includes a digital to analog converter, an analog to digital converter, and a radio module. The digital to analog converter (DAC) is operably coupled to convert outbound symbols into outbound baseband signals, wherein the digital to analog converter is fabricated within a DAC portion of a substrate of the RFIC. The analog to digital converter (ADC) is operably coupled to convert inbound baseband signals into inbound symbols, wherein the analog to digital converter is fabricated within an ADC portion of the substrate. The radio module is operably coupled to convert the outbound baseband signals into outbound radio frequency (RF) signals and to convert inbound RF signals into the inbound baseband signals. The radio module is fabricated within a radio portion of the substrate, wherein the DAC portion of the substrate is physically between the ADC portion and the radio portion of the substrate.

Abstract: In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.

Abstract: A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.

Abstract: A method of power consumption reduction in integrated circuits comprising extensive use of differential signaling within said circuits. Differential signaling comprises a pair of coupled, symmetrically opposite and operatively dependent electronic signals each driven by voltages of the same magnitude, but of opposite polarity with respect to a common ground. The drive voltages of each signal are of relatively low potential as compared to the core operating voltage of present day devices. The low-voltage pair of signals tends to create offsetting fields of electromagnetic interference from the flow of current within their respective conductors which tends to minimize inductive effects (and therefore corruption of signals) in adjacent signal lines. Differential signaling replaces all or as many single-end signals as possible throughout the device resulting in relatively lower power usage as compared to present devices.

Abstract: A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.

Abstract: A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.

Abstract: Integration and terminal arrangement of serially-connected parallel monitor circuits, capable of monitoring the terminal voltages of serially-connected capacitors, are disclosed. A semiconductor device has a predetermined number of parallel monitor circuits, corresponding to a number of capacitors existing in the system. The semiconductor device includes a number of capacitor terminals and transistor terminals distributed on a capacitor side surface or a capacitor side, and a number of connector terminals distributed on the side surface opposite to the capacitor side surface or the side opposite to the capacitor side.

Abstract: The method provides wide-range delay value adjustment without making changes in cell size and metal wiring, even when a process variation occurs. Threshold values of some or all of the transistors which form the delay gate inserted into the signal path are varied to control the delay value of the delay gate, so that the delay value of the signal path is adjusted.

Abstract: A semiconductor device capable of setting a large number of operation modes with a single external terminal, while ensuring a stable operation mode regardless of fluctuations in the power supply voltage. The semiconductor device includes an internal circuit having a plurality of modes, an external terminal, an external resistor connected to the external terminal, and a current detection circuit for generating a setting signal based on the current flowing through the external resistor. The internal circuit includes a mode setting circuit which sets one of the operation modes of the internal circuit in response to the setting signal.

Abstract: An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the rows. Tag assignment logic blocks are coupled to the data dependency comparator blocks to receive dependency information. The tag assignment logic blocks are positioned in one or more of the layout regions so as to be integrated with the data dependency comparator blocks to conserve area on the semiconductor chip and to spatially define a channel in and substantially orthogonal to one or more of the rows. Register file port multiplexer blocks are coupled to output lines of the tag assignment logic block adjacent to the orthogonal channel to receive tag information and to pass the tag information to address ports of a register file.

Abstract: A printed circuit board is built including metal traces for a differential clock. Within a break in each metal trace pads for a delay line socket are included along with pads for two 0-ohm resistors in series. In between the two 0-ohm resistors metal traces are build in a configuration to provide a specified delay in a signal passing through the trace. This group of pads and traces allows a designer to test (on the completed printed circuit board) differential clocks in modes including negative skew. In normal operation, the 0-ohm resistors are present on the printed circuit board and the clock signals pass through the metal traces build in a configuration to provide a specified delay in the signals passing through the traces. During testing, delay lines may be placed in the delay line sockets and the 0-ohm resistors may be removed.

Abstract: Provided a method of reducing impedance variations in an electrical circuit structured and arranged for placement on an integrated circuit (IC) substrate. The method includes forming sets of parallel connected resistors, each set corresponding to one of the impedance devices on the IC. Each set also includes two or more parallel resistor paths, each resistor path including two or more cascaded resistors and has a total impedance value substantially equal to the predetermined impedance value of its corresponding impedance device. Finally, the method includes configuring the sets of parallel resistor paths to form an interdigital structure across the substrate when the electrical circuit is placed on the IC.

Abstract: High-gain synchronizer circuitry and methods are provided that reduce the meta-stable resolve time of a synchronizer circuit. The high-gain synchronizer is made up of high-gain latch circuits. The high-gain latch circuits are made up of a series of inverters that at least initially increase in size and that are connected in a closed loop. In accordance with the invention, the time that the high-gain synchronizer remains in the meta-stable state is minimized through the use of the high-gain latch circuits.

Abstract: A power supply cell is arranged in the corner of a rectangular semiconductor chip. A first or second power supply voltage is supplied to a pad of the power supply cell. A first connecting line of the power supply cell connects a first power supply line in an input/output cell area to a first power supply line in a power supply line area. A second connecting line of the power supply cell connects a second power supply line in the input/output cell area to a second power supply line in the power supply line area. A leadout line of the power supply cell connects the first or second connecting line to the pad.

Abstract: An RFIC includes a baseband processing module, a digital to analog converter, an analog to digital converter, a radio module, and a border section. The border section is fabricated on the substrate, wherein the border section physically separates the radio module from the baseband processing module, the digital to analog converter, and the analog to digital converter, wherein the border section includes noise suppression circuitry operably coupled to convert outbound baseband signals into low noise outbound baseband signals and to convert low noise inbound baseband signals into inbound baseband signals.

Abstract: A semiconductor integrated circuit comprising a first circuit block including an oscillation circuit considered to be a noise generator and a second circuit block including circuits considered to be easily affected by a noise generated by the oscillation circuit, being most likely led to a malfunction are created on a single semiconductor substrate with the first and second circuit blocks separated from each other. To put it more concretely, the first and second circuit blocks are respectively created in a first island area and a second island area on the surface of the semiconductor substrate. The first and second island areas are each enclosed by an insulating isolation band. A low-resistance semiconductor area is created in a base area excluding locations occupied by active elements in the first and second island areas and is connected to a stable voltage terminal.

Abstract: A semiconductor integrated circuit comprises therein a plurality of logic circuits synchronously designed to operate in synchronization with a clock signal, a first power supply wire for supplying a high-potential side power supply voltage from a first input terminal to each logic circuit, a second power supply wire for supplying the high-potential side power supply voltage from a second input terminal to each logic circuit and a third power supply wire for supplying the high-potential side power supply voltage from a third input terminal to each logic circuit. The logic circuit (DFF circuit) includes two stages of latch circuits and a clock signal inversion circuit. Only the clock signal inversion circuit is connected with the first power supply wire, while the second power supply wire is connected with the remaining latch circuits.

Abstract: In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.

Abstract: Mode detection circuitry includes first detection circuitry which detects the presence of a first input signal selectively presented at a first terminal for a first selected time duration and, in response, selectively generating a first control signal indicative of a first mode. Second detection circuitry detects the presence of a second input signal selectively presented at a second terminal for a second selected time duration and, in response, selectively generating a second control signal indicative of a second mode. Control circuitry configures the second terminal as an output terminal in the first mode and as an input terminal in the second mode in response to the first and second control signals.

Abstract: The present invention provides a method to balance a clock tree dynamically. A controllable buffer is inserted in a specific level of a clock tree, and a controller is provided for adjusting two clocks with different skew by controlling the PMOS/NMOS arrangements in the controllable buffer so as to generate more current for compensating the time delay of slow clock to a sink. This method effectively suppressed the clock skew generated by the voltage drop or the temperature variations in the synchronous logic circuit design.

Abstract: In an integrated circuit device, a clock signal distribution section is arranged in an outer circumferential area of a semiconductor chip to supply a clock signal. Each of interface circuit blocks has at least an internal circuit operating based on the clock signal supplied from the clock signal distribution section.

Abstract: The reconfigurable analog cell according to the invention comprises admittances yab having first terminals (a) which are coupled to first terminals SW1 of a first plurality of switches, and having second terminals which are coupled to the first terminals SW1 of a second plurality of switches. The switches having second terminals, wherein each one of the second switch terminals SW2 of the first plurality of switches and of the second plurality of switches is coupled to at least one node of a plurality of nodes. In the arrangement only one of the switches from any plurality is ON. Therewith a particular state of a plurality of possible states (PSPPS) of the RAC (100) is defined, each of the states defining a transfer function having the same set of poles.

Abstract: A high frequency switching device includes a control terminal, a power source terminal, a GND terminal, an RF terminal, a switch section, a control section, and protecting diodes. The switch section switches input/output routes of an RF signal input from the RF terminal. The control section controls the switching section, and is connected to the control terminal and the power source terminal. The protecting diodes are provided between the control terminal and the RF terminal, between the control terminal and the GND terminal, and between the power source terminal and the GND terminal.

Abstract: Current consumption of an input unit with respect to a bonding option pad is reduced, and erroneous operation of a circuit connected to this bonding option pad is prevented. A boundary scan test circuit is selectively set to an operable or disabled state by a control gate according to a signal from a function set circuit that sets the operation mode according to a potential of a bonding pad. By particularly controlling the operable and disabled state of an input circuit located at the first stage of the test circuit, power consumption can be reduced and erroneous operation while the test circuit is disabled is prevented.

Abstract: Provided a method of reducing impedance variations in an electrical circuit structured and arranged for placement on an integrated circuit (IC) substrate. The method includes forming sets of parallel connected resistors, each set corresponding to one of the impedance devices on the IC. Each set also includes two or more parallel resistor paths, each resistor path including two or more cascaded resistors and has a total impedance value substantially equal to the predetermined impedance value of its corresponding impedance device. Finally, the method includes configuring the sets of parallel resistor paths to form an interdigital structure across the substrate when the electrical circuit is placed on the IC.

Abstract: The present invention provides a hermetic or open compressor for hydrocarbon refrigerant having high reliability. According to the present invention, in the compressor using hydrocarbon as refrigerant, synthetic oil such as polyalkylene glycol oil, ester oil or ether oil is used as freezer oil. Sliding member of the compressor includes both a portion made of aluminum material and a portion made of iron material. Therefore, it is possible to realize a compressor having excellent wear resistance and high reliability.

Abstract: A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.

Abstract: In electronic equipment, such as, for example, a personal computer printed circuit board, an arrangement for mitigating EMI, noise and other spurious signals at high frequencies. The arrangement includes a discrete capacitor coupled between an active pad and a reference pad. A conductor is coupled to the discrete capacitor and is configured to include a serpentine trace and a terminating tuning capacitance that are effectively series resonant at a predetermined frequency. In an exemplary embodiment, the serpentine trace comprises a number of substantially linear, mutually parallel segments that are joined by turns. The length and width of the serpentine trace, together with the number and spacing of linear segments, cooperates with the geometry of the tuning capacitance to determine the frequency of maximum attenuation of spurious signals.

Abstract: A composite rectifying charge storage device, consisting of a rectifier and capacitor which share common elements, is combined in a circuit with an antenna for remote energization in response to an external electromagnetic or electrostatic AC field. The energized composite device extracts power (voltage or current) and may be implemented in a variety of circuit configurations, such as a power supply for driving circuit components, e.g., radio frequency identification (RFID) circuitry, or for use in parameter sensing applications which may include a light emitting component, and others.

Abstract: A semiconductor integrated circuit including a digital circuit and an analog circuit which are integrated on a single semiconductor chip comprises a first electrostatic destruction protection circuit, connected to a digital circuit, for protecting the digital circuit from destruction caused by ESD therein by an influence of an input digital signal and a second electrostatic destruction protection circuit, connected to an analog circuit, for protecting the analog circuit from destruction caused by ESD therein by an influence of an input analog signal. A first grounding conductor connected to the first electrostatic destruction protection circuit and a second grounding conductor connected to the second electrostatic destruction protection circuit are connected to each other outside the semiconductor integrated circuit.

Abstract: A semiconductor integrated circuit includes a first pad mounted on a main surface of a semiconductor substrate, a second pad mounted on the main surface and positioned adjacent to the first pad, a pad joint mounted between the first pad and the second pad to connect the first pad and the second pad, a first signal input/output circuit including a first output buffer connected to the first pad, a second signal input/output circuit including a second input buffer connected to the second pad, and a second output buffer connected to the second pad and including an output section having a controllable output impedance, an input/output signal control circuit connected to the first signal input/output circuit and the second signal input/output circuit.

Abstract: Described are methods and systems for distributing low-skew, predictably timed clock signals. A clock distribution network includes a plurality of dynamically adjustable clock buffers. A control circuit connected to each clock buffer controls the delays through the clock buffers in response to process, voltage, and temperature variations, and consequently maintains a relatively constant signal-propagation delay through the network. In one embodiment, each clock buffer includes skew-offset circuitry that adds to or subtracts from the PVT compensated delay values provided by the PVT control circuit to simplify clock skew minimization.

Abstract: A mux scan cell includes a multiplexer having a first input node for receiving raw data, a second input node for receiving test data, an output node, a selection node, and a delay circuit electrically connected between the second input node and the output node for prolonging a traveling time which the test data takes to travel from the second input node to the output node. The mux scan cell also includes a flip-flop connected to the multiplexer. With the delay circuit, the traveling time of the test data is prolonged such that the traveling time which the test data takes to travel from the second input node to the output node simulates a sum of a traveling time in which the raw data travels through a combinational logic and a traveling time in which the raw data travels from the first input node to the output node.

Abstract: The respective ends of input wiring on a printed wiring board of a signal transmission circuit are connected to an input terminal section and a transistor. One terminal of a first capacitor and a first resistor are respectively connected to the input wiring. A leading-side transmission path from a connection point with the first capacitor to a connection point with the input terminal section is formed by only a conductive pattern. An intermediate transmission path from the connection point with the first capacitor to a connection point with the first resistor includes two or more through holes or via holes. The intermediate transmission path is placed near grounding wiring on the printed wiring board. When one terminal of a second capacitor is connected to the intermediate transmission path, a transmission path between the respective connection points with the two capacitors includes one or more through holes or via holes.

Abstract: A resistive divider for a voltage multiplier circuit minimizes output voltage overshoot by capacitively coupling the tap point of the resistive divider to the output terminal of the voltage multiplier circuit via the parasitic capacitance of the resistive divider. For a resistive divider that includes a resistive structure formed over a dielectric layer formed on a doped well, this capacitive coupling can be performed by connecting the well to the output terminal of the voltage multiplier circuit. This capacitive coupling improves the response time of the resistive divider, so that a scaled test voltage read from the tap point varies more rapidly than the elevated output voltage of the voltage multiplier circuit. Therefore, the scaled test voltage provides charging control that increases the elevated output voltage in gradual increments that prevent the elevated output voltage from exceeding a target output voltage.

Abstract: An IC chip 10 is divided into the analog circuit area 1 and a digital circuit area 2 in its layout. A clock generator circuit 6 that generates a clock signal CK is arranged within the digital circuit area 2, and a switching circuit 4 that performs switching operations by the clock signal CK is also arranged within the digital circuit area 2. This enables shortening of the wiring length of the clock line 9, which is routed from the clock generator circuit 6 to the switching circuit 4, and also enables the distance between the clock line 9 and the analog circuits within the analog circuit area 1 to be as great as possible. Through this, inconvenience where digital noise caused by the clock signal flowing through the clock line 9 jumps into analog circuits can be suppressed.

Abstract: An apparatus and method for a sensing circuit for cancelling an offset voltage. Specifically, in one embodiment, a CMOS inverter amplifier amplifies an input signal present at an input node. A resistive feedback circuit is coupled to the CMOS inverter amplifier for cancelling an offset voltage that is associated with the CMOS inverter amplifier. This is accomplished by biasing the CMOS inverter amplifier to its threshold voltage. A bias circuit is coupled to the resistive feedback circuit for biasing MOSFET transistors in the resistive feedback circuit at a subthreshold conduction region. As such, the resistive feedback circuit presents a high impedance to the input node. A clamping circuit, coupled to the resistive feedback circuit, maintains operation of the transistors in the resistive feedback circuit in the subthreshold conduction region.

Abstract: A non-inverting-side first switch is formed in a first area on one of sides of a differential amplifier, meanwhile a non-inverting-side second switch is formed in a second area on the other of sides of the differential amplifier, the non-inverting switches being for resetting a non-inverting input terminal of the differential amplifier. Similarly, An inverting-side first switch is formed in the first area, meanwhile an inverting-side second switch is formed in the second area, the inverting switches being for resetting a non-inverting input terminal of the differential amplifier. Further, a non-inverting-side line connecting the non-inverting-side first switch and the non-inverting input terminal, and an inverting-side line connecting the inverting-side first switch and the inverting-side second switch are provided next to each other. A signal line crossing one of the lines is provided so as to cross the other of the lines.

Abstract: A rectifying charge storage device, consisting of a rectifier and capacitor which share common elements, includes a sensor responsive to a monitored parameter such as pressure or the presence of a target chemical agent, to produce a variable and detectable electronic signal representative of the monitored parameter.

Abstract: A set of high speed interconnect lines for an integrated circuit has an improved line-to-line capacitance and overall RC time constant. The high speed interconnect line set incorporates a series of interconnect lines, wherein shorter run lines are routed between longer run lines. As the short run interconnect lines reach their destination and fall away they open up the line spacing and improve the line-to-line capacitance that dominates capacitive effects in modern reduced feature size integrated circuits. Additionally, the cross sectional area of the interconnect lines can be increased to lower the line resistance of longer run lines and compensate for the line capacitance without increasing the line-to-line capacitance. The capacitances, resistances, and RC time constants can be optimized for a single line of a group or for the entire group of interconnect lines, providing a low average value or a uniform value across all lines for uniform propagation delay.

Abstract: In an electronic device supplying a DC power to an LSI chip (20), a noise filter (1) of a distributed constant type, having an input port (2, 3) and an output port (5, 4), is mounted on a circuit board (6). The noise filter (1) reduces high-frequency noise incoming thereto and allows DC current to flow therethrough. The input port (2, 3) is connected to a DC power line (7a) and a ground conductor (8a) on the circuit board (6). The output port (5, 4) is connected to a separate power conductor (7b) and a separate ground conductor (8b) which are connected to the LSI (20) mounted on the circuit board (6). In another embodiment, the LSI (20) is mounted on a different circuit board (17) to which the output port (5, 4) is connected through conductor pins (18, 19) standing on the circuit board (6).

Abstract: The invention relates to a switching device comprising a matrix having connection points and integrated test means comprising two pairs of generators/detectors which are pairwise controlled in such a way that the transmission paths traversed by the RF test signals from the generators to the associated inputs of the matrix and from the outputs of the matrix and to the associated detector are of the order of length of a single side of the switching matrix.

Abstract: A floorplan for a reconfigurable chip uses slices adjacent to each of four corners of a region, each of the slices including tiles that contain multiple reconfigurable functional units including ALUs. The placement of the slices in the corners of their region allows for better and quicker interconnection between elements on the slices.

Abstract: RF filter circuits are described which include a bottom dielectric substrate fabricated of a high dielectric material having a relative dielectric constant in a range of 30 to 100. A conductor pattern defining a circuit topology is fabricated on a surface of the substrate.

Abstract: A signal pathway is presented for routing clock signals from a clock driving device to a circuit component and on to a termination. The signal pathway employs a minimal stub to carry the clock signals to the circuit component without introducing excess signal distortions. A first signal line of the signal pathway is formed on a circuit board and extends from the clock driving device to a first terminal for interfacing with the circuit component. A second signal line of the signal pathway is routed on the circuit component from one end adjacent to and electrically coupled with the first terminal to an opposite end adjacent to and electrically coupled with a second terminal formed on the circuit board. The stub extends from the second signal line on the circuit component. A third signal line of the signal pathway extends on the circuit board from the second terminal to the termination.

Abstract: An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the rows. Tag assignment logic blocks are coupled to the data dependency comparator blocks to receive dependency information. The tag assignment logic blocks are positioned in one or more of the layout regions so as to be integrated with the data dependency comparator blocks to conserve area on the semiconductor chip and to spatially define a channel in and substantially orthogonal to one or more of the rows. Register file port multiplexer blocks are coupled to output lines of the tag assignment logic block adjacent to the orthogonal channel to receive tag information and to pass the tag information to address ports of a register file.