With Bootstrap Circuit Patents (Class 327/589)
  • Patent number: 9979286
    Abstract: A power converting device, in one possible configuration, includes a chopper circuit with a first semiconductor switching device, a fast recovery diode, and an inductor of which one end is connected to a connection point connecting between the first semiconductor switching device and fast recovery diode; a series circuit, connected in parallel with the fast recovery diode, including a rectifying diode with a greater reverse recovery loss and a smaller forward voltage drop than those of the fast recovery diode, and a second semiconductor switching device. The second semiconductor switching device has a lower breakdown voltage and a smaller forward voltage drop than those of the first semiconductor switching device, is configured to turn on when the first semiconductor switching device is turned off, and is configured to turn off at a timing before the first semiconductor switching device shifts from an off-state to an on-state.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: May 22, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Ryuji Yamada
  • Patent number: 9761305
    Abstract: One embodiment describes a quantum memory system. The system includes an array controller that comprises a plurality of flux pumps configured to provide write currents in a write operation and read currents in a read operation with respect to a plurality of quantum memory cells, the array controller being configured to control timing associated with the write operation and the read operation in response to memory request signals based on application of the write currents and the read currents and based on recharging flux associated with the plurality of flux pumps.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: September 12, 2017
    Assignee: Northrop Grumman Systems Corporation
    Inventors: William Robert Reohr, Steven Brian Shauck, Donald Lynn Miller, Jeremy William Horner, Nathan Trent Josephsen
  • Patent number: 9306553
    Abstract: Certain aspects of the present disclosure provide a voltage level shifting circuit employing a low latency, AC-coupled voltage boost circuit, as well as other circuits and apparatus incorporating such a level shifting circuit. Such level shifting circuits provide significantly lower latency compared to conventional level shifters (e.g., latency reduced by at least a factor of two). Offering consistent latency over the simulation corners, level shifting circuits described herein also provide significantly lower power consumption and reduced duty cycle distortion compared to conventional level shifters.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: April 5, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Omid Rajaee, Wei Zheng, Dinesh Jagannath Alladi, Yuhua Guo
  • Patent number: 9286218
    Abstract: In a spin-torque magnetic random access memory (MRAM) that includes local source lines, auto-booting of the word line is used to conserve power consumption by reusing charge already present from driving a plurality of bit lines during writing operations. Auto-booting is accomplished by first driving the word line to a first word line voltage. After such driving, the word line isolated. Subsequent driving of the plurality of bit lines that are capacitively coupled to the word line causes the word line voltage to be increased to a level desired to allow sufficient current to flow through a selected memory cell to write information into the selected memory cell. Additional embodiments include the use of a supplemental voltage provider that is able to further boost or hold the isolated word line at the needed voltage level.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: March 15, 2016
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Syed M. Alam
  • Patent number: 9245602
    Abstract: A memory device with word-line voltage boosting includes a set of first switches that are operable to couple a word-line of the memory device to a supply voltage to pull the word-line up to a rail voltage. A dummy line including a conductive route can be disposed in a vicinity of the word-line to form a parasitic coupling capacitance with the word-line. A second switch is operable to couple the dummy line to the supply voltage to pull the dummy line to the rail voltage. Pulling up the dummy line boosts the word-line voltage above the rail voltage by a boost voltage.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: January 26, 2016
    Assignee: Broadcom Corporation
    Inventor: Sachin Joshi
  • Patent number: 9165917
    Abstract: Each one of a pair of CMOS transistors is formed in its own island and a gate terminal for each transistor is formed by a single, in-line conductor connecting both gate terminals together. This type of “in-line” connection achieves nearly a five-time improvement in the reduction of the ability of ionizing radiation particles to strike both transistors at the same time as compared to prior art “side-by-side” transistor stacking through use of a relatively smaller solid angle spanning the two transistors. This results in “hardening” of the transistors and improving their resistance to single event upsets and, thus, improving the soft error rate (SER) of the transistors.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: October 20, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ethan H. Cannon, David F. Heidel, K. Paul Muller, Alicia Wang
  • Patent number: 9106165
    Abstract: A voltage output circuit includes: an oscillator circuit configured to output an oscillation signal while changing an oscillation frequency thereof; and a voltage generating circuit configured to convert a first voltage into a second voltage higher than the first voltage, and output the second voltage, based on the oscillation signal.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: August 11, 2015
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yasuyuki Takamori, Shinobu Shioda
  • Patent number: 9065437
    Abstract: A circuit for driving a transistor includes a drive circuit, a first voltage boost circuit and a second voltage boost circuit. The drive circuit has a first specific node, a second specific node, and a third specific node coupled to a control node of the transistor. The drive circuit is arranged for coupling the first specific node to the third specific node according to at least a voltage of the first specific node and a voltage of the second specific node in order to charge the control node. The first voltage boost circuit is coupled between the first specific node and a connection node of the transistor, and is arranged for boosting the voltage of the first specific node. The second voltage boost circuit is coupled between the first specific node and the second specific node, and is arranged for boosting the voltage of the second specific node.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: June 23, 2015
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventors: Wee Guan Tan, Siong Siew Yong
  • Patent number: 9065444
    Abstract: A power-up initial circuit includes a power-up control unit, a first switch and a second switch. The power-up control unit is used for receiving a high voltage start-up signal, and generating a first power-up control signal. The first switch has a first terminal for receiving an external voltage, a second terminal for coupling to the power-up control circuit for receiving the first power-up control signal, and a third terminal. The second switch has a first terminal coupled to the third terminal of the first switch, a second terminal for coupling to the power-up control circuit for receiving the first power-up control signal, and a third terminal for coupling to a high voltage generator.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: June 23, 2015
    Assignee: Etron Technology, Inc.
    Inventors: Yen-An Chang, Hao-Jan Yang, Chun Shiah
  • Patent number: 9000836
    Abstract: Embodiments are provided that include a circuit for generating voltage in a memory. One such circuit includes a charge pump circuit including a first transistor, a high-voltage switch circuit, and a cut-off switch circuit arranged to reduce leakage current from the charge pump circuit. The cut-off switch circuit includes a second transistor, wherein an output of the charge pump circuit is coupled to one of a source node and a drain node of the second transistor, and a first control signal is input at a gate of the second transistor. Further embodiments provide a method for generating voltage. One such method includes enabling a first transistor coupled to an output of a charge pump circuit when the charge pump is operating and disabling the first transistor coupled to the output of the charge pump circuit when the charge pump circuit is not operating.
    Type: Grant
    Filed: January 10, 2008
    Date of Patent: April 7, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Patent number: 8994439
    Abstract: A semiconductor device which has reduced power consumption and includes a selection transistor is provided. A semiconductor device in which the number of wirings and terminals for inputting a power supply potential is reduced and which operates at high speed is provided. A buffer circuit connected to a gate line connected to a gate of the selection transistor has a function of generating a potential higher than a high power supply potential by using the high power supply potential and outputs the potential depending on the selection signal. A bootstrap circuit boosts a high power supply potential that is input to an inverter that is the closest to an output side among a plurality of inverters included in a buffer circuit. Further, by providing a delay circuit in the buffer circuit, the bootstrap circuit starts to boost a potential at the timing later than the input of the selection signal.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: March 31, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Makoto Kaneyasu, Kouhei Toyotaka
  • Patent number: 8981843
    Abstract: This document discusses, among other things, a control circuit, such as a translator circuit, configured to reduce voltage stress of first and second transistors when a first voltage received by the first transistor exceeds a voltage rating of at least one of the first or second transistors.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: March 17, 2015
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Nickole Gagne, Kenneth P. Snowdon
  • Patent number: 8963630
    Abstract: In accordance with an embodiment, a method includes activating a first semiconductor switch having a first switch node coupled to a first input of a bootstrap circuit, a second switch node, and a control node coupled to a first end of a capacitor of the bootstrap circuit. A first end of the capacitor is coupled to the first input of the bootstrap circuit and a second end of the capacitor is set to a first voltage. Next, the first end of the capacitor is decoupled from the first input of the bootstrap circuit, and the second end of the capacitor is set to a second voltage. The control node is boosted to a first activation voltage that turns on the first semiconductor switch.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: February 24, 2015
    Assignee: Infineon Technologies AG
    Inventors: Jose Luis Ceballos, Christian Reindl
  • Patent number: 8901912
    Abstract: A bootstrap capacitor detecting circuit includes a current source, for providing a discharging current; a first switch, for conducting connection between a system voltage and a bootstrap voltage node according to a power-on-reset signal, to charge the bootstrap voltage node; a second switch, for conducting connection between a current source and the bootstrap voltage node according to the power-on-reset signal, to discharge the bootstrap voltage node; and a detecting unit, for determining whether a bootstrap capacitor is connected normally according to a bootstrap voltage of the bootstrap voltage node after the current source discharges the bootstrap voltage node.
    Type: Grant
    Filed: January 21, 2013
    Date of Patent: December 2, 2014
    Assignee: Anpec Electronics Corporation
    Inventors: Tsung-Kuan Lee, Chih-Yuan Chen
  • Patent number: 8847673
    Abstract: A conventional circuit requires a booster circuit for generating a voltage higher than an external power supply voltage, thus low power consumption is difficult to be achieved. In addition, a display device incorporating the aforementioned conventional switching element for booster circuit has problems in that the current load is increased and the power supply becomes unstable with a higher output current.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: September 30, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 8841959
    Abstract: Disclosed is a noise removing circuit including: a voltage booster which boosts an input signal; and a regulator which receives an output signal of the voltage booster and reduces the signal's voltage higher than a specific value to the signal's voltage having the specific value and then outputs the signal.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: September 23, 2014
    Assignee: HiDeep Inc.
    Inventors: Seyeob Kim, Youngho Cho, Bonkee Kim
  • Patent number: 8836380
    Abstract: A semiconductor device, includes: a first field effect transistor having one terminal to which a first electrical potential is given; a second field effect transistor having one terminal to which a second electrical potential smaller than the first electrical potential is given; a controller that controls each electrical potential of each control terminal of the first field effect transistor and the second field effect transistor; a capacitor element having one end connected to the control terminal of the first field effect transistor, the capacitor element being charged by the control of the controller; and a load element connected between another terminal of the first field effect transistor and another terminal of the second field effect transistor.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: September 16, 2014
    Assignee: Transphorm Japan, Inc.
    Inventor: Yoshihiro Takemae
  • Patent number: 8816748
    Abstract: An apparatus comprising a level shifter circuit and a control circuit. The level shifter circuit may be configured to generate a differential output in response to (i) a first differential input, (ii) a second differential input and (iii) a first supply. The level shifter circuit comprises a first pull down transistor pair operating with the first supply. The control circuit may be configured to generate the second differential input in response to (i) the first differential input and (ii) a second supply. The control circuit generally comprises a second pull down transistor pair operating with the second supply. The first supply has a higher voltage than the second supply.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: August 26, 2014
    Assignee: LSI Corporation
    Inventors: Pankaj Kumar, Pramod Parameswaran, Makeshwar Kothandaraman
  • Patent number: 8797092
    Abstract: An embodiment of a discharge circuit for evacuating electric charge accumulated in circuit nodes of a charge pump during a discharge phase consequent to a shutdown of the charge pump is proposed. The charge pump is configured to bias each circuit node with a corresponding pump voltage during an operational phase of the charge pump. The discharge circuit includes a generator circuit configured to generate a discharge current during the discharge phase. The discharge circuit further includes means for evacuating the electric charge stored in each circuit node of the charge pump during a corresponding portion of the discharge phase; such means for evacuating include a respective discharge stage for each circuit node of the charge pump. Each discharge stage includes a first discharge circuit branch and a second discharge circuit branch coupled to the corresponding circuit node.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: August 5, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventors: Guido De Sandre, Luca Bettini, Gianni Giacomi
  • Patent number: 8779850
    Abstract: A bootstrap circuit includes an input terminal, an inverting input terminal, an output terminal, an inverting output terminal, a first sub-bootstrap circuit, a second sub-bootstrap circuit, and a charging path providing circuit. The first sub-bootstrap circuit includes a first bootstrap capacitor, a first charging path, a first discharging path, and a first high voltage providing path. The charging path providing circuit includes a third charging path. In response to a high voltage level inputted into the input terminal, the first charging path and the third charging path are turned on, the first bootstrap capacitor is charged to a capacitor voltage, and the first discharging path is turned on to discharge the output terminal. In response to a low voltage level inputted into the input terminal, a first superimposed voltage including the high voltage level and the capacitor voltage is provided to the output terminal.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: July 15, 2014
    Assignee: Orise Technology Co., Ltd.
    Inventor: Che-Wei Wu
  • Patent number: 8754675
    Abstract: In accordance with an embodiment, a circuit for driving a switch includes a driver circuit. The driver circuit includes a first output configured to be coupled to a gate of the JFET, a second output configured to be coupled to a gate of the MOSFET, a first power supply node, and a bias input configured to be coupled to the common node. The switch to be driven includes a JFET coupled to a MOSFET at a common node.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: June 17, 2014
    Assignee: Infineon Technologies AG
    Inventors: Dieter Draxelmayr, Karl Norling
  • Patent number: 8664979
    Abstract: Various exemplary embodiments relate to a tracking system and method. The system includes a transistor switch having a gate node and a source node, a power source circuit connected to the gate node, and a bootstrapping circuit connected to the source node and to the gate node. The power source circuit charges the switch during a first tracking phase, and the bootstrapping circuit charges the switch during a second tracking phase.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: March 4, 2014
    Assignee: NXP B.V.
    Inventors: Konstantinos Doris, Erwin Janssen, Anton Zanikopoulos, Alessandro Murroni
  • Publication number: 20140015503
    Abstract: A boot-strap circuit for a voltage converting device includes a boot-strap capacitor; a charging module, for charging the boot-strap capacitor; and a protection module, for detecting a capacitor voltage of the boot-strap capacitor and adjusting conducting statuses of one of an upper-bridge switch and a lower-bridge switch of the voltage converting device according to the capacitor voltage and a duty cycle signal utilized for controlling conducting statuses of the upper-bridge switch and the lower-bridge switch.
    Type: Application
    Filed: October 25, 2012
    Publication date: January 16, 2014
    Applicant: ANPEC ELECTRONICS CORPORATION
    Inventor: Chieh-Wen Cheng
  • Patent number: 8624662
    Abstract: An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor both encased in a single package. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, a drain electrode of the high-voltage depletion-mode transistor is electrically connected to a drain lead of the single package, a gate electrode of the low-voltage enhancement-mode transistor is electrically connected to a gate lead of the single package, a gate electrode of the high-voltage depletion-mode transistor is electrically connected to an additional lead of the single package, and a source electrode of the low-voltage enhancement-mode transistor is electrically connected to a conductive structural portion of the single package.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: January 7, 2014
    Assignee: Transphorm Inc.
    Inventors: Primit Parikh, James Honea, Carl C. Blake, Jr., Robert Coffie, Yifeng Wu, Umesh Mishra
  • Patent number: 8604862
    Abstract: A bootstrapped switch circuit includes a first switch transistor to receive an input signal and a second switch transistor to provide an output signal. The sources of the switch transistors may be coupled. A voltage source may be coupled to the sources of the switch transistors and at least one of the gates of the switch transistors. The voltage source may generate a control voltage to activate at least one of the switch transistors based on a bias current. A voltage source driver may be coupled to the voltage source to generate the bias current based on a bias voltage. The bias voltage may include a first voltage approximately corresponding to an overdrive voltage of at least one of the switch transistors and a second voltage approximately corresponding to a threshold voltage of the switch transistors.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: December 10, 2013
    Assignee: Analog Devices, Inc.
    Inventors: Christian Steffen Birk, Gerard Mora Puchalt
  • Patent number: 8593211
    Abstract: A half-bridge power circuit comprises a first gallium nitride field effect transistor (GaN FET); a first driver coupled to a gate of the first GaN FET; an anode of a capacitor coupled to an output of the driver and a source of the first GaN FET; a diode having a cathode coupled to the cathode of the capacitor; and a bootstrap capacitor clamp (BCC) controller, including: a field effect transistor (FET) coupled to an anode of the diode, and a comparator coupled to a gate of the FET, the comparator configured to receive as inputs: a) a signal representative of an input voltage (VDRV) applied to the FET; b) a ground; c) a boot signal representative of a voltage at the anode of the capacitor (Boot); and d) a signal representative of a voltage at the source of the first GaN FET (SW).
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: November 26, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Hassan Pooya Forghani-Zadeh, Luis A. Huertas-Sanchez
  • Patent number: 8576156
    Abstract: An auxiliary capacitor line driving circuit (5), provided in a surrounding region located around a display region (R1) in a liquid crystal display panel, generates auxiliary capacitor driving signals, and includes: first and second voltage trunk lines (VCS1, VCS2) which carry two different voltages, respectively; at least one control signal line (VCTRL1, VCTRL2) carrying one control signal; and a plurality of TFTs (T1, T2, T3, T4) each alternately supplying, to the respective auxiliary capacitor lines (CSn, CSn+1, and the like) in a given cycle, the two different voltages supplied to the auxiliary capacitor line driving circuit (5). Therefore, a liquid crystal display device employing multi-picture element drive method can be provided as a liquid crystal display device that achieves narrowing of a picture frame region as a non-display region and an external circuit board.
    Type: Grant
    Filed: November 26, 2010
    Date of Patent: November 5, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masahiko Nakamizo, Akihiro Shohraku
  • Patent number: 8575986
    Abstract: A level shift circuit includes an input port to which an input signal is input, a first signal amplifying unit configured to amplify the input signal input to the input port, a node at the first signal amplifying unit to output the amplified signal, a level shift input port to which a level shift voltage for controlling a DC level of the node is input, a first supply voltage configured to drive the first signal amplifying unit, and a level shift voltage generation circuit configured to generate the first supply voltage and the level shift voltage.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: November 5, 2013
    Assignee: Rohm Co., Ltd.
    Inventor: Hironori Sumitomo
  • Patent number: 8564258
    Abstract: A first pump circuit generates a first voltage for decreasing the distance between primary electrodes. The first voltage is limited to a predetermined limit by a first limiter circuit. A second pump circuit generates a second voltage for keeping the distance between the primary electrodes constant. A third pump circuit generates the second voltage and has a supplying capacity smaller than the first one. The second voltage is limited by second and third limiter circuits. A ripple capacitor is charged up to the second voltage by the second pump circuit and the second limiter circuit within a period of time the first voltage is being generated. When a supplying voltage of the first pump circuit reaches to the first voltage, and a deformation stops, the second voltage is supplied by the third pump circuit and the third limiter circuit instead of the second pump circuit and the second limiter circuit.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: October 22, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Atsushi Suzuki
  • Patent number: 8536928
    Abstract: An integrated circuit (IC) comprises a transistor circuit and a voltage generator circuit. The voltage generator circuit is configured to generate an activation voltage for the transistor circuit using an output voltage at an output of the transistor circuit, and maintain a gate-source voltage (VGS) of the transistor circuit at a substantially constant voltage above the output voltage when a magnitude of the generated activation voltage is less than a device voltage rating of the IC and when the magnitude of the generated activation voltage meets or exceeds the device voltage rating of the IC.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: September 17, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Nickole Gagne, Jouni Mika Kalervo Vuorinen
  • Patent number: 8536808
    Abstract: A modified bootstrap circuit utilized, for example, in a high voltage DC/DC CMOS buck converter to convert a high input voltage (e.g., 24V) to a regulated voltage (e.g., 4V) for use, for example, by an LED driver circuit. The bootstrap circuit utilizes a feedback diode and a PMOS switch to avoid high reverse diode voltages across a low voltage bootstrap diode. A bootstrapped buck converter implements the bootstrap circuit to generate a high gate voltage on a high-side NMOS switch during all operating phases. The PMOS switch is controlled by the NMOS switch's output voltage to pass a system voltage (e.g., 5V) through the bootstrap diode whenever the output voltage drops low (e.g., 0V), and to shut off when the output voltage subsequently rises such that the feedback diode forward biases to pass the output voltage to the anode of the bootstrap diode.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: September 17, 2013
    Assignee: Tower Semiconductor Ltd.
    Inventors: Erez Sarig, Raz Reshef
  • Patent number: 8525574
    Abstract: In one embodiment, a bootstrap switch circuit has (i) a switch device that selectively provides a input signal as an output signal and bootstrap circuitry that provides a relatively high-voltage control signal to the gate of the switch device to turn on the switch device while preventing any over-voltage conditions from being applied to the switch device. The bootstrap circuitry includes a capacitor and a number of transistors configured as either switches or inverters. The circuit has two operating phases: one in which the capacitor gets charged while the switch device is turned off and the other in which the charged capacitor is isolated and used to generate the high-voltage control signal to be a fixed voltage difference above the current voltage level of the input signal applied to the switch device, thereby preventing an over-voltage condition.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: September 3, 2013
    Assignee: LSI Corporation
    Inventor: Abhishek Duggal
  • Patent number: 8502594
    Abstract: A switch circuit is described, where a switch to be controlled is formed of two NMOS transistors having their source terminals connected together and their gate terminals connected together. Their drain terminals are the input and output terminals of the switch. A driver circuit controls a bootstrap circuit that is formed of a latching circuit and a capacitor. When the switch is in an off state, the driver circuit connects the capacitor to a charging voltage source for charging the capacitor to a bootstrap voltage, and applies a non-zero voltage across the latching circuit. When the driver circuit is controlled to turn on the switch, the driver circuit disconnects the capacitor from the charging voltage source, and the latching circuit becomes conductive and effectively connects the capacitor across the gate and source terminals of the switch to turn it on with the bootstrap voltage. The bootstrap voltage across the capacitor maintains the latching circuit in a latched conductive state.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: August 6, 2013
    Assignee: Linear Technology Corporation
    Inventor: Jesper Steensgaard-Madsen
  • Patent number: 8487664
    Abstract: In accordance with an embodiment, a circuit for driving a switch includes a driver circuit. The driver circuit includes a first output configured to be coupled to a gate of the JFET, a second output configured to be coupled to a gate of the MOSFET, a first power supply node, and a bias input configured to be coupled to the common node. The switch to be driven includes a JFET coupled to a MOSFET at a common node.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: July 16, 2013
    Assignee: Infineon Technologies AG
    Inventors: Dieter Draxelmayr, Karl Norling
  • Patent number: 8482341
    Abstract: The invention provides a booster circuit including a first transistor, a second transistor, a first capacitor element, a second capacitor element, a diode, and an inverter, wherein one electrode of the first transistor is maintained at a predetermined potential, the output of the inverter is connected to the gate electrode of the first transistor and one electrode of the second transistor through the second capacitor element, the input of the inverter is connected to the other electrode of the first transistor through the first capacitor element and connected to the gate electrode of the second transistor, and the diode is connected between the other electrode of the first transistor and the other electrode of the second transistor so as to be forwardly biased.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: July 9, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 8310281
    Abstract: In accordance with an embodiment, a method of driving switches includes sensing a control node of a first switch, sensing a control node of a second switch, and driving the control node of the first switch to a first active state after the control node of the second switch transitions to a second active state. The method also includes driving the control node of the second switch to a second inactive state after the control node of the first switch transitions to a first inactive state. Driving the control node of the first switch is based on sensing the control node of the second switch, and driving the control node of the second switch is based on based on sensing the control node of the first switch.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: November 13, 2012
    Assignee: Infineon Technologies AG
    Inventor: Dieter Draxelmayr
  • Patent number: 8294512
    Abstract: A track-and-hold circuit includes a bootstrapped clock generator and a track-and-hold unit. The bootstrapped clock generator receives an input voltage signal and generates a sampling control signal having a voltage level lower than or equal to a level of a power supply voltage by maintaining an initial level of a boost capacitor voltage at a level lower than the level of the power supply voltage. The boost capacitor voltage is a voltage that is charged across a boost capacitor included in the bootstrapped clock generator and the sampling control signal is generated based on a clock signal. The track-and-hold unit samples and holds the input voltage signal in response to the sampling control signal to generate a sampled signal.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: October 23, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jungho Lee, Heung-Bae Lee
  • Patent number: 8278886
    Abstract: A circuit for recovering charge at the gate of an output transistor arranged to drive the output of a switching circuit such as a switching regulator or controller. A substantial portion of the charge for each switching cycle is recovered under a wide range of load conditions for the switching circuit, e.g., no load, partial load, or full load. Also, charge recovery operates effectively with a switching circuit that is arranged to switch in a synchronous or asynchronous manner. Additionally, if the output voltage of a switching circuit is 12 or more volts, the amount of charge that can be saved can be relatively substantial.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: October 2, 2012
    Assignee: National Semiconductor Corporation
    Inventor: David James Megaw
  • Patent number: 8269547
    Abstract: A bootstrap circuit comprises: a first transistor connecting a first power supply with an output node; and a second transistor applying a first input signal to a gate node of the first transistor and having a conductivity type identical to that of the first transistor. A second input signal obtained by inverting a level of the first input signal, delaying the inverted signal, and adding a direct current bias to the delayed signal is inputted to a gate node of the second transistor.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: September 18, 2012
    Assignee: NLT Technologies, Ltd.
    Inventor: Yoshihiro Nonaka
  • Patent number: 8232830
    Abstract: A highly efficient rectifier can readily replace a two-terminal diode. Its conduction losses are reduced from that of the two-terminal diode. Connected between the source and drain of a MOSFET including a parasitic diode are a micro-power converter section for boosting a conduction voltage Vds between the source and drain to a predetermined voltage, and a self-drive control section that operates based on a voltage output from the micro-power converter section. When the source and drain are conductive with each other, the micro-power converter section generates, from the conduction voltage Vds, a power source voltage for the self-drive control section, and the self-drive control section (4) continues drive control of the MOSFET.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: July 31, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Miyuki Takeshita, Akihiko Iwata, Ikuro Suga, Shigeki Harada, Kenichi Kawabata, Takashi Kumagai, Kenji Fujiwara
  • Patent number: 8222948
    Abstract: A bootstrapped switch circuit can include at least one transistor, to receive an input signal and allow the input signal to pass through as an output signal based on a control signal, and a voltage-controlled voltage source, to provide first and second voltages between a gate and a source of the at least one transistor in response to the control signal. The voltage-controlled voltage source can include a differential pair and a current source. A gate of one of the differential pair can receive the control signal and a gate of the other of the differential pair can receive a logical inverse of the control signal. The current source can provide a current to connected sources of the differential pair. The first voltage can turn on the at least one transistor and be produced in response to a first logic state of the control signal resulting in the current of the current source flowing entirely through a first one of the differential pair.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: July 17, 2012
    Assignee: Analog Devices, Inc.
    Inventor: Christian Steffen Birk
  • Patent number: 8217487
    Abstract: Disclosed is a power semiconductor device including a bootstrap circuit. The power semiconductor device includes a high voltage unit that provides a high voltage control signal so that a high voltage is output; a low voltage unit that provides a low voltage control signal so that a ground voltage is output, and is spaced apart from the high voltage unit; a charge enable unit that is electrically connected to the low voltage unit and charges a bootstrap capacitor for supplying power to the high voltage unit when the high voltage is output, when the ground voltage is output; and a high voltage cut-off unit that cuts off the high voltage when the high voltage is output so that the high voltage is not applied to the charge enable unit, and includes a first terminal electrically connected to the charge enable unit and a second terminal electrically connected to the high voltage unit.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: July 10, 2012
    Assignee: Fairchild Korea Semiconductor Ltd.
    Inventors: Yongcheol Choi, Chang-Ki Jeon, Minsuk Kim, Donghwan Kim
  • Patent number: 8207714
    Abstract: A switching regulator integrated circuit (IC) is disclosed that includes a switch circuit that further includes a first switch and a second switch, a mode selector circuit controlled by external circuitry to select between a first mode and a second mode, and a control circuit. In response to a feedback signal from the switch circuit, when the first mode is selected, the control circuit toggles the first switch and the second switch ON and OFF alternately at a fixed first frequency. When a second mode is selected, the control circuit causes the second switch to turn OFF completely and the first switch to switch ON and OFF at a variable second frequency.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: June 26, 2012
    Assignee: Monolithic Power Systems, Inc.
    Inventor: Wei Chen
  • Patent number: 8179191
    Abstract: A conventional circuit requires a booster circuit for generating a voltage higher than an external power supply voltage, thus low power consumption is difficult to be achieved. In addition, a display device incorporating the aforementioned conventional switching element for booster circuit has problems in that the current load is increased and the power supply becomes unstable with a higher output current.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: May 15, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 8138820
    Abstract: A distributed charge pump system uses a delay element and frequency dividers to generate out of phase pump clock signals that drive different charge pumps, to offset peak current clock edges for each charge pump and thereby reduce overall peak power. Clock signal division and phase offset may be extended to multiple levels for further smoothing of the pump clock signal transitions. A dual frequency divider may be used which receives the clock signal and its complement, and generates two divided signals that are 90° out of phase. In an illustrative embodiment the clock generator comprises a variable-frequency clock source, and a voltage regulator senses an output voltage of the charge pumps, generates a reference voltage based on a currently selected frequency of the variable-frequency clock source, and temporarily disables the charge pumps (by turning off local pump clocks) when the output voltage is greater than the reference voltage.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Fadi H. Gebara, Jente B. Kuang, Abraham Mathews
  • Patent number: 8130026
    Abstract: A booster circuit includes a pump circuit having a plurality of charge pump circuits for outputting a boosted voltage to a first output terminal. The booster circuit also includes a clock adjusting circuit that generates, from a first clock signal, a second clock signal for operating the charge pump circuits. A pump controlling circuit outputs the first clock signal for operating the pump circuit. A first comparator outputs a first output signal. A second comparator outputs a second output signal. A third comparator outputs a third output signal. A gradient of the boosted voltage is decreased when the first output signal is output. A frequency of the first clock signal is reduced when the second output signal is output. The third output signal is output when the boosted voltage is higher than a set value of the boosted voltage.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: March 6, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Maejima
  • Patent number: 8115518
    Abstract: An integrated circuit allows for the correction of distortion at an input of a sampling network. The integrated circuit contains a first bootstrap circuit to drive a sampling network transistor and a second bootstrap circuit to separate the back-gate terminal of the transistor from a voltage input by a resistance inserted in series. The presence of the inserted resistance counteracts the effect of the nonlinear back-gate capacitance on the distortion at the input.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: February 14, 2012
    Assignee: Analog Devices, Inc.
    Inventor: Ahmed Mohamed Abdelatty Ali
  • Patent number: 8098089
    Abstract: A voltage booster for generating a boosted voltage, including a charge pump adapted to generate the boosted voltage starting from a supply voltage by a transfer of electric charge controlled by at least one oscillating signal having an oscillation frequency; an oscillator for providing the oscillating signal; and a regulation circuit arranged to receive and perform a comparison of a voltage related to the boosted voltage and a reference voltage, and adapted to provide at least one regulation signal indicative of a result of said comparison, wherein said regulation signal is fed to the oscillator to control said oscillation frequency. The regulation circuit is adapted to cause the at least one regulation signal take one among a plurality of discrete values, depending on the result of the comparison, so that the oscillation frequency of the at least one periodical signal accordingly can take one among a plurality of discrete oscillation frequency values.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: January 17, 2012
    Assignee: STMicroelectronics S.r.l.
    Inventors: Davide Bitonti, Andrea Castaldo, Angela Foschini
  • Patent number: 8076912
    Abstract: A first pump circuit generates a first voltage for decreasing the distance between primary electrodes. The first voltage is limited to a predetermined limit by a first limiter circuit. A second pump circuit generates a second voltage for keeping the distance between the primary electrodes constant. A third pump circuit generates the second voltage and has a supplying capacity smaller than the first one. The second voltage is limited by second and third limiter circuits. A ripple capacitor is charged up to the second voltage by the second pump circuit and the second limiter circuit within a period of time the first voltage is being generated. When a supplying voltage of the first pump circuit reaches to the first voltage, and a deformation stops, the second voltage is supplied by the third pump circuit and the third limiter circuit instead of the second pump circuit and the second limiter circuit.
    Type: Grant
    Filed: September 8, 2008
    Date of Patent: December 13, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Atsushi Suzuki
  • Patent number: 8076966
    Abstract: An analog switch circuit that includes a first field-effect transistor, a source of which is coupled to a first switch terminal, and a drain of which is coupled to a second switch terminal; a first capacitance storing electric charge; a second capacitance storing electric charge; a first switch circuit that couples the first capacitance between a direct current voltage node and a reference potential node; a second switch circuit that couples the first capacitance and the second capacitance in parallel; and a third switch circuit that couples the second capacitance between a gate and the source of the first field-effect transistor.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: December 13, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Minoru Hosoda, Mitsuo Kitamura