Abstract: Integrated buffer circuits include an output driver powered at a first power supply voltage (EVC) and a voltage boosting circuit which drives an input (DOK) of the output driver and is powered at a second power supply voltage (VINTQ) having a magnitude less than a magnitude of the first power supply voltage. An internal power supply voltage generator is provided which generates the second power supply voltage at a level which varies inversely with increases in the first power supply voltage in order to minimize timing skew associated with the output driver. This is achieved by lowering the voltage of the signal applied to the input (DOK) of the output driver to compensate for the output driver being powered at an increased first power supply voltage.

Abstract: A method and apparatus comprising a first circuit configured to generate a first output in response to a first input, a second circuit configured to present a second output in response to a second input, and a third circuit configured to generate a first voltage signal and a second voltage signal in response to the first output and said second output. The first voltage signal may be above the positive supply and the second voltage signal may be below the negative supply.

Abstract: A device for generating a voltage pulse in a low-voltage integrated circuit includes a capacitor and a control circuit. An input signal having negative pulses is received by the device. The input signal has a high level corresponding to a level of a logic supply voltage for the device, and a low level corresponding to zero volts. The control circuit includes a first and a second circuit element. The first circuit element transmits the low level of the input signal to a second terminal of the capacitor and also provides the capacitor a charging path. The second circuit element transmits the low level of the input signal to a first terminal of the capacitor with a predetermined delay so that a negative pulse between the high level and a negative level is provided at the second terminal of the capacitor in response to the input signal.

Abstract: A semiconductor integrated circuit configured of a DRAM or the like has a function of generating a step-up voltage and supplying it to a plurality of semiconductor devices. During the period when a burn-in test is conducted, the input voltage of a precharge portion for precharging a step-up node for outputting the step-up voltage is clamped to a predetermined level by a precharge input voltage clamping unit. The precharge input voltage clamping unit prevents the step-up voltage level across the step-up node from excessively increasing during the burn-in test.

Abstract: A portion of a differential charge pump circuit is partially replicated and is utilized as a replica circuit to define the common-mode voltage VCM of the differential output voltages of the charge pump circuit that drives a voltage controlled oscillator (VCO) in a PLL system application, or a voltage-controlled delay (VCD) circuit in a DLL system application. The replica circuit includes a high gain operational amplifier and at least three MOS transistors electrically coupled to the differential charge pump circuit. The operational amplifier generates the DC output voltage VO which is used to define the common-mode voltage VCM of the charge pump circuit. The three transistors are configured in replica of one-half of the charge pump circuit. The operational amplifier is provided with a bias voltage at the inverting-end input terminal.

Abstract: A circuit for charging a capacitance using an LDMOS integrated transistor functioning as a source follower and controlled, in a manner to emulate a high voltage charging diode of the capacitance. The LDMOS transistor is controlled via a bootstrap capacitor charged by a diode at the supply voltage of the circuit, and by an inverter driven by a logic control circuit as a function of a Low Gate Drive Signal and of a second logic signal which is active during a phase wherein the supply voltage is lower than the minimum switch-on voltage of the integrated circuit. The circuit uses a first zener diode to charge the bootstrap capacitor and the source of the transistor is connected to the supply node through a second zener diode.

Abstract: A switching circuit operable under a low voltage power source includes first and second level shift circuits. The level shift circuits receive a switching control signal and generate an internal switching signal and an inverted internal switching signal. The level shift circuits supply the internal switching signals to switching elements. A switched capacitor filter includes an amplifier and the described switching circuit. The amplifier has amplification inverters connected in series in three stages.

Abstract: In a semiconductor device having a plurality of output circuits such as a semiconductor memory device, a drive signal having a boosted voltage level which is produced from a boosting circuit is applied to a gate of a low-level outputting MOS transistor in the output circuit. As a result, even when a potential at the ground wiring line is floated, a substantial decrease of a potential difference between the ground wiring line and the gate of the low-level outputting MOS transistor can be prevented. Also, a signal having a sufficiently high level can be supplied to a gate of a low-level outputting output MOS transistor. As a consequence, delays in the switching operation of the output MOS transistor can be suppressed, and the output circuit can be operated at high speed.

Abstract: A bootstrap sample and hold circuit accurately acquires and holds values of a high frequency analog input signal, to avoid harmonic distortion of a signal representing the analog input signal in, for example, a pipeline ADC, includes a first sampling MOSFET coupling the analog input signal to a sampling capacitor. A bootstrap circuit includes a bootstrap capacitor. First and second MOSFETs couple the bootstrap capacitor between a first reference voltage and ground in response to pulses of a first clock signal. Third and fourth MOSFETs then couple the bootstrap capacitor between the gate and source of the sampling MOSFET in response to non-overlapping pulses of a second clock signal to apply a constant gate-to-source voltage to the sampling MOSFET, the gate-to-source voltage having a magnitude equal to the difference between a first reference voltage and ground during the pulses of the second clock signal.

Abstract: An active digital voltage regulator circuit stores energy during times when the local power supply voltage is greater than a predefined voltage, e.g., during times when the parasitic inductances supplement the local power supply voltage. The active digital voltage regulator circuit uses the stored energy to supplement the local power supply voltage during times when the local power supply voltage starts to collapse, e.g., during periods when inductive losses are preventing the power supply from maintaining the local power supply voltage. A control circuit within the regulator circuit is a combination of two self-biasing and off-set nulling power supply monitor circuits. Each power supply monitor circuit further includes a differencing, non-overlapped, dual-output amplifier connected to the first and second power supply input lines.

Abstract: Disclosed is a biasing circuit for bringing a power FET to a substantial full enhancement. The biasing circuit includes: (a) a rail power voltage that is coupled to a drain terminal of the power field effect transistor; (b) a load being coupled between an other potential and a source terminal of the power field effect transistor; and (c) a micromachined DC/DC converter that is coupled between a gate terminal of the power field effect transistor and the rail power voltage. The micromachined DC/DC converter is configured to produce an enhanced voltage that is greater than the rail power voltage to the gate terminal of the power field effect transistor to achieve a substantial enhancement of the power field effect transistor.

Abstract: A circuit for providing programmable voltage output levels in a logic device includes a pull-up device for driving an output pad with either a first voltage output level or a second voltage output level. A charge pump generates a pumped voltage. A first clamp regulator, coupled to the charge pump and the pull-up device, receives a first reference signal. The first clamp regulator, in response to the first reference signal, generates a first voltage from which the first voltage output level is derived. A second clamp regulator, coupled to the pull-up device, receives a second reference signal. In response to the second reference signal, the second clamp regulator generates a second voltage from which the second voltage output level is derived. A passgate multiplexer is coupled to the first and second clamp regulators. The passgate multiplexer receives at least one output voltage select signal.

Abstract: A voltage boosting circuit for use in an integrated circuit having at least four driving voltage phases that include first and second voltage phases with amplitudes substantially equal to the supply voltage, and first and second boosted voltage phases. The voltage boosting circuit includes an input that receives the first or second voltage phase, an output that supplies the first or second boosted voltage phase, and a charge node that is coupled to the input. Additionally, a supply voltage precharge circuit precharges the charge node, and an additional transistor is connected between the supply voltage and the charge node. The additional transistor is driven by a voltage with a greater amplitude than the supply voltage so that the charge node is precharged up to the supply voltage and the first or second boosted voltage phase that is output by the voltage boosting circuit reaches an amplitude equal to substantially twice the supply voltage.

Abstract: A circuit for charging a capacitance using an LDMOS integrated transistor functioning as a source follower stage and controlled, in a manner to emulate a high voltage charging diode of the capacitance via a bootstrap capacitor charged by a diode connected to the supply node of the circuit, and by an inverter driven by a logic control circuit as a function of a first Low Gate Drive Signal and of a second logic signal. The second logic signal is active during a phase where the supply voltage is lower than the minimum switch-on voltage of the integrated circuit. The circuit further includes a second inverter functionally referred to the charging node of the bootstrap capacitor and to the voltage of the output node of the inverter. The second inverter has an input coupled to the second logic signal and an output coupled to the gate node of the LDMOS transistor for preventing accidental undue switch-on of the LDMOS transistor.

Abstract: Voltage boosting circuits having improved overvoltage protection circuits therein include a first pumping circuit and a second pumping circuit. The first pumping circuit includes comprises a first charge pump having an output coupled to a boosted voltage signal line and an oscillator for driving the first charge pump. The second pumping circuit comprises a second charge pump having an output coupled to the boosted voltage signal line and an active kicker circuit for driving the second charge pump upon receipt of a control signal during an active mode of operation. This control signal may be an address strobe signal, such as a complementary row address strobe signal (RASB). An overvoltage protection circuit is also provided. This overvoltage protection circuit includes a circuit to detect an overvoltage condition if a potential of the boosted voltage signal line exceeds a first threshold and a circuit to block receipt of the control signal by the active kicker circuit if the overvoltage condition is detected.

Abstract: For use in a boost converter having a boost inductor coupled between an input and an output of the boost converter and an output capacitor coupled between rails of the output, an energy storage circuit for, and method of, extending a holdup time of the boost converter.

Abstract: Aspects for self bootstrapping word-line driver circuitry are provided. In a circuit aspect, a word-line driver circuit for a memory cell in a semiconductor memory includes a signal input means, the signal input means comprising a first plurality of transistors, the first plurality of transistors receiving an input voltage signal higher than a voltage supply signal of the semiconductor memory. The circuit further includes a signal output means, the signal output means comprising a second plurality of transistors coupled to the first plurality of transistors and providing an output drive signal sufficient for the memory cell.

Abstract: One embodiment of an apparatus for generating a boosted voltage to drive a data signal comprises a voltage pump that includes a driver coupled to an input signal for generating the boosted voltage signal from the input signal; a capacitor coupled to the data signal that stores a charge thereof; and an output transistor that delivers an incremental charge to the driver when the drive signal is asserted. Thus, the boosted voltage signal compensates for a change in logic level of the drive signal. In another embodiment, the apparatus also has gates for combining a plurality of data signals into a single disable-on-low signal. The disable-on-low signal is coupled to the output transistor. When all the data signals are at a low logic level, the disable-on-low signal turns off the output transistor, disabling the circuit. As a result, the circuit conserves power by generating the boosted voltage signal only when needed.

Abstract: A voltage boosting circuit for an "H-driver," providing for each "pull-up" switch in the H-driver a switching shunt that charges a capacitor from a supply voltage when the "pull-up" switch is open and couples the capacitor directly to the write head when the "pull-up" switch is closed. The side of the capacitor which is not directly coupled to the write head is coupled to the data signal (or its inverse, in the case of the capacitor for the otherwise identical circuit serving the parallel half of the "H-driver") through a buffer which sets the voltage at the signal level (or its inverse), thereby dumping the charge to the write head and elevating the voltage of the write head significantly above the supply voltage. The identical circuit serving the parallel half of the "H-driver" similarly boosts the negative going transition voltage.

Abstract: The present invention relates to a booster circuit which uses multiple pump circuits to provide high voltages. The pump circuits are provided with an input voltage Vcc and are generally each made up of a diode and a capacitor. A node driving circuit provides driving signals to driving nodes and thereby to the pump circuits. The driving nodes are connected by a charge transfer switch which is selectively activated so as to allow charge that would otherwise be lost to ground to be conserved for inclusion in the final high-output voltage.

Abstract: A bootstrap logic driver circuit operable from a low voltage power supply includes first and second bipolar transistors coupled between positive and negative voltage supplies and having a collector load comprising a first diode structure. A further transistor coupled between the voltage supplies has a collector load comprising a second diode structure. A bootstrap capacitor coupled between the diode structures stores charge when the circuit is in a first condition and is discharged when the circuit is in a second condition to provide an enhanced drive voltage for an output transistor.

Abstract: A voltage booster circuit including an input for receiving a supply voltage, a plurality of stages for producing an output voltage from the supply voltage by the transfer of charges between at least two of the plurality of stages, and circuit for coupling and decoupling stages to vary the number of stages operatively connected together. A method for producing an output voltage from a supply voltage by using a voltage booster circuit, the circuit includes an input for receiving the supply voltage, a plurality of stages, and a selection switch for the selective isolation of the stages or for the selective connection of the stage. The method includes the following steps: starting the circuit; comparing the value of the output voltage with a decrementation threshold; and decreasing the number of stages which are connected if the decrementation threshold is reached by the value of the output voltage.

Abstract: The well regions of pumping units of charge pump circuits are maintained electrically floating. By maintaining the wells electrically floating, reduced impact from the body effect may be obtained. More specifically, integrated circuit charge pump circuits boost a first voltage from a voltage source to a second voltage at an output terminal. The charge pump circuits include a plurality of pumping units in an integrated circuit substrate of first conductivity type, that are serially connected between the voltage source and the output terminal. Each of the pumping units includes a well region of second conductivity type in the integrated circuit substrate of first conductivity type. The well region of second conductivity type is electrically floating.

Abstract: A charge pump circuit comprises an input terminal for receiving an input voltage, an output terminal for providing an output voltage, and a plurality of pump stages connected in series between the input and output terminals and alternately coupled to first and second clock signals having complementary states. Each of the pump stages includes a transistor having a gate terminal, a source terminal, a drain terminal, and a bulk terminal, and a capacitor connected between the gate terminal of the transistor and a corresponding one of the clock signals. Each bulk terminal is biased by the voltage of a previous pump stage driven by the same clock signal, so that each of the corresponding threshold voltages of the transistors is suppressed to a voltage sufficient for generating a higher voltage on a low power supply voltage regardless of body effect.

Abstract: A positive charge pumping circuit which is capable of reducing a sheet resistance and a threshold potential drop. The pumping circuit includes a pumping node, a power supply node, a first diode and at least one pumping stage, The pumping node provides a pumping potential. The supply node provides a power supply potential. An anode of the diode is coupled to the power supply node. The pumping stages are coupled in series between the pumping node and a cathode of the first diode. Each of the pumping stages includes a driving node and a control node, a pumping driving circuit, a transfer control circuit, a charge pumping circuit, and a potential control circuit.

Abstract: A voltage boost circuit having dual voltage outputs and a single input receives a DC voltage from an external source. The input voltage is boosted to provide a constant voltage at the first output at a level higher than the voltage input and to provide a constant voltage output at the second output. A switch is coupled to the output of the inductor for controlling the current flow to the second output.

Abstract: A potential across an output terminal (OUT) is applied to a node N2 through a transistor (Tr66) even when a potential across a node N1 is higher than a power source voltage Vdd due to a bootstrap effect. Accordingly, the potentials between the drain and the source electrodes are not higher than the power source voltage Vdd for both a transistor (Tr62) and the transistor (Tr66). This allows circuit designing without setting the withstand voltage for the transistor over the power source voltage Vdd.

Abstract: A power supply circuit for powering a load circuit comprises a load circuit and includes a converter circuit for inducing current in the load circuit. The converter circuit comprises first and second converter switches serially connected in the foregoing order between a bus conductor at a d.c. voltage and a reference conductor, and connected together at a common node through which the load current flows. The first and second converter switches each comprise respective interconnected control nodes and references connected together at the common node. The voltage between a control node and associated reference node determines the conduction state of the associated switch. A first node is coupled to the bus conductor, and a second node is coupled to the reference conductor. A bridge network is connected between the first and second nodes and has first and second input nodes on which respective first and second input signals are applied.

Abstract: In a high voltage pass gate suitable for use as a block decoder in a flash memory circuit, the boosting of the block decoder's internal nodes is performed using coupling capacitors and boost transistors which are decoupled from the high capacitance pass gate node. The block decoder uses three internal block decoder nodes. Each of the three nodes is held to ground by a corresponding discharge transistor when the block is unselected. Each of the three nodes of a selected block is discharged to a normal supply voltage by a corresponding diode-connected regulation transistor when the high voltage supply is turned off after a programming operation has finished. Each of the three nodes has a separate coupling capacitor associated with it. One of the nodes is connected to the gates of the high voltage pass transistors, this node has high capacitance. The remaining two nodes have relatively small coupling capacitors.

Abstract: Selected transistors in a charge pump circuit have their associated well regions tied to a capacitor electrode. As a result, the body effect in these devices is reduced, and, consequently, the threshold voltage is reduced as well. With a lower threshold voltage, these transistors allow the charge pump to quickly generate a voltage higher than the positive power supply voltage or a negative substrate bias voltage. In addition, the metal-insulator-semiconductor (MIS) capacitors in the charge pump preferably have their source/drain regions tied to an associated well region, thereby shorting the source/drain/well region junction. Thus, parasitic capacitances associated with these MIS capacitors is significantly reduced, further increasing the speed of the charge pump circuit.

Abstract: A circuit for driving a power transistor in pulse mode, particularly adapted for use in a defibrillator. The gate of the power transistor is connected to the drain of a depletion mode transistor so no charge can build up at the gate of the power transistor when the depletion mode transistor is in its normal, conducting state. An electrical path is provided which allows current to flow, in response to a control signal, so that negative charge builds up at the gate of the depletion mode transistor, causing it to switch off (non-conducting), at which point the same current flow begins to charge the gate of the power transistor, switching it on. When the current flow is reversed, the gate of the depletion mode transistor is discharged and it switches back on, causing the gate of the power transistor to also discharge and turn the power transistor off. The various components are selected such that leakage current is less than 1 .mu.a with the resulting power pulse lasting about 25 ms.

Abstract: A first charge pumping circuit including a first capacitor and first and second switches, and a second charge pumping circuit including a second capacitor and third and fourth switches, are operated complementarily. The first capacitor is provided between first and second nodes, and the second capacitor is provided between third and fourth nodes. An NMOS transistor as equalizing means is provided between the first and third nodes. Before the start of supply of charges by the second switch to the second node and injection of charges by the third switch to an output node, the NMOS transistor is turned on, whereby potentials at the first and third nodes are equalized. Accordingly, the charges consumed by the first charge pumping circuit can be recycled by the second charge pumping circuit. Thus, lower power consumption is realized.

Abstract: The invention relates to a voltage multiplier such as a charge pump circuit. The circuit is realized by a plurality of cascade connected voltage gain stages, each stage comprising a first and a second cell each receiving a pair of clock phase signals and comprising a pair of MOS transistors having first and second conduction terminals and a control terminal. These transistors have their first conduction terminals connected together and to a voltage reference; while the control terminals of each transistor are connected to the second conduction terminal of the other transistor of the same cell. Moreover, the second conduction terminal of the first transistor receives a first phase signal via a first coupling capacitor, and the second conduction terminal of the second transistor receives a second phase signals via a first pumping capacitor. Third and fourth cells are provided having the same structure as the first and the second cell.

Abstract: The present invention discloses a negative voltage drive circuit which does not takes an influence from the load capacitor or the power supply voltage drive circuit according to the present invention comprises a cross pumping circuit, a pumping unit block and circuit for supplying VCC or VSS power supply voltages for the pumping unit block.

Abstract: In a preferred embodiment of the present invention, a bidirectional buffer connects a first device, such as a CMOS chip having a first voltage, such as VCC, to a second device having a second voltage, such as VDD, through a terminal pad. The buffer includes a bootstrap capacitor to assist in driving up the terminal pad. In particular, the buffer comprises an output and an input portion. The output portion includes a first driver for driving the terminal pad up to VDD and a second driver for driving the terminal pad down to VSS. The first driver includes a pull-up PMOS transistor and a pull-up NMOS transistor connected in series and the second driver includes a pull-down NMOS transistor. Further, preferably one pair of push-pull bootstrap control transistors are connected in parallel to the gate of the pull-up NMOS transistor for quickly driving up the first driver to a voltage level based on the bootstrap capacitor having a predetermined capacitance.

Abstract: A method of improving the boosted wordline compliance of a memory circuit. A wordline is grounded prior to boosting with a voltage greater than the circuit bias voltage (e.g. vdd) from a boost voltage generator. Grounding the wordline pulls the gate of a pass transistor to the bias voltage minus a threshold voltage and prepares the pass transistor to self-boost upon boosting the wordline. The transconductance of the pass transistor is improved, improving the charge transfer from the boost generator to the wordline, decreasing rise time. In another embodiment, an isolation transistor between the wordline select circuit and the pass transistor is boosted to provide additional pass transistor gate voltage.

Abstract: A charge pump circuit that is capable of generating a voltage that is greater in absolute magnitude than that of the substrate voltage Vsub in circuits where the substrate cannot be pumped to a voltage that is greater in absolute magnitude than Vsub is disclosed. Various innovative circuit techniques are used to implement a, for example, negative charge pump circuit in an N-well CMOS process with all PMOS transistors. The negative charge pump circuit according to the present invention can reliably drive on-chip transmission line termination switches.

Abstract: A ballast circuit for a gas discharge lamp comprises a resonant load circuit incorporating the gas discharge lamp and including a resonant inductance and a resonant capacitance. A d.c.-to-a.c. converter circuit induces an a.c. current in the resonant load circuit. The converter circuit comprises first and second converter switches serially connected in the foregoing order between a bus conductor at a d.c. voltage and a reference conductor, and being connected together at a common node through which the a.c. load current flows. The first and second converter switches comprise respective interconnected control nodes respective reference nodes interconnected together at a common node. The voltage between each control node and associated reference node determining the conduction state of the associated switch. A voltage-limited energy source is connected between first and second nodes.

Abstract: A voltage pump circuit for precharging/pumping a charge to/from a pumping capacitor separately employs a voltage generator for independently supplying a well-bias voltage to a PMOS transfer transistor which transfers a charge of a precharged capacitor to produce reference voltage. The voltage of the voltage generator is applied to a well of the PMOS transfer transistor to body bias the PMOS transfer transistor and, thus, ruggedize its threshold voltage transistor. Here, the well-bias voltage equals or exceeds the reference voltage while being approximately twice a power source voltage.

Abstract: A bootstrap clock generator powered by a variable DC power supply voltage signal generates an approximate boost voltage signal depending on the DC power supply voltage signal level. The clock generator comprises a capacitor having a first and a second terminal and a first switching circuit coupled to the first terminal so as to couple the variable voltage supply signal to the first terminal. A second switching circuit is coupled to the second terminal so as to couple a variable reference voltage signal to the second terminal. A third switching circuit is coupled to the second terminal so as to connect a substantially fixed reference voltage signal to the second terminal. A first and a second control signal activates the switching circuits, such that the first control signal activates the first and second switching circuits, and the second control signal activates the third switching circuit.

Abstract: This invention discloses a 1.5 V bootstrapped pass-transistor-based Manchester-carry-chain circuit suitable for CMOS VLSI using a low supply voltage, in which a bootstrapper circuit is incorporated to enhance the speed performance of the conventional Manchester-carry-chain circuit, which is composed. The bootstrapper circuit contains two P-type metal-oxide-semiconductor (PMOS) transistors, one N-type metal-oxide-semiconductor (NMOS) transistor; a capacitor device, and an inverter. The bootstrapper circuit provides an output having a voltage overshoot, as a carry propagation signal, to the gate of a pass transistor of the Manchester-carry-chain circuit.

Abstract: An augmentation circuit for use in connection with a self-bootstrap type output buffer having an n-channel pullup transistor is disclosed. The augmentation circuit includes a capacitor formed by a second n-channel transistor, connected as a capacitor, and disposed between first and second capacitor terminals. A non-overlapping signal generator is formed from a pair of NOR gates, and an inverter, to generate a pair of control signals CS1, and CS2 wherein when one of the control signals is active, the other control signal is inactive. Four n-channel transistors are provided in a switching matrix. One pair of the four n-channel transistors responds to control signal CS2 to connect the capacitor formed by the n-channel transistor across and between ground, and the output pad. In this switched configuration, a voltage level on the output pad is effectively impressed upon the capacitor, and is stored thereon.

Abstract: A charging circuit for a bootstrap capacitance employing an integrated LDMOS transistor and including a circuital device for preventing the turning on a parasitic transistors of the integrated LDMOS structure during transients that comprises a plurality of directly biased junctions (D1, D2, . . . , Dn) connected in series between a source and a body of the LDMOS transistor structure and at least a current generator, tied to ground potential, coupled between said body and ground, has at least one switch (INT1) between said source and a first junction (D1) of said plurality of junctions and a limiting resistance (R) connected between the body and the current generator (GEN). The switch (INT1) is kept open during a charging phase of the bootstrap capacitance (Cboot) and is closed when the charge voltage (Vboot) of the bootstrap capacitance reaches a preset threshold.

Abstract: A voltage booster circuit including a pull-up capacitor connected to the supply line via a PMOS switching transistor. The other terminal of the pull-up capacitor is supplied with a pull-up voltage switching between a first value determining charging of the capacitor, and a second value higher than the first and determining pull-up of the capacitor. A negative voltage source presents an output connected to the control terminal of a switch transistor, and generates a negative voltage of a value lower than the first pull-up voltage value when charging the capacitor, so as to saturate the switch transistor and charge the capacitor to a voltage close to the supply voltage.

Abstract: A booster circuit uses a source voltage to generate a boosted voltage that is higher than the source voltage. The booster circuit has two capacitors. The two capacitors are alternately charged and discharged in response to a signal applied to an input terminal. The first capacitor is discharged to boost the voltage at the boosting node, whereas the second capacitor is discharged to boost the voltage at an output terminal. Further, the booster circuit includes a control circuit. When the voltage at the input terminal changes from an "H" level to an "L" level, the control circuit supplies a voltage for discharging the first capacitor to the first capacitor after the second capacitor has been brought into a charging state. Since the voltage at the output terminal is reduced by the charging of the second capacitor, a transistor is deactivated in response to the voltage at the output terminal. As a result, the boosting node and the source voltage can be prevented from being coupled by the transistor.

Abstract: In a voltage transferring device connected between a voltage supplying section and a voltage receiving section, the voltage supplying section supplies, in a transferring period, a boost voltage having a boost level to the voltage receiving section. The voltage supplying section has, in a non-transferring period, a non-transferring voltage which has a non-transferring level smaller than the boost level. A transferring field effect transistor has a source electrode connected to the voltage supplying section and a drain electrode connected to the voltage receiving section. A controlling circuit is connected to a substrate electrode of the transferring FET. The voltage controlling circuit supplies, in the transferring period, a high voltage having the boost level to the substrate electrode of the transferring FET. The controlling circuit supplies, in the non-transferring period, a low voltage having the non-transferring level to the substrate electrode of the transferring FET.

Abstract: A charge pump circuit for charging/pumping charge into/out of a charge pumping capacitor. Charge is pumped from the capacitor to turn on one of a pair of MOSFET transistors formed in an integrated circuit for driving a load. The MOSFET transistors are connected at a node in series with one another. The charging capacitor has one end connected at the node and the other connected through a diode to one side of a power supply which is also applied across both transistors. An input signal turns the MOSFETs on and off in a complementary fashion. Each MOSFET has a gate which is discharged to ground when the MOSFET is turned off. A zener diode prevents the capacitor from pumping excess charge to the gate of the MOSFET to which it is connected. Another zener diode prevents damage resulting from excessive voltage external to the integrated circuit.

Abstract: A charge pump circuit for generating an output voltage in response to a clock pulse is disclosed. The charge pump circuit has a switching node connected to a gate of a transistor which is connected between a high voltage output from a high voltage generator and the output voltage, a first path for providing a first coupling voltage to the switching node in response to the clock pulse and a second path for providing a second coupling voltage to the switching node in response to an inverse signal of the clock pulse. Each path includes a capacitor, where a capacitor in the first path has a coupling ratio greater than that of a capacitor of the second path.

Abstract: A clock distribution system for low power operation. Such a clock distribution system includes a global clock generation circuit coupled to generate a global clock signal. This global clock signal is received by a local clock generation circuit which generates a local clock signal. While the system has an operating voltage generally used throughout the system, at least one of the global clock signal and the local clock signal is a small swing clock signal which has a voltage swing substantially less than the operating voltage of the system.

Abstract: Disclosed is a ballast circuit for a gas discharge lamp comprising a resonant load circuit incorporating the gas discharge lamp, a resonant inductance, and a resonant capacitance. A d.c.-to-a.c. converter circuit induces an a.c. current in the load circuit, and comprises first and second converter switches serially connected in the foregoing order between a bus conductor at a d.c. voltage and a reference conductor. The switches are connected together at a common node through which the a.c. load current flows. The switches each have a control node and a reference node, the voltage between such nodes determining the conduction state of the associated switch. The respective control nodes of the switches are interconnected, and the respective reference nodes of the switches are connected together at the common node.