Abstract: Disclosed is a ballast circuit for a gas discharge lamp comprising a resonant load circuit incorporating the gas discharge lamp, a resonant inductance, and a resonant capacitance. A d.c.-to-a.c. converter circuit induces an a.c. current in the load circuit, and comprises first and second converter switches serially connected in the foregoing order between a bus conductor at a d.c. voltage and a reference conductor. The switches are connected together at a common node through which the a.c. load current flows. The switches each have a control node and a reference node, the voltage between such nodes determining the conduction state of the associated switch. The respective control nodes of the switches are interconnected, and the respective reference nodes of the switches are connected together at the common node.

Abstract: A high-efficiency charge pumping circuit includes an oscillator for generating a predetermined cycle of pulse voltage; a first booster capacitor unit for storing an output of the oscillator at a high level, and outputting an output when the output of the oscillator is at a low level; a first clamp unit for maintaining the output of the first booster capacitor unit at a predetermined level; a second clamp unit for maintaining the output of the first booster capacitor unit at a predetermined level; a double-booster circuit for performing a double-boosting of an output signal of the oscillator and then outputting the double-boosted output signal as an output of the double-booster circuit; a second booster capacitor unit for temporarily storing an output voltage of the double-boosted circuit and for outputting the temporarily stored voltage to the second clamp unit; an output transistor for receiving a voltage greater than a predetermined level from the double-booster circuit, and for completely outputting a volt

Abstract: An ultra-low power pumped n-channel transistor output buffer with self-bootstrapping includes an n-channel pullup transistor as the primary pullup device. A gate-to-source capacitance C.sub.gs of the pullup transistor is used to self-bootstrap the input data signal. A pass n-channel transistor is connected between the input data signal, and the gate of the pullup transistor, and is biased on a gate terminal thereof by a charge pump having a voltage magnitude one device threshold higher than the device operating rail V.sub.cc. The pass transistor, so biased, permits the input data signal, which may have a magnitude of V.sub.cc, to charge C.sub.gs. An over-voltage can be developed on the gate of the pullup transistor by the self-bootstrapping effect of C.sub.gs. The pass transistor, in addition, so biased, prevents such over-voltage on the pullup transistors gate from being shorted to V.sub.cc through a driving device.

Abstract: An integrated circuit voltage multiplier 30 in a semiconductor substrate of a first conductivity type. The multiplier includes a diode 22, having a first voltage VDD applied to a first port thereof, the diode being made of: 1) a first well 12 of a second conductivity type formed in the substrate, being connected to a second voltage VB; 2) a second well 14 of the first conductivity type formed in the first well, having an electrical contact point comprising the first port of the diode; and 3) a third well 16 of the second conductivity type formed in the second well, having an electrical contact point comprising a second port of the diode. The multiplier also includes a capacitor C3, having a first contact thereof connected to the second port of the diode and having a third, pulsed voltage PH1 connected to a second contact of the capacitor.

Abstract: In order to provide a voltage booster circuit to be controlled for generating either of a positive high voltage and a negative high voltage for economizing chip size, a voltage booster circuit of the invention, having a charge transfer circuit wherein charges are transfered from a lowest node (N10) to a highest node (N15), comprises switching means (1 and 2) for selecting one of a positive high voltage output mode and a negative high voltage output mode. A positive high voltage (VPP) is output from the highest node (N15) by supplying a power supply voltage (VCC) to the lowest node (N10) in the positive high voltage output mode, and a negative high voltage (VBB) is output from the lowest node (N10) by grounding the highest node (N15) in the negative high voltage output mode.

Abstract: A boosting pulse generating circuit includes a first inverter circuit connected between a first potential node and a second potential node and receives an input signal. A second inverter circuit, connected between the first potential node and the second potential node through a diode connected MOS transistor, is connected to an input terminal and an output terminal. A capacitor is connected between an output terminal of the first inverter circuit and a node interconnecting the diode connected MOS transistor and second inverter circuit. A back gate of the MOS transistor is connected to the gate thereof. This circuit produces good performance even when powered by a low voltage source of operating potential.

Abstract: A circuit and method for generating a fractional multiple of a primary power supply voltage is disclosed. The circuit operates in two phases wherein during a first phase a first capacitor is charged to the primary power supply voltage Vdd, and during a second phase the voltage on the first capacitor is bootstrapped toward twice the power supply voltage. A second capacitor, however, is coupled in parallel to the first capacitor during the second phase to cause charge sharing. The circuit can thus generate a fractional voltage between Vdd and 2 Vdd without the need for any voltage regulator circuitry.

Abstract: A bootstrap circuit includes a transfer transistor and a driver transistor of the same channel type each having two channel terminals and a gate. A first signal terminal receives a first signal and a second signal terminal receives a second signal. One of the channel terminals of the transfer transistor is connected to the gate of the driver transistor. The other of the channel terminals of the transfer transistor is connected to the first signal terminal. One of the channel terminals of the driver transistor is connected to the second signal terminal. The other of the channel terminals of the driver transistor forms an output of the bootstrap circuit. A configuration generates a third signal and has an output connected to the gate of the transfer transistor. The second signal has an edge extending from a first level to a second level and beginning at a bootstrap time.

Abstract: A device for copying a voltage (Ve) comprises a pair of series-connected MOS transistors, their sources forming a common point. The voltage (Ve) to be copied is applied between the gate of the first MOS transistor of the pair and a reference. Means are provided to inject a flux of electrons at a common point. A storage capacitor has a first terminal connected to the drain of the second MOS transistor and a second terminal designed to be biased. Means dictate a potential at the drain of the second MOS transistor and then let it vary so that the flux of electrons is stored in the storage capacitor while at the same time decreasing in the second MOS transistor to the benefit of the first one. The copied voltage Vs is available, after stabilization, between the first terminal of the storage capacitor and the reference. Application in particular to circuits for the reading of charges generated in a photosensitive matrix or photosensitive linear array.

Abstract: A charge-pumping circuit of a semiconductor memory device for generating a voltage higher than an applied supply voltage, including a first MOS transistor having gate and drain terminals through which the supply voltage is received and a source terminal through which an initial voltage is provided to a first node; a first capacitor with predetermined capacitance having one plate connected to the first node and the other plate through which an applied first oscillating signal is received; a third MOS transistor having gate and source terminals connected to the first node to introduce the electric current of the first node into its drain terminal; a second capacitor with capacitance lower than that of the first capacitor, having one plate connected to the second node that is the drain terminal of the third MOS transistor and the other plate through which an applied second oscillating signal is received; and a second MOS transistor having drain and gate terminals connected to the first node and the second node e

Abstract: A ferroelectric memory array includes a word line coupled to a row of ferroelectric memory cells and a word line driver circuit for establishing a full power supply voltage on the word line. A bootstrapping circuit is coupled between the word line and a boost line for receiving a boost signal. The bootstrapping circuit includes a ferroelectric capacitor and coupling circuitry for coupling the ferroelectric capacitor between the boost line and the word line in a first operational mode such that the peak voltage on the word line is greater than the power supply voltage, and for isolating the ferroelectric capacitor from the boost line in a second operational mode.

Abstract: A high voltage pump with an initiation scheme to achieve voltages above VDD. In response to a pulse signal, an initiation voltage is placed on a first node (515) of a voltage pump to initiate pumping action. The initiation voltage is passed through a transistor (545) coupled between a high voltage output node (415) and the first node (515) of the voltage pump. The first node (515) is coupled through a capacitor (510) to an oscillator (405) which charges the first node (515). A high voltage is produced at the high voltage output node (415). The initiation scheme may be applied to one-stage and multiple-stage voltage pumps.

Abstract: A phase generator circuit cyclically produces a first pair of phase signals and a second pair of phase signals, comprising a first circuit to produce a first phase of each pair of phase signals, these first phase signals being non-overlapping and switching over between a voltage 0 and a voltage VCC, and second and third circuits for the production, from the first phase signals, respectively of the second phase of the first pair and the second phase of the second pair of phase signals, these second phase signals being non-overlapping with the first phase signals and switching over between a negative voltage -V and a voltage VCC. The disclosure finds application in the piloting of charge pump type of negative voltage generator circuit.

Abstract: A semiconductor memory device uses three different power supply voltage levels including an internal IVcc, ground Vss and a boosted level Vpp more positive than the internal Vcc. A precharge control circuit in the memory device includes at least one NMOS transistor, at least one PMOS transistor and an output node having voltage values ranging from the IVcc either to Vss or to Vpp. The NMOS transistor acts as a loading transistor to the PMOS transistor and prevents latch-up in the PMOS transistor by maintaining IVcc below Vpp during the initial power set-up period of the memory device.

Abstract: An improved output driver circuit for a semiconductor integrated circuit device is provided. The output driver circuit receives a type select signal (.phi.1, /.phi.1) determined by bonding selection. When a heavy load circuit is connected to an output terminal (DQ), a signal (.phi.1) of low level and a signal (/.phi.1) of high level are provided, whereby transistors (18, 19) are turned on simultaneously in response to a data signal (Mo). When a light load circuit is connected to the terminal (DQ), a signal (.phi.1) of high level and a signal (/.phi.1) of low level are provided, whereby transistors (18, 19) are turned on at a different timing. More specifically, following charging of a light load by a transistor (18) having low mutual conductance, a transistor (19) is turned on. Therefore, noise generation can be flexibly suppressed by bonding selection.

Abstract: A 1.5V full-swing bootstrapped CMOS large capacitive-load driver circuit using two bootstrap capacitors to enhance the switching speed for low-voltage deep-submicron CMOS VLSI. For a supply voltage of 1.5V, the full-swing bootstrapped CMOS driver circuit shows a 2.2 times improvement in switching speed in driving a capacitive load of 10 pF as compared to the conventional CMOS driver circuit. Even for a supply voltage of 1V, this full-swing bootstrapped CMOS large capacitive-load driver circuit is still advantageous.

Abstract: In a booster circuit for use in a semiconductor integrated circuit device that includes: a voltage detection circuit for detecting the boosted voltage with respect to a reference voltage; a pulse oscillator circuit in which oscillation is controlled in accordance with the results of voltage detection; and a charge pump circuit that uses the oscillation pulses to charge capacitors and generates a boosted voltage; a transfer control circuit is inserted between the pulse oscillator circuit and the charge pump circuit that is composed of a transfer gate which is ON/OFF-controlled by the detection output of the voltage detection circuit and a latch circuit. When the boosted voltage is higher than the set value and the detection output changes to low level, this transfer gate is immediately turned OFF, the oscillation output immediately preceding the OFF state is latched in the latch circuit, and oscillation pulses are not transferred to the charge pump circuit.

Abstract: The present invention discloses methods and apparatus for implementing a clocked high voltage switch involving MOS devices. The switching is from a high voltage source typically at 21V to ground. An intermediate voltage source typically at 11V is introduced for reducing the gated breakdown voltage requirement to approximately 10V. This reduced gated breakdown voltage requirement is easily met by special layout methods applied to various transistors in the circuit. The basic layout methods include the terminating of the field implant region near the N+P junction to expose the N+ diffusion over the P substrate to increase the junction breakdown and the gated diode breakdown, and the use of short channel length to reduce the threshold voltage.

Abstract: When input signal IN rises to an "H" level, node N1 attain an "H" level, and output terminal OUT is charged to a level of VCC-V.sub.TH by n channel transistor. Capacitor is charged by the "H" level signal transmitted through inverters, and the charged potential is superimposed on output terminal OUT. When a short pulse is merged with input signal IN, RS flipflop is latched, and node N1 attains an "L" level, thereby discharging the voltage of the output terminal. When the output terminal attains an "L" level, NAND gate is opened and RS flipflop is reset, thereby raising the output terminal again to a boost voltage.

Abstract: A voltage booster circuit includes a driver circuit (117) for generating a 3-state output for driving wordlines via row decoder circuits in an array of flash EEPROM memory cells during read and programming modes of operation. The driver circuit effectively disconnects a large booster capacitor (115) in order to allow a small charge pump (114) to further pump up the wordline voltage during programming. As a result, the booster pump has improved efficiency since there is achieved a significant reduction in power consumption.

Abstract: A boost circuit effects increasing current flow through an inductor and a switch when the switch is closed, and then, when the switch is open, directs the inductor current through a diode to charge a storage capacitor at the output. A logic circuit operates the switch. The switch is controlled on by sensing low current flow in the capacitor and off by sensing high current flow in the switch, so that inductor current is continuous.

Abstract: A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2V.sub.dd. Transistors in a boosting circuit are fully switched, eliminating the reduction of the boosting voltage by V.sub.tn as in the prior art. The boosting capacitors are charged by V.sub.dd, thus eliminating drift tracking problems associated with clock boosting sources and V.sub.dd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.

Abstract: A semiconductor integrated circuit comprises a NAND gate which constitutes a previous stage circuit, a reset circuit, a charging circuit, and a capacitor for generating a boost potential. A signal of a node A expressing data and a signal of a node B expressing permission of outputting data are not only input to the NAND gate, but also to the reset circuit, and the output of the reset circuit is not only input to the charging circuit but also to the NAND gate; therefore, the previous stage circuit and the reset circuit are interlinked with the output signals. In the result, even in a case where noise is generated in the node A, it is possible to obtain a sufficient boost potential generated in the capacitor.

Abstract: A high side monolithic switching circuit integrated into a silicon chip is described in which the charge pump is connected to the ground terminal by a constant current circuit and floats relative to the ground terminal to reduce noise generation. The charge pump is connected to a V.sub.CC terminal by an auxiliary power MOSFET having its gate connected to the charge pump output circuit. The conventional charge pump diodes are implemented as MOSFET devices which can be easily integrated into the common monolithic chip. A clamping circuit across the charge pump permits the use of a low voltage, small area capacitor for a high voltage device.

Abstract: In a dynamic random access memory (DRAM), first and second output transistors form an NMOS-type tristate output buffer. Interposed between a gate electrode of the first output transistor and a data input/output terminal (DQ terminal) is an auxiliary transistor of which gate electrode is grounded and of which threshold voltage is lower than that of the first output transistor. Further interposed between the DQ terminal and a gate electrode of the second output transistor is another auxiliary transistor of which gate electrode is grounded and of which threshold voltage is lower than that of the second output transistor. Both auxiliary transistors lower gate voltages of both output transistors down to a negative voltage level such that both output transistors are maintained as cut off when a negative voltage is externally applied to the DQ terminal at the time of high impedance.

Abstract: A voltage stepup circuit having a plurality of setup circuit units connected in stages between an input voltage node and a stepup voltage node. Each circuit unit comprises at least two first and second MOS transistor T1 and T2. Each of first stepup capacitors is connected between a first clock signal supply node and a first connection node at which the drain and gate of a corresponding one of odd-numbered MOS transistors, of a plurality of MOS transistors connected in series through the plurality of stepup circuit units, are connected together. Each of second stepup capacitors is connected between a second connection node at which the drain and gate of a corresponding one of even-numbered MOS transistors of the plurality of MOS transistors connected together and a second clock signal supply node for supplying said second connection node with a second clock signal whose pulse width does not overlap in time with that of the first clock signal.

Abstract: A high side monolithic switching circuit integrated into a silicon chip is described in which the charge pump is connected to the ground terminal by a constant current circuit and floats relative to the ground terminal to reduce noise generation. The charge pump is connected to a V.sub.cc terminal by an auxiliary power MOSFET having its gate connected to the charge pump output circuit. The conventional charge pump diodes are implemented as MOSFET devices which can be easily integrated into the common monolithic chip. A clamping circuit across the charge pump permits the use of a low voltage, small area capacitor for a high voltage device.

Abstract: A semiconductor device includes a boost circuit and a boost control circuit, wherein the boost control circuit comprises a first transistor connected to a load for outputting a boost voltage supplied thereto from a boost circuit to the load, a second transistor connected to the first transistor and further to the load, the second transistor being biased to turn on permanently, and a third transistor connected to the load via the second transistor, wherein the second transistor has a conductance exceeding a conductance of the third transistor.

Abstract: A semiconductor device includes an increase voltage generation circuit generating an increased voltage having a higher potential than a high potential of a power-supply voltage externally supplied. In the device, an increased voltage stabilizing capacitor is connected between the increased voltage and the high potential of the power-supply voltage, and stabilizes the increased voltage.

Abstract: An improved charge pump circuit prevents excessive current leakage. A first MOS transistor has a drain terminal to receive an external voltage and a gate terminal which receives a word line voltage. The first MOS transistor drops the word line voltage by a threshold voltage and transfers the dropped voltage to a source terminal thereof. A capacitor generates a desired voltage for each rising edge of clock pulses applied thereto, and a second MOS transistor has a gate terminal receiving the word line voltage and a drain terminal receiving the voltage from the capacitor. The second MOS transistor transfers the voltage from the capacitor through a source terminal thereof with substantially no voltage drop. A third MOS transistor has a gate terminal connected to the source terminal of the first MOS transistor and a drain terminal connected in common to the source terminals of the first and second MOS transistors.

Abstract: A booster power generating circuit according to the present invention comprises first to fourth booster circuits for supplying first to fourth booster potentials to first to fourth nodes in response to first to fourth pulse signals, a first precharge circuit for precharging the first node when controlled by the fourth booster potential from the fourth node, a second precharge circuit for precharging the third node when controlled by the second booster potential from the second node and a first output circuit for outputting the first booster potential of the first node to an output node, whereby a given booster potential can be output since there is no voltage drop of the boosted potential of the second and fourth nodes, there is obtained high potential between the first and third precharge circuits and the precharging speed of the first and third node is not slowed.

Abstract: A DRAM operable in a precharge cycle and an activation cycle, includes word lines, bit lines in which a first bit line and a second bit line are included, memory cells located between the first bit line and the second bit line, a first node and a second node through which data in the memory cell is transferred, a transfer gate to connect the first bit line to the first node and the second bit line to the second node, a sense amplifier located between the first node and the second node, an equalizer for equalizing the first node and the second node located between the first node and the second node, a voltage booster for boosting the control signal for the transfer gate and the equalizer. In the DRAM, the control signals for the transmisiion gate and the equalizer are set at V.sub.CC during the precharge cycle, and boosted above V.sub.CC in the activation cycle after the precharge cycle, and the control signal for the transfer gate is changed to V.sub.

Abstract: An improved output driver circuit for a semiconductor integrated circuit device is provided. The output driver circuit receives a type select signal (.phi.1, /.phi.1) determined by bonding selection. When a heavy load circuit is connected to an output terminal (DQ), a signal (.phi.1) of low level and a signal (/.phi.1) of high level are provided, whereby transistors (18, 19) are turned on simultaneously in response to a data signal (Mo). When a light load circuit is connected to the terminal (DQ), a signal (.phi.1) of high level and a signal (/.phi.1) of low level are provided, whereby transistors (18, 19) are turned on at a different timing. More specifically, following charging of a light load by a transistor (18) having low mutual conductance, a transistor (19) is turned on. Therefore, noise generation can be flexibly suppressed by bonding selection.

Abstract: A bootstrap circuit comprising a capacitive device connected between an input line and an output line to boost a signal from the input line, a first voltage supply path being selectively driven in response to a voltage on the output line to transfer or block a supply voltage from a supply voltage source to the output line, a second voltage supply path connected in parallel to the first voltage supply path to transfer or block the supply voltage from the supply voltage source to the output line, and a controller for controlling the second voltage supply path in response to the signal from the input line. According to the present invention, the bootstrap circuit enhances a response speed of an output signal with respect to an input signal. Therefore, the bootstrap circuit can boost the input signal stably and accurately regardless of an impulse noise component.

Abstract: A level determining circuit performs level determination of a potential of a boosted potential node. A determination control circuit is provided for controlling a level determination timing of the level determining circuit. The determination control circuit supplies a control pulse signal of a long cycle to the level determining circuit when a charge pump is not operating, and supplies the control pulse signal of a short cycle to the level determining circuit when the charge pump is operating. The level determining circuit performs the level determination in accordance with a timing defined by the control pulse signal supplied from the determination control circuit. In response to the result of determination, the charge pump is driven. In this manner, a power consumption of a semiconductor memory device can be reduced, and overshoot of a boosted potential of the semiconductor memory device can be prevented.

Abstract: A booster circuit device comprises: a liquid crystal drive circuit (14) whose dissipated current changes; a timing circuit (11) for outputting a select signal according to the dissipated current of the liquid crystal drive circuit; a drive signal select circuit (12) for selecting and outputting any one of at least two drive signals CLK of different frequencies on the basis of the select signal outputted by the timing circuit (11); and a booster circuit (13) for supplying a supply voltage to the liquid crystal drive circuit (14) on the basis of the drive signal CLK outputted by the drive signal select circuit (12). Since any of the drive signals CLK of different frequencies can be selected and applied to the booster circuit (13) according to the dissipated current of the liquid crystal drive circuit (14), it is possible to reduce the current dissipation of the booster circuit, that is the current dissipation of the whole booster circuit device can be reduced markedly.

Abstract: A semiconductor device comprises: a signal of high voltage not less than the power voltage; a first transistor for transmitting the high voltage signal; a second transistor for electrically charging and discharging the gate potential of the first transistor; and a circuit for generating a pulse signal of which "H" level is a voltage higher than the power voltage by the threshold voltage of the second transistor. The pulse signal generating circuit is connected to the gate electrode of the second transistor. This cancels the drop of a voltage corresponding to the threshold voltage generated at the time when the electric charge is transferred to the gate electrode of the first transistor. Accordingly, even though the power voltage is low, a high voltage signal can be transferred through the first transistor and the word line potential can be boosted to a voltage not less than the power voltage.

Abstract: An improved bootstrap circuit comprising a booster for boosting a binary signal and outputting the boosted binary signal through its output terminal, a voltage detector for detecting a variation of a supply voltage from a supply voltage source, and an active load for adjusting an output load amount of the booster under control of the voltage detector. According to the present invention, the binary signal is boosted to a voltage level which is stable regardless of the variation of the supply voltage.

Abstract: A supply voltage detect circuit is described which generates a control signal indicating the status of VCC to be at 5.0 or 3.3 volts. This control signal is used to generate analog reference signals used by A/D and/or D/A circuitry in an audio processing integrated circuit and by other circuitry to control clock frequencies or current drive.

Abstract: A boost voltage generating circuit includes a boost voltage producing circuit having a first and a second capacitor receiving a first and a second control signal, respectively, a third smoothing capacitor connected at an output terminal, and a first, a second, a third, and a fourth transistor. A boost output voltage is derived through the third and fourth transistors. The boost voltage producing circuit further includes a fourth capacitor connected between the first capacitor and the gate of the third transistor; a fifth capacitor connected between the second capacitor and the gate of the fourth transistor; a fifth transistor having one of a source and a drain connected to the first capacitor with the other thereof connected to the gate of the third transistor and a gate connected to the second capacitor; and a sixth transistor having one of a source and a drain connected to the second capacitor with the other thereof connected to the gate of the fourth transistor and a gate connected to the first capacitor.

Abstract: A bootstrap circuit particularly suitable for low voltage applications and use with semiconductor memories is disclosed.

Abstract: A bootstrap circuit comprising an inverter for inverting an input signal from an input node, a delay stage for delaying the input signal from the input node for a predetermined time period, a first capacitor connected between an output terminal of the inverter and a junction node, a first NMOS transistor for transferring the input signal delayed by the delay stage to the junction node, the first NMOS transistor having a drain connected to an output terminal of the delay stage, a source connected to the junction node and a gate connected to a supply voltage source, a second capacitor connected between an output node and a ground voltage source, and a second NMOS transistor for transferring the input signal inverted by the inverter to the second capacitor connected to the output node in response to a signal charged on the first capacitor. According to the present invention, the bootstrap circuit bootstraps the input signal to a high voltage level at a high speed.

Abstract: A booster power generating circuit according to the present invention comprises first to fourth booster circuits for supplying first to fourth booster potentials to first to fourth nodes in response to first to fourth pulse signals, a first precharge circuit for precharging the first node when controlled by the fourth booster potential from the fourth node, a second precharge circuit for precharging the third node when controlled by the second booster potential from the second node and a first output circuit for outputting the first booster potential of the first node to an output node, whereby a given booster potential can be output since there is no voltage drop of the boosted potential of the second and fourth nodes, there is obtained high potential between the first and third precharge circuits and the precharging speed of the first and third node is not slowed.

Abstract: A constant impedance sampling switch suitable for a high-frequency analog-to-digital converter, presents a substantially constant impedance to the input signal regardless of the instantaneous level of the input signal. The exemplary sampling switch employs a single metal oxide semiconductor (MOS) transistor to selectively couple the input signal to a sampling circuit. The gate signal for this transistor is generated by circuitry which is disconnected from the gate of the transistor while the transistor is in an non-conductive state. During a sampling interval, the gate signal is boot-strapped by the instantaneous potential of the input signal to render the transistor conductive. Accordingly, the potential difference between the signal being sampled and the gate potential of the transistor remains substantially constant over a relatively wide range of amplitudes for the analog input signal.

Abstract: An integrator includes a capacitor and a bootstrap circuit for detecting any leaking charge from the capacitor and replacing it. The integrator also includes a charge injection circuit for adjusting the charge applied to the capacitor in response to a digital control input to the charge injection circuit. The bootstrap circuit has two transistors to sense leaking charge, and two further transistors forming a differential pair. The bootstrap circuit uses positive feedback and unity gain to replenish the lost charge.

Abstract: The output circuit according to this invention includes a first transistor (output transistor) provided between a first power terminal and an output terminal and receiving a first input signal into its gate via a voltage boosting circuit, a second transistor provided between a second power terminal and the output terminal and receiving a second input signal into its gate, a third and a fourth transistors connected in series between the gate of the first transistor and the output terminal with their respective gates connected to the second power terminal, and a fifth transistor provided between the first power terminal and the node of the third and fourth transistors with its gate connected to the gate of the output transistor.

Abstract: A dynamic random access memory in which data are successively read out responsive to a read command signal is provided with a boosting circuit device. The boosting circuit device has a pumping circuit operable with a first electric power source at a first voltage and responsive to a control clock signal for producing a second electric power at a second voltage boosted higher than the first voltage of the first electric power. A one-shot pulse generator is provided for generating a single pulse from which a pre-pumping pulse is produced to be included in the control clock signal. Thus, the control clock signal contains a pre-pumping pulse and a plurality of clock pulses following the pre-pumping pulse, so that the second voltage of the second electric power has been boosted higher than the first voltage of the first electric power by the pre-pumping pulse in advance of a successive readout of data.

Abstract: A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2V.sub.dd. Transistors in a boosting circuit are fully switched, eliminating the reduction of the boosting voltage by V.sub.tn as in the prior art. The boosting capacitors are charged by V.sub.dd, thus eliminating draft tracking problems associated with clock boosting sources and V.sub.dd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.

Abstract: The circuit comprises a tank capacitance and a charge circuit supplied with the same voltage as the bridge and comprising an inductance and a control transistor. There is also provided a control circuit, which comprises an oscillator controlling the periodic switching of control transistor and a comparator which controls the momentary clamping of control transistor in the condition wherein the charge circuit is interrupted when the difference between the voltage across capacitance and the power supply voltage exceeds a present maximum value and the unclamping of the same transistor when such difference falls below a preset minimum value. A further comparator similarly clamps control transistor if there is an excess current in the transistor itself.

Abstract: This device for generating a reference voltage for a capacitive bootstrap circuit of an output stage can be easily integrated. The output stage comprises a driving block, a capacitive bootstrap circuit and a reference voltage generating block generating a floating reference voltage which is referred to the output voltage signal and switches in accordance thereto.