Abstract: A system may include a processor configured to: receive ambient data from an environment; calculate an average amplitude of the ambient data as a measure of a noise floor; receive a signal of interest found by the signal exceeding a noise riding threshold, the noise riding floor being an upward offset from the noise floor; calculate a running average for amplitude and frequency of the signal of interest; calculate a running variance for the amplitude and the frequency of the signal of interest; use the running average and the running variance to provide an adjustment to limits for modulation detection; use an offset from the noise riding threshold to provide a signal qualification minimum amplitude; and qualify the signal of interest based at least on the signal qualification minimum amplitude.

Abstract: A touch screen, an electronic device, and a wireless charging method are provided. The touch screen includes: a substrate adapted to carry a touch sensor circuit, where the touch sensor circuit includes a first touch sensor circuit and a second touch sensor circuit; and an equivalent switch arranged between the first touch sensor circuit and the second touch sensor circuit, where the first touch sensor circuit and the second touch sensor circuit form the touch sensor circuit in a case that the equivalent switch is off; and the first touch sensor circuit and the second touch sensor circuit form an equivalent coil and two ends of the equivalent coil are connected to a rechargeable power supply to generate an induced current for charging the rechargeable power supply, in a case that the equivalent switch is on.

Abstract: A system and method of color data compression may perform variations of MRC compression including taking into consideration means and/or variances within k×k cells of an image, background texture, background smoothed color, and gradient components for determination of which parts of an image belong to the background and foreground MRC layers, for calculating thresholds values for such determinations, and determining correctness of determined thresholds and polarity, and may determine the background and foreground layer colors based on the variances, the gradient components, and neighboring pixels of non-color-assigned pixels of the background and foreground layers.

Abstract: A peak sample circuit for AC voltage, including: a rectifier coupled to receive an AC voltage and to rectify the AC voltage to generate a rectified signal; a delay circuit coupled to receive the rectified signal and to delay the rectified signal to generate a delayed rectified signal; a comparison circuit coupled to receive the delayed rectified signal and to generate a square signal based on the comparison of the rectified signal and the delayed rectified signal; and a sample output circuit coupled to receive the rectified signal, wherein the sample output circuit samples the rectified signal under the control of the square signal and provides a peak sample signal representative of the peak value of the AC voltage.

Abstract: A signal detector includes a summation unit connected to offset first and second input signals representing a differential input signal into two offset pairs of first and second signals. The signal detector also includes a detection unit connected to select the first signal from one of the offset pairs of first and second signals and the second signal from the other of the offset pairs in an overlap portion of the first and second signals to form a complementary pair of overlap signals and provide a differentially peak-detected output signal from the complementary pair of overlap signals. Additionally, the signal detector includes a comparator connected to provide a detection output signal corresponding to the differentially peak-detected output signal and a reference signal. A method of operating a signal detector is also included.

Abstract: A serial data transmission system, includes a transmitting terminal for transmitting a data, a receiving terminal for receiving the data transmitted by the transmitting terminal, a first connecting capacitor connected between the transmitting terminal and the receiving terminal, and a second connecting capacitor connected between the transmitting terminal and the receiving terminal, wherein the transmitting terminal comprises a transmitting terminal driver unit and an amplitude detection unit connected with the transmitting terminal driver unit, the transmitting terminal driver unit outputs a pair of differential signals, the amplitude detection unit detects an amplitude variation of the differential signals output by the transmitting terminal driver unit, and outputs an indication signal indicating whether the transmitting terminal and the receiving terminal are properly connected with each other. A serial data transmission method is further provided.

Abstract: This transmission input circuit is provided with an adjustment processing section which turns ON a switch at an empty timing where transmission current from a slave device is not flowing, to allow a reference current to flow from a constant current circuit to a current detection resistor, generates in the current detection resistor a target adjustment voltage, in which a threshold voltage corresponding to the reference current is added to a load current detection voltage corresponding to the load current, and adjusts a digital value so that a reference voltage output from a digital variable resistor matches with the target adjustment voltage.

Abstract: A transmission input circuit of the present invention is provided with: a current detection resistor which receives an input of a line current flowing through a transmission line and generates a line current detection voltage; a constant current circuit which generates a predetermined reference current; a first switch which performs a switching operation at an empty timing where a transmission current is not flowing, to thereby allow the reference current to flow from the constant current circuit to the current detection resistor, and generate a reference voltage, in which a threshold voltage corresponding to the reference current is added to a load current detection voltage corresponding to the load current; a capacitor which is connected to the current detection resistor via the first switch; a second switch which performs a switching operation in synchronization with the first switch to thereby sample-hold the reference voltage generated by the current detection resistor in the capacitor; and a comparator

Abstract: A high linear fast peak detector having a variable bias current and/or a variable bias voltage is described. In an exemplary design, the peak detector includes a transistor, a variable current source, a capacitor, and a feedback circuit. The transistor receives the input signal and provides a source current. The variable current source receives the input signal, provides high bias current when the input signal is low, and provides low bias current when the input signal is high. The capacitor is charged by the source current when the input signal is high and is discharged by the high bias current when the input signal is low. The feedback circuit receives a detected signal from the capacitor and provides higher bias voltage for the transistor when the input signal is high, which results in higher source current from the transistor.

Abstract: In an embodiment a semiconductor device correlates a received signal with a known pattern. A correlation output is used as a basis for forming a confidence reference level. The confidence reference level and the correlation output are compared to identify a peak in the received signal indicating that a present signal state of the received signal contains the known pattern.

Abstract: A comparator circuit according to an embodiment of the present invention includes a comparator configured to compare an input signal voltage with a reference voltage obtained by smoothing the input signal by use of a resistor and a capacitor, and output a result of the comparison, a discharge circuit configured to compare a first addition signal which is obtained by adding a positive first voltage to the input signal voltage, with the reference voltage, and discharge the capacitor when the first addition signal is lower than the reference voltage, and a charge circuit configured to compare a second addition signal which is obtained by adding a negative second voltage to the input signal voltage, with the reference voltage, and charge the capacitor when the second addition signal is higher than the reference voltage.

Abstract: A power detection system is disclosed that includes a detector circuit and a comparator circuit. The detector circuit includes a first transistor, a second transistor that is not identical to the first transistor, and a third transistor that is substantially identical to the first transistor. Each of the transistors is commonly coupled to a current source and is coupled to a differential input voltage. The comparator circuit is for providing an output that is representative of whether the input voltage is above or below a threshold voltage responsive to a difference between the first transistor and the second transistor.

Abstract: Circuitry and methodology for tracking the maximum power point (MPP) of a solar panel is disclosed. The voltage and current generated by the solar panel are monitored and used to generate a pulse signal for charging a capacitor. The changes in the voltage and current generated by the solar panel are also monitored, and that information is used to generate a pulse signal for discharging the capacitor. The charging and the discharging pulse signals are used to charge and discharge the capacitor. A reference signal indicative of the charge level of the capacitor is generated. As the current and voltage generated by the solar panel approach the maximum power point (MPP), the frequency of the discharging pulse signal becomes progressively higher, so that the capacitor charging occurs in progressively smaller increments. When the MPP is reached, the reference signal level becomes steady because the charge level of the capacitor becomes steady.

Abstract: A peak detect-and-hold circuit and method thereof using ramp sampling technique includes utilizing two sampling signals of different slopes to sample an input voltage for respective tracking voltages; comparing the held tracking voltage sampled with the sampling signal of a smaller slope and the input voltage to determine whether the input voltage is rising or falling, and if the input voltage starts falling, the held tracking voltage sampled with the sampling signal of a larger slope is taken as the peak. The peak detect-and-hold circuit using ramp sampling technique controls respective tracking voltages by comparing the input voltage with the sampling signals rather than the feedback tracking voltage. Also, it uses the input voltage directly rather than an operational transconductance amplifier to charge holding capacitors for the tracking voltages. Therefore, the errors of peak detecting and holding, namely the pedestal voltage, overshoot voltage and voltage droop are reduced.

Abstract: The invention relates to a pixel cell (100; pixel), comprising an output (102), a photosensor (110; sensor), which is configured to generate a first measuring current (IDPh1) in a first measurement cycle (?c) and a second measuring current (IDPh2) in a second measurement cycle (?c) as a function of radiation, an output node (104), a power storage device (120; SI-Mem), which is configured so that in a first operating mode a current (IM1) can be injected by the power storage device (120) as a function of the first measuring current (IDPh1), and so that in a second operating mode the power storage device (120) is configured to hold the injected current (IM1) so that the injected current can be detected at the output node (104), and a switching unit (130; IO), which is configured to form a difference between the injected current (IM1) and the second measuring current (IDPh2) at the output node in a reading cycle and couple the output node (104) to the output (102).

Abstract: A peak detector capable of rapidly detecting a peak value of a signal is provided. The peak detector includes first and second operational amplifiers and an auxiliary current source to detect two rail to rail signals. The first operational amplifier outputs a detection signal by buffering a first rail to rail input signal. The second operational amplifier outputs a control signal in response to a second rail to rail input signal and the detection signal. The auxiliary current source includes a terminal connected to an output terminal of the first operational amplifier and the other terminal connected to the first or second source voltage. The auxiliary current source operates in response to the control signal. The auxiliary current source supplies a current from the first source voltage to the output terminal in response to the control signal or supplies a path for discharging a current from the output terminal to the second source voltage.

Abstract: An envelope detecting circuit is provided. The envelope detecting circuit comprises a source degeneration circuit that amplifies an input differential signal, a differential gain stage that supplies a voltage proportional to the amplified signal, a potential hold circuit that holds the voltage supplied from the gain stage, a comparator circuit that compares the voltage held by the potential holding circuit with a reference potential to output a detect signal, and envelope level adjustment and selection unit that responds to the detect signal and outputs a control signal to the source degeneration circuit.

Abstract: Disclosed herein is a voltage detection circuit including: a voltage detection section; a first voltage determination section; and a second voltage determination section.

Abstract: A comparison circuit includes a comparator into a first input terminal of which an input signal is input, and into a second input terminal of which a reference voltage for comparison is input, a controller which monitors an output signal of the comparator, and a voltage generation circuit into which a threshold voltage control signal from the controller is input, wherein the voltage generation circuit, when the voltage level of the output signal of the comparator is a first level, outputs as the reference voltage a first threshold voltage which is one of a high potential side threshold voltage and a low potential side threshold voltage which define a hysteresis width, and when the voltage level of the output signal of the comparator is a second level, outputs as the reference voltage a second threshold voltage which is the other one of the high potential side threshold voltage and low potential side threshold voltage.

Abstract: Aspects of the present invention include a method, apparatus and device for generating a power on reset (POR) signal in relation to the crossing point of two currents wherein at least one current is a quadratic function and the other is an exponential function, where each has a mathematical correlation to a function of a predetermined power supply voltage.

Abstract: A method for adapting threshold values in an electronic signal processing device, involving a plurality of different threshold values being calculated and being compared with processing variables calculated in the signal processing device, involves calculation of a common correction value which is valid for the various threshold values. The threshold values are then set on the basis of the common correction value.

Abstract: A charge pump for a DC-DC converter includes an input terminal receiving an input voltage, an output terminal outputting an output voltage, a plurality of charge pumping stages connected in series between the input terminal and the output terminal, and a voltage level shifter shifting voltage levels of first and second gate clock signals so that received first and second gate clock signals have a predetermined amplitude. Therefore, the charge pump can increase power efficiency by maximizing a magnitude of VGS. A DC-DC converter using the charge pump can also be applied to a portable device, for minimizing power consumption, and a method for improving power efficiency of the DC-DC converter is provided.

Abstract: A QP detection unit includes digital circuit elements. There is provided a digital QP detector which detects an electric power signal Vi, which is an input signal, and outputs a detection signal Vo. The digital QP detector includes a register which records input digital data, a first multiplier which multiplies the digital data recorded in the register by a first coefficient, a second multiplier which multiplies the digital data recorded in the register by a second coefficient, an adder which adds the electric power signal Vi and the output from the first multiplier to each other, a comparator which compares the level of the electric power signal Vi and the level of the detection signal Vo, and a first switch which switches the digital data to be fed to the register between the output from the adder (Vi>Vo) and the output from the second multiplier (Vi<Vo) based on a comparison result of the comparator.

Abstract: A comparator circuit according to an embodiment of the present invention includes a comparator configured to compare an input signal voltage with a reference voltage obtained by smoothing the input signal by use of a resistor and a capacitor, and output a result of the comparison, a discharge circuit configured to compare a first addition signal which is obtained by adding a positive first voltage to the input signal voltage, with the reference voltage, and discharge the capacitor when the first addition signal is lower than the reference voltage, and a charge circuit configured to compare a second addition signal which is obtained by adding a negative second voltage to the input signal voltage, with the reference voltage, and charge the capacitor when the second addition signal is higher than the reference voltage.

Abstract: Precision amplitude detection circuitry without pattern dependencies is provided that includes rectifier circuitry to output a rectified voltage signal and delay circuitry to send one or more delayed or phase-shifted versions of a differential signal input to the rectifier circuitry. The delayed versions of the differential signal input may be delayed in order to reduce or eliminate the dips in the input seen by the rectifier. This may help correct for low rectified voltage levels. The signal amplitude detection circuitry of the present invention may be incorporated on the input pin of any programmable logic resource and may be included in communication circuitry of a PLD. The precision amplitude detection circuitry may operate in the Gbps (gigabit per second) range.

Abstract: A delayed peak detector detects a peak level of an input signal IN at timing lagged behind a peak detector, and a peak difference detector detects a peak difference PLD between a delayed peak level DPL and a peak level PL. A reset portion outputs a reset signal BRS for a bottom detector when a level difference between the peak level PL and a bottom level BL exceeds a predetermined value comparable with the amplitude of the input signal IN and the peak difference PLD exceeds an allowable peak difference PLM. It is thus possible to replace the bottom level BL outputted from the bottom detector with a bottom level based on a latest input signal IN.

Abstract: An electronic signal level detection system and method are provided. The method receives an analog input signal having a variable voltage and compares the input signal voltage to a threshold. A detection signal is generated for input signal voltages exceeding the threshold in a periodic first time frame. In a second periodic time frame (following the first time frame), a count is updated in response to the generated detection signals. The count is used to create a metric representative of the difference between the input signal voltage and the threshold. The count is incremented in response to the generating a detection signal (“1”) in the first time frame, and decremented in response to not generating a detection signal (“0”) in the first time frame.

Abstract: Methods and related computer program products, systems, and devices for auto-focusing in an image-capturing system includes sampling output signals from an auto-focusing circuit in a first interval of lens distances and determining a first lens distance and a second lens distance corresponding to the two highest values of the sampled output signals in the first interval of lens distances.

Abstract: A data slicer of the present invention comprises a reference voltage generation circuit and a comparator. The reference voltage generation circuit comprises a plurality of capacitances which area connected in parallel to one another, holding electrical charges on the basis of an input signal, a plurality of first switches which are connected to the plurality of capacitances with first nodes, respectively, for controlling the inflow of the input signal to the plurality of capacitances and a plurality of second switches which are connected to the plurality of capacitances with the first nodes, respectively, for controlling the connection among the plurality of capacitances. The plurality of first switches are controlled with predetermined timing where these first switches are individually brought into an ON state, and the plurality of second switches are controlled with predetermined timing where all the second switches are brought into an ON state.

Abstract: A system and method are provided for measuring the amplitude of a received signal. The method receives an analog input signal, and compares a peak value of the analog input signal to a threshold level. Threshold transition data is generated, and the threshold level is adjusted in response to the transition data. The above-mentioned processes of comparing, generating, and adjusting are reiterated until the threshold level is about equal to the analog input signal peak value. As a result, a measurement of the analog input signal peak value is supplied. In one aspect, threshold transition data is converted into a digital value. Then, the measurement of the analog input signal peak value uses the digital value to represent the analog input signal peak value. Further, the digital value is converted into an analog voltage as feedback, and the analog voltage is used as the threshold level.

Abstract: A receiver for receiving a switched signal on a communication line (1), such as a LIN bus, the signal varying between first and second voltage levels (sup, ground). The receiver comprises a comparator (31, 54) responsive to the relative values of the received signal voltage level (Vlin) and an input reference voltage level (Vsup). The comparator (31, 54) comprises a current generator (40, 41) selectively operatble when the recieved signal is asserted to produce an input current (Iin) which is a function of the received signal voltage level (Vlin) and a reference current (Isup) which is a function of the input reference voltage level (Vsup), and output means (28, 32, 31; 55, 56) responsive to the relative values of the input current (Iin) and the reference current (Isup). The output means (28, 32, 31; 56) is supplied with power at a voltage (VDD) substantially lower than the difference between the first and second voltage levels (Vsup, ground).

Abstract: A data slicer with a source-degeneration structure is described. In particular, this invention can be implemented in a FM demodulation system. It located at the end of the demodulator. The data slicer can slice a signal transmitted through air and demodulates the same with a demodulator to produce a frequency-shifted modulation (FSK) signal. The signal is a perfect square-wave and is transmitted to a base band circuit. The data slicer with a source-degeneration structure obtains the exact reference voltage. The reference voltage is not affected by noise and doesn't need the coupling capacitor, so it can reduce the difficulty of manufacture and cost. The present invention has a common-source unit with a source-degeneration resistor for producing an input signal and a reference voltage, and a comparator unit for comparing the input signal and the reference voltage and outputting a square-wave signal that corresponds to the input signal.

Abstract: A method and device are disclosed for the detection and synchronization of a signal in a frequency-hopping system. The method has a step, for each frequency F(1) . . . F(M), of selecting the K samples corresponding to the greatest values of the signal, and their positions. For a given position, the M greatest values are combined which are selected from among K samples on each frequency having the given position. The greatest combined value is kept and the corresponding position. The greatest combined value is compared with a threshold value, and if the greatest combined value is greater than this threshold value, then the detection of the signal is declared.

Abstract: The discrimination phase margin monitor circuit (10) of the present invention comprises a first discrimination circuit (11 and 12) discriminating an input data signal using a clock signal extracted from the input data signal, a second discrimination circuit (13 and 14) discriminating the input data signal using a clock signal with a frequency different from that of the clock and an operation circuit (15 and 16) calculating the exclusive OR of the output signal of the first discrimination circuit and that of the second discrimination circuit and obtaining a phase margin monitor output signal by averaging the exclusive ORs.

Abstract: A fully differential peak detection circuit includes programmable sensitivity and an autozero function. The peak detector has a fully differential charge-coupled analog signal path. The entire analog signal path is autozeroed upon enable and/or in response to sensing a logic zero at the output, where the logic zero follows a logic one. The peak detector includes a differential gain stage for receiving an analog input signal. The differential gain stage includes offset error compensation. The offset error compensation is selected upon enable and/or in response to an output signal of the peak detection circuit and automatically zeros an offset error voltage in response to a predetermined logic state of the output signal. The output of the gain stage is provided to a comparator stage. A plurality of capacitors coupled to the comparator stage stores a predetermined voltage for setting a sensitivity of the peak detector.

Abstract: Circuitry and methods allow signal detection based entirely on differential voltage pairs. An incoming differential data signal is processed by separate full-wave rectifiers to extract high and low peak voltage envelopes. The rectifiers utilize negative feedback to ensure accurate envelope detection, and can detect peaks regardless of incoming signal polarity. The extracted envelopes are compared to a differential pair of threshold voltages. If the envelope signals have a smaller voltage difference than that of the threshold signals, the final output of the detector indicates that a loss-of-signal condition has occurred. Fully differential operation makes the detector independent of common-mode voltage, and thus more robust.

Abstract: A diode-less peak detector comprises first and second comparators (U1, U2) for comparing an input signal (V) with a peak signal. The first comparator (U1) is connected such that the peak signal functions as a reference and the second comparator (U2) is connected such that the input signal functions as a reference. An inverter (U4) is provided for inverting the output of one of the first and second comparators. Means, such as an AND gate (U3) is provided responsive to the output of the inverter and the other of the first and second comparators so as to provide a switching signal. A MOSFET (Q1) is provided responsive to the switching signal and adapted to adjust the magnitude of the peak signal towards the magnitude of the input signal only when the magnitude of the input signal is greater than the magnitude of the peak signal.

Abstract: A peak detection circuit with double peak detection stages includes an analog peak detector, an analog-to-digital converter (ADC), and a digital peak detector. The analog peak detector receives an analog input signal, detects a peak value of the analog input signal with a first period, and outputs an analog peak signal. The ADC receives the analog peak signal and converts it into a digital signal. The digital peak detector receives the digital signal, detects the peak value of the digital signal with a second period longer than the first period, and outputs a digital peak signal. Therefore, the analog peak signal will not decay seriously due to the leakage and the digital peak signal can hold the digital peak value for a long time.

Abstract: Paying attention to the difference between a subsequently inputted analog signal and a reference signal which is an analog signal converted to the digital signal immediately before for instance, changing timing dynamically for converting the analog signal to the digital signal, and converting an analog signal sampled at the timing of changing dynamically to a digital signal.

Abstract: A semiconductor integrated circuit includes a first clock input and a second clock input to receive elements of a differential clock signal. Each clock signal element has a logic state. The circuit generates an output activation signal that depends on the states of the differential clock input signals. Operation of the circuit does not require detection of a frequency of the differential clock signal.

Abstract: A level discrimination circuit includes two offset compensation circuits. Each offset compensation circuit receives a differential pair of input signals, detects their peak values, and adds the peak value of each input signal to the other input signal, thereby generating an offset-compensated differential pair of output signals. The output signals of the first offset compensation circuit are used directly as the input signals of the second offset compensation circuit. The output signals of the second offset compensation circuit therefore have the correct duty cycle, and can be correctly discriminated by a comparator, even if the input signals to the first offset compensation circuit are burst signals in which each burst includes a large direct-current bias. This level discrimination circuit is suitable for receiving optical signals transmitted in bursts.

Abstract: An Ultra-low power voltage detection circuit is implemented in a digital integrated circuit to device to provide a basic timer, programmable timer and programmable low voltage detection (PLVD) using a single connection of the digital integrated circuit device and a passive component(s) external to the digital integrated circuit device. An internal low current source may be enabled so as to discharge an external timing capacitor connected to the output connection, thus eliminating the need for an external resistor. However, timing accuracy may be improved by adding an external discharging resistor and/or charging resistor. The output connection may be configured as a tri-state output and may be driven high to charge and low to discharge the timing capacitor. A voltage reference may be used in determining a voltage trip point for timing and low voltage detection purposes.

Abstract: The present invention comprises a circuit consisting of four transistors (101-104) and an optional clamping Zener (107) arranged such that the current drawn through a load (120) is equal to the lesser of an input current (106) and a reference current (105).

Abstract: A threshold value at a side of a bottom value of a sensor signal is renewed by a value calculated by multiplying a minimum value of a deviation between the bottom value and a reference value for the predetermined period of time by a ratio when the minimum value of the deviation is equal to or smaller than the threshold value. A threshold value at a side of a peak value thereof is also renewed by a value calculated by multiplying a minimum vale of a deviation between the peak value and the reference value from the predetermined period of time by a ratio when the minimum value of the deviation is equal to or smaller than the threshold value.

Abstract: A method of processing a pulse response with an adaptive threshold and corresponding receiver. According to the method, an adaptive threshold is calculated that is a function of a maximum reached by the pulse response, noise, and a coefficient adjustable between 0 and 1. The processing only comes into operation for signals that exceed this threshold. Such a method may find application notably to digital radio-communications with spread spectrum.

Abstract: A system and method are provided for compensating a comparator threshold level. The method comprises: accepting an input signal with an ac component; lowpass filtering the input signal to generate the input signal average voltage; accepting the input signal average voltage; accepting a first dc level; summing the average voltage with the first dc level; supplying a first sum as a first comparator threshold level; comparing the input signal to the first comparator threshold level; and, supplying a first comparator output signal with an ac component. In some aspects of the method, accepting a first dc level includes accepting a plurality of dc levels. Then, the average voltage is summed with each of the plurality of dc levels and supplied as a corresponding plurality of comparator threshold levels. The input signal is compared to each of the comparator threshold levels and a plurality of comparator output signals are supplied.

Abstract: In accordance with one embodiment of the present invention, a signal detect circuit may analyze an input signal before passing it on to a receiver. The analysis may be done outside of the data path to avoid affecting the data path speed or adding distortion or jitter. The positive and negative thresholds of the data may be checked to see if the numbers of positive and negative crossings are comparable. Random and bursty noise can be detected since such noise normally does not have comparable positive and negative crossings.

Abstract: An apparatus and method for detecting gear features is provided. The apparatus includes a magnetic-sensing element, a thresholding module, and an output module. The magnetic-sensing element may provide a sensor-output signal indicative of the presence of a gear feature. The thresholding module may (i) transform the sensor-output signal into a characteristic waveform, which is also indicative of the presence of the gear feature; (ii) detect a first difference between the characteristic waveform and a reference signal, and responsively provide a tracking signal that tracks this difference; and (iii) detect a second difference between the tracking and reference signals, and responsively adjust the sensor-output signal. Adjustment may be performed (i) as a function of the second difference when it falls below a given threshold and (ii) by a predetermined amount when the second difference satisfies the given threshold.

Abstract: A programmable transducer device that includes a signal source (e.g., a sensor) and a transducer output to output a transducer output signal and to receive a control signal from an external control unit. The control signal is superposed on the transducer output signal, and is detected at the transducer output from a resultant superposition signal by a detector circuit. The transducer output signal and the control signal may co-exist on the transducer output. Advantageously, providing a programmable transducer device that is actuated by control signals conducted through the transducer output and does not need to be switched over to a special receiving state, ensures the uninterrupted transmission of transducer output signals even while the control signals are received by the programmable transducer device. In addition, no additional signal path is required for programming.

Abstract: There is provided a signal detection circuit capable of detecting a signal at a high speed having small amplitude, and a data transfer control device and electronic equipment using the same. The signal detection circuit includes a peak hold circuit, a constant potential setting circuit, and a comparison circuit. The peak hold circuit holds a peak value of an input signal at a given node. The constant potential setting circuit always returns the potential at the given node changed by holding the peak value by the peak hold circuit to a constant potential at a time constant greater than the potential change caused by holding the peak value. The comparison circuit compares the potential at the node at which the peak value is held and which is slowly returned to the constant potential with a given reference level, and outputs the comparison result as a detection signal.