Abstract: An interleaved digital peak detector has multiple acquisition pipes with each pipe receiving a common input signal. Each acquisition pipe receives a common sample clock signal that is delayed through an analog delay circuit for selectively delaying the sample time of each analog-to-digital converter in the pipe. Each pipe has peak detector that receives the digitalized output from the analog-to-digital converter and accumulates maximum and minimum peak values. A programmable decimator receives the sample clock signal and a decimation value for establishing an acquisition clock by decimating the sample clock signal as a function of the decimation value to trigger a latch circuit for storing the accumulated maximum and minimum values from the peak detector.

Abstract: A circuit to generate a servo burst signal, including a circuit to generate a first differential signal and a second differential signal, a first half wave rectifier to rectify the first differential signal and to generate a first rectified signal, a second half wave rectifier to rectify the second differential signal and to generate a second rectified signal, a first peak detector to detect a first peak of the first rectified signal, a second peak detector to detect a second peak of the second rectified signal, and a circuit to generate the servo burst signal based on the first peak signal and the second peak signal.

Abstract: It is common that the presence of a defect causes abnormal gate output voltage excursions in data buffers, AND gates, OR gates and multiplexers in current-mode logic circuits. A voltage excursion is detected by a voltage excursion detection apparatus which includes a built-in detector. The detector, which is little overhead, is used to monitor output swings of all gates (differential circuits) and flags all abnormal voltage excursions. These detection results cover classes of faults that cannot be tested by stuck-at testing methods only. The voltage detection apparatus works well below "at-speed" frequencies.

Abstract: A magnetic-field-to-voltage transducer includes a Hall element and a digitally gain-controlled Hall-voltage amplifier that produces an analog signal voltage Vsig having excursions of one polarity corresponding to the passing of magnetic articles. The gain of an AGC Vsig amplifier is only decreased in small sequential gain increments during an initial interval defined as that in which two excursions in Vsig have occurred, and the gain remains unchanged thereafter. Vsig is applied to the input of a peak-referenced-threshold signal detector that generates a binary output voltage, Vout, having transitions of one direction and the other direction corresponding respectively to the approach and retreat of the passing articles. The peak-referenced-threshold signal detector includes a dual-threshold-voltage comparator which is set to a large threshold at start-up.

Abstract: A data slicer which effectively compensates for wobble and asymmetrical phenomena due to optical and electrical characteristics of a disk. The data slicer includes a comparator for outputting a pulse signal by comparing an RF signal detected by an pickup device with a slice reference value, a low pass filter for low-pass-filtering the pulse signal output from the comparator, a first differential amplifier for detecting the difference between the output of the low pass filter and a predetermined reference value (Vref), and providing the detected difference as the slice reference value of the comparator, a peak detector for detecting a peak value of the RF signal, a bottom detector for detecting a bottom value of the RF signal, and an average value detection portion for detecting an average value of the peak value detected by the peak detector and the bottom value detected by the bottom detector, and adding the detected value to the slice reference value of the comparator.

Abstract: The present invention includes a circuit for detecting voltage levels in an integrated circuit including a first reference voltage(324), a first differential amplifier(349) having an inverting input terminal connected to the first reference voltage, a non-inverting input terminal and an output terminal, a first transistor (356) having a control terminal connected to the output terminal of the first differential amplifier, having a first current handling terminal connected to a voltage supply terminal and having a second current handling terminal connected to the non-inverting input terminal of the first differential amplifier, a first load (358) device having a first terminal connected to the second current handling terminal of the first transistor and a second terminal, a second load device (360) having a first terminal connected to the second of the first load device and a second terminal connected to a second reference potential, a second differential amplifier (391) having an inverting input terminal, a n

Abstract: An input first stage circuit performing switching between activation and inactivation in response to an input signal includes a differential amplifier for comparing the input signal with a reference voltage and a switching transistor for receiving a power supply disconnection signal to control the power supplied, and a level detection circuit including a low level standby detector for detecting a low level of the input signal and a high level standby detector for detecting a high level of the input signal.

Abstract: A regulator system includes first and second voltage sensing circuits coupled to a voltage generator control circuit. The first and second voltage sensing circuits are configured to monitor the voltage generated by the on-chip voltage generator (i.e., the on-chip supply voltage) and detect when the on-chip supply voltage reaches thresholds that are predetermined to define a desired range of the on-chip supply voltage. The voltage generator control circuit receives voltage sense signals from the voltage sense circuits and, in response, asserts or de-asserts a control signal received by the on-chip voltage generator so as to activate or de-activate the on-chip voltage generator to maintain the on-chip supply voltage within the desired range. The voltage generator control circuit introduces hysteresis in the generation of the control signal provided to the on-chip voltage generator.

Abstract: A peak detector circuit (100) includes an output transconductance amplifier (102), a current rectifier (104) and an averaging circuit (108). The current rectifier includes an amplifier (115) which reduces input impedance of the current rectifier to increase the operating frequency of the peak detector circuit. An isolator (106) employs a current mirror (509) with a cascode transistor (512) having a bias potential which is dynamically adjusted to achieve accurate mirroring. An amplifier of a common mode feedback circuit (110) has improved linearity.

Abstract: To solve a problem that, as the number of signal sources for outputting peak values decreases, a peak output voltage decreases, and to improve detecting precision, there are provided a plurality of first buffer units ?Q.sub.11 .multidot.Q.sub.21 .multidot.M.sub.31 to Q.sub.13 .multidot.Q.sub.23 .multidot.M.sub.33 !, which are emitter-follower circuits, to each of which a signal is input, a plurality of second buffer units ?Q.sub.31 to Q.sub.33 ! which are respectively connected to the first buffer units and an output unit for outputting the detected peak signal.

Abstract: An automatic threshold control circuit includes a bottom detection circuit, a relative peak detection circuit, and a voltage divider circuit. The bottom detection circuit detects an absolute minimum level of an input signal, and the relative peak detection circuit detects, in accordance with the input signal, a maximum level relative to the minimum level detected by the absolute bottom detection circuit. Further, the voltage divider circuit generates a threshold level by dividing the absolute minimum level and the relative maximum level in a predetermined ratio. Using this configuration, a signal amplifying circuit can be constructed that is capable of accurately reproducing digital signals at all times regardless of variations in the amplitude or the DC level of the input signal.

Abstract: The present invention relates to an analog voltage-signal selector device of the type comprising at least one plurality of comparator circuits operating in parallel and each having at least a first and second input terminals and designed to receive respectively an analog voltage-comparison signal and analog voltage signals of predetermined value and at least one output terminal for digital voltage signals. This selector device also comprises at least one logic circuit having a plurality of input terminals each connected to a corresponding output terminal of the comparator circuits and at least one output terminal. Finally the selector incorporates at least one plurality of latches each having at least one input terminal connected to the output terminal of a corresponding comparator circuit and at least one drive terminal coupled to the output terminal of the logic circuit with each of the memory circuits having at least one output terminal corresponding to an output of the selector.

Abstract: A differential comparison circuit obtains an improved common mode range with respect to the voltages on first and second inputs. A first comparator is activated when the first and second input voltages are above a first level. A second comparator is activated when the first and second input voltages are below a second level. The output of the comparator that is activated is selected for providing the comparison output signal. In this manner, the comparator having improved performance, typically in terms of differential input voltage sensitivity, may be selected for the voltages present at the inputs. In a typical embodiment, the first comparator uses n-channel input devices, and the second comparator uses p-channel input devices. The activation is provided by voltage level-sensing circuitry, and may include hysteresis to help ensure reliable operation.

Abstract: A power level sense circuit which is substantially immune to variations in integrated circuit processing and operating temperature. The sense circuit uses a diode biased to a predetermined average conduction level as the primary element in an envelope detector to detect the envelope of the RF transmit signal. While the DC offset of the diode will vary with temperature and integrated circuit processing, the DC offset is eliminated by an auto zeroing procedure before each power sensing cycle.

Abstract: The present invention overcomes the shortcomings and deficiencies of the prior art by providing a circuit for processing an AC signal having a peak to peak envelope associated therewith, this circuit including structure for detecting the upper edge of the peak to peak envelope of the AC signal, structure for detecting the lower edge of the peak to peak envelope of the AC signal, structure for sampling the AC signal at a mid range upper point, and structure for sampling the AC signal at a mid range lower point.

Abstract: A circuit for generating a time base signal from a power line signal produced by an alternating current (AC) power source. The circuit sets the output of a latch to a first state when a positive peak of the power line signal is detected, and sets the output of the latch to a second state when a negative peak is detected. Peaks are detected based upon comparisons between the power line signal and a reference voltage. A reference circuit derives the reference voltage from the power line signal using an AC-to-DC converter to generate a peak voltage signal from the power line signal and a reference generator to generate a reference voltage based upon the peak voltage signal. Positive and negative peaks are detected using positive and negative peak detectors.

Abstract: A voltage detector circuit (10) for detecting voltage levels of a digital data bitstream has an input terminal (20) coupled to receive the digital data bitstream. A first peak detector circuit (40) coupled to the input terminal detects a positive peak voltage, and provides a first peak signal. A first differential amplifier is coupled to the input terminal and further coupled to receive the first peak signal, for providing a first difference signal. A second peak detector circuit is coupled to receive the first difference signal from the first differential amplifier, for detecting a peak voltage in the first difference signal and for providing a second peak signal. The first peak signal indicates the value of logical 1 levels in the bitstream, and the second peak signal indicates the relative value of logical 0 levels in the bitstream with respect to the logical 1 levels.

Abstract: A bias current controlling circuit minimizes the power consumption of a high-frequency power amplifier incorporated in a battery powered portable telephone by controlling a bias current supplied to the high-frequency power amplifier in such a manner that an output signal of the high-frequency power amplifier increases the distortion as large in an allowable range as possible, because the bias current is inversely proportional to the magnitude of the distortion.

Abstract: A method and apparatus for signal threshold adjustment that compensates for signal asymmetry which utilizes an algorithm to detect each side of an asymmetric signal independently to ensure that the proper signal detection point is used on both the high and low side of the asymmetric signal. In particular, the high side threshold is adjusted downwards a predetermined amount until detected, the high side threshold voltage is then recorded and reset to the maximum value. Correspondingly, the low side threshold is then adjusted upwards the predetermined amount until detected, the low side threshold voltage is then recorded and reset to the minimum value. The algorithm may be repeated to continuously monitor a signal. The gain of the read amplifier can then be accordingly adjusted by the controller such that it approximately equals the peak of the amplified reference burst to the predetermined value.

Abstract: A circuit for use with a magnetic sensing device having at least first and second sensors has a summing amplifier for providing a difference signal and a peak detector for detecting peaks in the difference signal. The peaks determine a spatial offset of a transition in a sensed body.

Abstract: A method and apparatus for recovering timing information from a ternary signal includes transforming a ternary signal into a binary signal while retaining the necessary timing information. A two facet circuit initially receives a ternary signal, one that includes three levels of values. A first facet of this circuit transforms the ternary signal into two binary signals, each having one of the three levels represented by one value and both having the same level represented by the other value. The second facet of this circuit combines the two binary signals to produce a third binary signal that has one value representing one level and another value representing the two other levels.

Abstract: In a full-wave rectifying circuit comprising a differential amplifier (20) differentially amplifies an input alternating current signal (V.sub.IN) to produce first and second amplified output voltages (V.sub.O1, V.sub.O2) and a voltage reference circuit (30) for generating a reference voltage (V.sub.REF), a differential pair circuit (40) carries out half-wave rectification on the first and the second amplified output voltages on the basis of the reference voltage to obtain first and second half-wave rectified currents (I.sub.C3, I.sub.C4). The differential pair circuit (40) includes a combining part (44) for combining the first and the second half-wave rectified currents into a full-wave rectified current (I.sub.RO). The full-wave rectifying circuit may further comprise a current/voltage converting section (50) for converting the full-wave rectified current into a full-wave rectified voltage (V.sub.RO).

Abstract: The device proposed comprises a Hall sensor (101) with an associated magnet (102), a pulse-generation wheel (104) rotating at an angular speed w and fitted with teeth having a rising and falling face, the wheel turning in front of the sensor to generate a curve which corresponds exactly to the tooth-face positions and which can be used to determine precisely the position of the rotating shaft. The Hall sensor 9101) registers the variation with time of the magnetic flux density through the pulse-generation wheel (104) as a Hall voltage signal. This signal is converted by a differentiator circuit (103.2) into a differentiated signal. The maxima and minima of the differentiated signal are determined and a digital output signal (AS) is generated form the differentiated signal, the low-level to high-level transitions in the output signal corresponding to the maxima of the differentiated signal and the high-level to low-level transitions corresponding to the minima.

Abstract: A digital peak detector formed of a plurality of comparators for outputting signals which, in combination, can form a thermometer code signal, apparatus for distributing an analog input signal to an input of each of the comparators, a plurality of digital to analog converters (DACs), apparatus for providing an output signal of each DAC to another input of a corresponding comparator, and apparatus for applying a digital signal to an input of each DAC to establish a comparison level against which a corresponding DAC can determine an output signal level.

Abstract: A low voltage constant transconductance input stage is achieved with relatively simple design methodology. The approach uses current-mode techniques and is based upon the processing of signal currents, rather than handling the bias currents of input stages. Such an approach becomes universal and independent of the input stage transistor types (FET or bipolar) and their operating regions. Further, the arrangement considerably simplifies the design procedure of low voltage operational amplifiers. MOS and bipolar Op Amp input stages are described wherein almost constant g.sub.m is achieved which is independent of the common mode input voltage ranging from rail-to-rail.

Abstract: A playback signal is supplied to a delay amplifier and a noise comparator. The delayed playback signal is supplied to a comparator, which compares the delayed playback signal with the playback signal and provides a first comparison signal to a pulse adjustment circuit. The noise comparator compares the playback signal with threshold signals and provides a second comparison signal to the pulse adjustment circuit. The pulse adjustment circuit generates the peak detection signal at each point when the signal level of the first comparison is inverted, and determines the peak detection signal to be invalid when the signal level of the playback signal falls within the range between the threshold signals. A read signal is generated based on the valid peak detection signal.

Abstract: The present invention overcomes the aforementioned shortcomings and deficiencies of the prior art by providing a circuit for processing an AC signal having a peak to peak envelope associated therewith, this circuit including structure for detecting the upper edge of the peak to peak envelope of the AC signal, structure for detecting the lower edge of the peak to peak envelope of the AC signal, structure for sampling the AC signal at a mid range upper point, and structure for sampling the AC signal at a mid range lower point.

Abstract: An accurate peak-to-peak detector, readily implemented in CMOS and consuming low power. The peak-to-peak detector includes a clamp portion (circuit) followed by a peak-detect portion (circuit), each of which circuits includes at least one active component (e.g., transistor). The clamp circuit receives an input signal having an alternating current (AC) component via an input coupling capacitor which outputs a voltage on a line to the peak-detect circuit. The clamp circuit includes either a passive load element (e.g., a resistor), or an active load element (e.g., a CMOS transistor), so that the clamp circuit bleeds current from the input coupling capacitor, and any slow drift in the DC level of the input voltage will be followed. The peak-detect circuit follows the voltage output by the coupling capacitor, and includes either a passive load element (e.g., a resistor) or an active load element (e.g.

Abstract: An extreme level circuit for determining an extreme level of a plurality of input levels includes a plurality of independent parallel branches (T4+M2+M5, T5+M3+M6) with intercoupled output terminals (MAX) from which the extreme level can be taken. Each branch has an input terminal (INA, INB) for receiving a respective one of the input levels, and includes a separate distortion compensation circuit (M2+M5, M3+M6) which is independent of the distortion compensation circuits of the other parallel branches.

Abstract: A peak and valley measuring circuit (40) featuring a single digital-to-analog converter (DAC) (100), a peak counter (110), a valley counter (120), and a comparator (130). The peak and valley measuring circuit (40) uses the peak counter (110) when detecting peaks of the recovered audio signal and the valley counter (120) when detecting valleys of the recovered audio signal. The DAC (100) is used in conjunction with one of the counters (110) or (120) depending on whether peaks or valleys are being detected, and is preferably a current-mode DAC.

Abstract: The peak voltage detector according to the present invention includes (a) an input and output terminals, (b) a comparator for comparing the input terminal voltage to the output terminal voltage, (c) a hold capacitor coupled to the output terminal, and (d) a charge pump coupled between the comparator and the hold capacitor. The charge pump has (i) a current reduction circuit for reducing a charge current that charges the hold capacitor, (ii) a differential input pair for receiving the output voltages of the comparator, (iii) a current mirror for mirroring a current in the differential input pair to the charge current, and (iv) a current source. To detect the peak of the input terminal voltage, the peak voltage detector of the present invention compares the input terminal voltage to the output terminal voltage, and charges the output terminal when the input terminal voltage is greater than the output terminal voltage until the output terminal voltage is substantially equal to the input terminal voltage.

Abstract: A circuit which can be used to hold either the maximum or minimum voltage applied. A comparator compares the input voltage to the previous high or low and a set of two mirror circuits either charge or discharge a holding copacitor to the new value. A control circuit of transistor switches configures the circuit into either a maximum or minimum holding mode.

Abstract: A transistor circuit for detecting and holding a peak or bottom level of an input voltage includes a first transistor connected between a first power line and an output terminal, a capacitor connected between the output terminal and a second power line, a second transistor supplied with the input voltage and producing a current responsive to the input voltage, and a current mirror circuit supplied with the current from the second transistor as an input current and discharging the capacitor with an output current. The output current of the current mirror circuit is preferably designed to be smaller than a charging current to the capacitor from the first transistor.

Abstract: Peak and valley voltages of signals from at least two analog sensors are held by the circuit. A plurality of threshold voltages is generated from the previous peak and valley voltages of the respective analog sensors. The signal of each sensor is compared to the respective threshold voltages to produce a sequences of output transitions for each sensor. The output transitions are combined such that each sequence of output transitions from each analog sensor occurs between sequences of the other analog sensor (or sensors). An optional peak and valley reset is also disclosed.

Abstract: The present invention is a closed loop peak detection circuit comprising switching means, comparing means, control means, two current sources, and a holding capacitor. The switching means selectively provides one of a plurality of input signals to the comparing means. The control means is coupled to the comparing means. The control means receives first and second control signals for selecting one of three modes: reset, peak detect, and hold. First and second current sources are coupled to the control means. A capacitor is coupled to the first and second current sources for generating an output signal. The output signal is feedback coupled to the comparing means. The comparing means determines when one of the plurality of input signals exceeds the output signal. The control means enables and disables the current sources in response to the comparing means and to the first and second control signals.

Abstract: Voltage minimizer and maximizer circuits are provided for both single-ended and fully-differential analog input voltages. A single-ended analog voltage maximizer circuit includes a plurality of operational amplifiers (OP.sub.1, OP.sub.2 . . . OP.sub.N) wherein the number of operational amplifiers corresponds to the number of separate voltages (V.sub.1, V.sub.2 . . . V.sub.N) from which a maximum voltage is to be determined, each of the operational amplifiers receives a single-ended analog voltage at its non-inverting input, each output of the plurality of operational amplifiers is connected to a common output line where the maximum analog voltage output (V.sub.0) will be received, the common output line is also connected to the inverting input of each of the operational amplifiers. Each operational amplifier also has an operational amplifier circuit (FIGS.

Abstract: A circuit for use as a channel of a minimum selector and subtractor circuit includes a P-Channel MOS transistor having a gate connected to an input node, a source connected to the output of a current source, and a drain connected to a fixed voltage source. The source of the P-Channel transistor is connectable to a common conductive line through a first switch. The source of the P-Channel transistor is also connected to the non-inverting input of a transconductance amplifier. The inverting input of the transconductance amplifier is connected to a first plate of a capacitor. The second plate of the capacitor is connected to a fixed voltage source such as ground. The output of the transconductance amplifier is connectable to its inverting input through a second switch. The output of the transconductance amplifier forms the output of the minimum selector and subtractor circuit. A plurality of individual channel circuits may all be connected to the common conductive line.

Abstract: A maximum likelihood sequence metric calculator for use in a sequence decoder for processing sequences of sampled values from a communication channel or recording device. The metric calculator can be used in a maximum likelihood decoder, where the sequence can be based upon a 2-state trellis. This would include duobinary, dicode, or partial response class IV signalling. The survivor metrics for the two states is proportional to the peak amplitude detected for that state. Thus, the peak amplitude for a state is stored by a peak detector, until an opposite polarity amplitude is detected to switch the trellis path to the opposite polarity state. The path switching threshold to a state is determined by the opposite polarity state's peak amplitude and the maximum likelihood threshold value. Since only the peak amplitude of the state is stored, unbounded metric absolute value growth is not a problem.

Abstract: A maximum likelihood detector for a continuous time disk drive read channel includes a dynamic threshold updating circuit for a maximum likelihood detector using both positive and negative comparators for detecting the positive and negative peaks of an input signal; this includes comparing the input signal with at least one present dynamic threshold to produce positive and negative binary gating signals; a control circuit responsive to the binary gating signals, to the input signal, and to the peak detector circuit which identifies qualified input signal peaks; and a threshold update circuit responsive to the identification of qualified input signal peaks, which adjusts the present dynamic threshold by the difference between the input signal and the present dynamic threshold to obtain the next dynamic threshold.

Abstract: In a highly integrated semiconductor memory device, apparatus for setting a stress mode without applying a stress voltage from the exterior is provided. A triggered time point T.sub.S to a stress mode can be set by greatly raising an internal supply voltage when the external supply voltage is raised to a voltage over the stress voltage.