Abstract: The peak comparator circuitry comprises a differential amplifier circuit having an output node to generate a differential amplifier output signal in response to an amplification of a difference of an input signal and a reference signal, and a comparator circuit having an output node to generate a comparator output signal. A feedback path of the peak comparator circuitry is arranged between the output node of the comparator circuit and the output node of the differential amplifier circuit. The proposed peak comparator circuitry allows for a low voltage supply, a low current consumption and a fast output validity.

Abstract: A transmitter circuit for a field bus driver includes a first bus terminal and a second bus terminal for connecting a first bus line and, respectively, a second bus line. The transmitter circuit further includes a first supply terminal for receiving a supply voltage and second supply terminal for receiving a reference voltage, a first switching circuit coupled between the first supply terminal and the first bus terminal, and a second switching circuit coupled between the second bus terminal and the second supply terminal. The first switching circuit includes a first transistor and a second transistor, and the second switching circuit includes a third transistor and a fourth transistor. Further, the transmitter circuit comprises control circuitry configured to generate first drive signals for the first transistor and the third transistor and second drive signals for the second transistor and the fourth transistor based on a transmit signal.

Abstract: A method for determining the position of a motor-vehicle crankshaft with a rotating target wheel including markers distributed uniformly over its periphery and a signature, and a sensor sending an electrical signal with edges that appear during the passage of a marker or of the signature before the sensor, including: determining detection time of an edge; determining detection time and computing time difference between estimation and determination; determining angular error; determining presence of an abnormal edge when the angular error exceeds a threshold and storing the associated marker number in a first error list; when the signature passes, copying the first error list to the second if it does not exist; adjusting an occurrence counter depending on the error list; and if the errors are not transient, correcting edges with marker numbers in memory in the second error list, then sending a crankshaft position signal depending on the signal.

Abstract: A CAN bus transceiver includes CAN bus fault detection circuitry that can provide detailed information to simplify the task of the service technician when there is a CAN bus fault. Voltage and current measurements of the CAN bus are made and from them a fault type is determined. A time-domain reflectometer monitors the CAN bus signals for transmitted and reflected signals and from them a distance to the fault is determined. Either or both values are provided to a service technician to allow error determination and correction.

Abstract: A transmission circuit includes a first transmitter and a second transmitter. The first transmitter turns OFF first transistors when a transmission data is in a high level, and turns ON the first transistors when the transmission data is in a low level. When a permission signal is in the high level, the second transmitter turns ON the second transistors when the transmission data is in the high level, and turns OFF the second transistors when the transmission data is in the low level. Diodes are set to suppress an amplitude of a differential signal in an ON time of the second transistors more than an amplitude of a differential signal in an ON time of the first transistors, to suppress ringing and radiation noise.

Abstract: An electronic fault detection unit is provided that has a first register, a second register, a comparator circuit, and a timer circuit. The first and second register can be written from a first software portion, and a second software portion, respectively. The comparator circuit is arranged to detect that both the first and second register have been written, verify a relationship between first data written to the first register and second data written to the second register, and signal a fault upon said verification failing. The timer circuit is arranged to signal a fault if said verification of the comparator circuit does not occur within a time limit.

Abstract: A controller area network (CAN) includes a CAN bus having a CAN-H wire, a CAN-L wire, and a pair of CAN bus terminators located at opposite ends of the CAN bus. The CAN further includes a plurality of nodes including controllers wherein at least one of the controllers is a monitoring controller. The monitoring controller includes a CAN monitoring routine for detecting a wire short fault in the CAN bus and its location.

Abstract: A latching comparator includes a switching logic circuit coupled to receive a first signal from a first signal circuit, and a second signal from a second signal circuit. The switching logic circuit is further coupled to receive a latching signal that is a rectangular pulse waveform in either a first or a second state. An output circuit having an input terminal is coupled to the switching logic circuit. The input terminal of the output circuit is coupled to receive both the first and second signals to compare the first signal and second signal when the latching signal is in the first state. The input terminal of the output circuit is coupled to receive only one of the first and second signals when the latching signal is in the second state.

Abstract: Embodiments of the present invention provide a comparator and an analog-to-digital converter. A sampling module, a pre-amplifying module, and a coupling module in the comparator obtain a third differential voltage signal according to a positive input signal and a negative reference signal, and obtain a fourth differential voltage signal according to a negative input signal and a positive reference signal. A latch that is in the comparator and formed by a first P-type field effect transistor, a second P-type field effect transistor, a third field effect transistor, a fourth field effect transistor, a first switch, and a second switch is directly cross-coupled through gates, and directly collects the third differential voltage signal and the fourth differential voltage signal to the gates, so as to drive the latch to start positive feedback.

Abstract: Power monitoring circuitry. In some embodiments, comparator circuitry may be configured to receive a first voltage value and a second voltage value, and to identify the greater of the first and second voltage values. Selector circuitry coupled to the comparator circuitry may be configured to power one or more components within the comparator circuitry with a supply voltage corresponding to the greater voltage value. In other embodiments, a method may include identifying, via a comparator, the largest among a plurality of voltage values, and powering one or more logic components within the comparator with the identified voltage value.

Abstract: A bandgap ready circuit for an RFID tag includes a bandgap circuit for providing a bandgap voltage, a first comparator for monitoring first and second voltages in the bandgap circuit and for providing a first logic signal, a second comparator for monitoring third and fourth voltages in the bandgap circuit and for providing a second logic signal, and a logic circuit for combining the first and second logic signals to provide a bandgap ready logic signal.

Abstract: A circuit and method for detecting a brown-out condition and providing a feed-forward transfer function in a power supply circuit. A comparison circuit is coupled to a delay element through a latch. A second delay element is connected between the first delay element and an input of the latch. The output of the first delay element is connected to a clamping circuit via a logic circuit. A first voltage is compared with a reference voltage to generate a comparison voltage, which is transmitted through the latch and the first delay element. The comparison voltage is monitored at an output of the first delay element. A brown-out condition occurs if the comparison voltage being monitored at the output of the first delay element results from the first voltage being less than the reference voltage.

Abstract: A comparator is provided and the comparator includes a comparing input unit and a latching unit. Wherein, the comparing input unit has a first input receiving a first comparing signal and has a second input receiving a second comparing signal. The comparing input unit drives a first intermediate node signal at a first intermediate node depending on the first comparing signal according to a first strobe signal, and the comparing input unit drives a second intermediate node signal at a second intermediate node depending on the second comparing signal according to the first strobe signal. The latching unit determines a comparing result according to at least one of the first intermediate node signal and the second intermediate node signal. In addition, the latching unit latches the comparing result according to a second strobe signal.

Abstract: The present disclosure provides a dynamic comparator with equalization function including a preamplifier, switched latch and dynamic transconductance circuit. The preamplifier amplifies input signals of the dynamic comparator. The dynamic transconductance circuit is inserted between the preamplifier and the switched latch for operating in a reset mode or a comparison mode. When operating in the reset mode, the dynamic transconductance circuit in conjunction with the switched latch performs voltage equalization of output signals of the switched latch, or when operating in the comparison mode, the dynamic transconductance circuit in conjunction with the switched latch receives the output signals generated by the preamplifier and carries out signal transconductance. The switched latch generates output signals as a comparison result of the dynamic comparator based on the transconductance signals generated by the dynamic transconductance circuit.

Abstract: A bi-directional comparator compares two input signals and applies a hysteresis level to the smaller input signal only after the output signal switches logical states and when the two input signals are within a predetermined range of each other. In one embodiment, the hysteresis applied to the smaller input signal is removed when the two input signals are no longer within the predetermined range of each other.

Abstract: An apparatus for comparing differential input signal inputs is provided. The apparatus comprises a CMOS sense amplifier (which has having a first input terminal, a second input terminal, a first output terminal, and a second output terminal), a first output circuit (which has a first load capacitance), a second output circuit (which has a second load capacitance), and an isolation circuit. The isolation circuit is coupled between the first output terminal of the CMOS sense amplifier and the first output circuit and is coupled between the second output terminal of the CMOS sense amplifier and the second output terminal of the CMOS sense amplifier. The isolation circuit isolates the first and second load capacitances from the CMOS sense amplifier.

Abstract: A hysteresis device produces an output signal in accordance with hysteresis characteristics that changes at a plurality of thresholds with respect to an input signal. The hysteresis apparatus includes an input signal adjusting section that outputs an adjustment signal in which an offset level corresponding to each of the plurality of thresholds is added to the input signal, a comparator that outputs a first signal based on the adjustment signal, the first signal being binarized, and a determining section that controls the input signal adjusting section to switch the offset level for each of the plurality of thresholds, that acquires the first signal for each switching of the offset level, and that produces a present output signal based on a previous output signal and the first signal corresponding to the threshold relating to a range to which the input signal is belonged.

Abstract: A latching comparator includes a switching logic circuit coupled to receive a latching signal, a first signal and a second signal. An output circuit having an input terminal is coupled to the switching logic circuit. The input terminal of the output circuit is coupled to receive both the first and second signals through the switching logic circuit in response to the latching signal being in a first state. The input terminal of the output circuit is coupled to receive only one of the first and second signals through the switching logic circuit in response to a signal representative of an output terminal of the output circuit and in response to the latching signal being in a second state.

Abstract: An integrated circuit includes: a circuit pin; a detecting circuit coupled to the circuit pin, and arranged to detect a signal level value of the circuit pin when the integrated circuit operates in a first operational mode; a storage circuit coupled to the detecting circuit, and arranged to store the signal level value; and a controlling circuit coupled to the storage circuit, and arranged to set a voltage level of the circuit pin according the signal level value when a processing circuit of the integrated circuit operates in a second operational mode.

Abstract: A comparator includes: a differential amplifier circuit to operate based on a clock signal and output a first intermediate output and a second intermediate output corresponding to a first input signal and a second input signal respectively; and a differential latch circuit to operate based on the clock signal and vary a state based on the first intermediate output and the second intermediate output, the differential latch circuit having a controllable sensitivity with respect to a state variation of the first intermediate output and the second intermediate output.

Abstract: Differential signal detection circuitry with an integrated reference voltage. The reference voltage is added as an offset to the output voltage, and its integration ensures that variations in the reference voltage closely track variations in the signal. Accordingly, the detection threshold for the signal being detected remains more consistent over variations in the circuit manufacturing process, power supply voltage and operating temperature.

Abstract: A comparator includes: a wide-swing operation transconductance amplifier (OTA), having first and second differential input pairs for receiving first and second differential input signals respectively, the wide-swing OTA generating first and second intermediate output voltages in comparing the first with the second differential input signals; a current switch group; a current mirror group, wherein when an input common mode voltage of the first and the second differential input signal tends to one of a first and a second reference voltage, one of the first and the second differential input pair is turned off, and the current switch group and the current mirror group compensate a current flowing through the other of the first and the second differential input pair; and a decision circuit coupled to the wide-swing OTA, for enlarging a voltage difference between the first and the second intermediate output voltage to output a voltage comparison output signal.

Abstract: A common-source circuit including two branches in parallel between a terminal of application of a voltage and a current source, each branch comprising: a series association of a resistor and a transistor, having their junction point defining an output terminal of the branch; a first switch connecting an input terminal of the branch to a control terminal of the transistor; and a controllable stage for amplifying data representing the level present on the output terminal of the opposite branch.

Abstract: A bandgap ready circuit for an RFID tag includes a bandgap circuit for providing a bandgap voltage, a first comparator for monitoring first and second voltages in the bandgap circuit and for providing a first logic signal, a second comparator for monitoring third and fourth voltages in the bandgap circuit and for providing a second logic signal, and a logic circuit for combining the first and second logic signals to provide a bandgap ready logic signal.

Abstract: A identical-data determination circuit includes a first activation unit configured to activate an output signal when first and second signals each have a first level, a second activation unit configured to activate the output signal when the first and second signals each have a second level different from the first level, an initialization unit configured to deactivate the output signal when an initialization signal is applied, and a storage unit configured to store the output signal.

Abstract: An inverter is configured by double gate TFTs, and an inverter is configured by double gate TFTs. Top gate terminals of the TFTs that configure the inverter are connected to an input terminal DAT(+), and bottom gate terminals are connected to an output of the inverter and an output terminal OUT. Bottom gate terminals of the TFTs that configure the inverter are connected to an input terminal DAT(?), and bottom gate terminals are connected to an output of the inverter. With this, threshold voltages of the inverters are controlled so as to facilitate switching operations of the inverters, and whereby the comparator circuit operates at a high speed. It is possible to obtain a comparator circuit that is insusceptible to a variation in the threshold voltages of the transistors and fluctuation of a common mode voltage of an input signal and capable of operating at a high speed.

Abstract: Traditionally, latched comparators have suffered from performance problems related to exposure of the latch to load capacitances. Even attempts to isolate the latch from the load capacitances by way of resistors has resulted in performance problems (namely, voltage swing degradation). Here, however, a latched comparator is provided that employs inductors to generally provide isolation from load capacitances, which generally improves performance. Moreover, the latch has been modified to accommodate the inductors during a track period (namely, provision of grounding paths).

Abstract: This disclosure relates to permuting transistors to compensate for offsets generated by transient variations of the transistors' parameters.

Abstract: A circuit to minimize thermally generated offset voltages includes a differential pair of transistors having a first transistor and a second transistor and coupled to a current source, a differential input having a first input coupled to the first transistor and having a second input coupled to the second transistor, a pair of bypass transistors having a first bypass transistor and a second bypass transistor, the first bypass transistor coupled in parallel with the first transistor and the second bypass transistor coupled in parallel with the second transistor, wherein the pair of bypass transistors is coupled to the current source, and control circuitry coupled to the pair of bypass transistors for controlling current through the pair of bypass transistors.

Abstract: A dynamic comparator with background offset calibration is provided. The dynamic comparator includes at least one input differential pair, a first back-to-back inverter, a second back-to-back inverter, and an integrator. The input differential pair includes two current branches, wherein one of the current branches has an input referred offset. The first back-to-back inverter determines which one of the two current branches has the input referred offset in response to a first clock signal and generates two control signals accordingly. The integrator generates two calibration voltages for the input differential pair in response to the two control signals, so as to calibrate the input referred offset. The second back-to-back inverter determines a difference between two input signals received by the input differential pair after the input referred offset is calibrated in response to a second clock signal and outputs two comparison signals accordingly.

Abstract: A compare cycle of a comparator includes a precharge phase and a compare phase. During the precharge phase, a node of the comparator is precharged to a defined voltage. In addition, during the precharge phase an input transistor of the comparator is decoupled from the node. During the compare phase, an input voltage is coupled to the node via the input transistor. The input transistor is maintained in saturation during both the precharge phase and the compare phase, reducing switching noise.

Abstract: An envelope detecting circuit is provided. The envelope detecting circuit comprises a source degeneration circuit that amplifies an input differential signal, a differential gain stage that supplies a voltage proportional to the amplified signal, a potential hold circuit that holds the voltage supplied from the gain stage, a comparator circuit that compares the voltage held by the potential holding circuit with a reference potential to output a detect signal, and envelope level adjustment and selection unit that responds to the detect signal and outputs a control signal to the source degeneration circuit.

Abstract: A digital noise filter circuit includes a gating clock generating circuit and a noise filter circuit. The gating clock generating circuit compares logic levels of an input signal and an output signal of the noise filter circuit. The gating clock generating circuit supplies a gating clock as an operating clock to the noise filter circuit when the logic levels of both signals do not coincide, and halts supply of the gating clock when the logic levels of both signals do coincide. The noise filter circuit removes noise from the input signal and outputting the resultant signal as the output signal.

Abstract: To provide a comparator and an A/D converter having the comparator. The comparator includes a differential amplifier circuit section and a differential latch circuit section. A first input voltage signal, a second input voltage signal and a clock signal are inputted to the differential amplifier circuit section. The differential amplifier circuit section operates base on the clock signal to output a first output voltage signal and a second output voltage signal which respectively correspond to the value the input voltage signal and the value of the reference voltage signal and are amplified. The differential latch circuit section operates based on the first and second output voltage signals to keep and output a comparison result between the first input voltage signal and the second input voltage signal.

Abstract: One of differential signals is inputted to a first input terminal. The other of the differential signals is inputted to a second input terminal. A first sample hold circuit samples the signal inputted to the first input terminal and hold it thereafter. A second sample hold circuit samples the signal inputted to the second input terminal and holds it thereafter. A comparison unit compares a signal corresponding to a difference between respective output signals from the first and the second sample hold circuits, with a predetermined threshold value. A latch circuit latches an output from the comparison unit. Sample timings of the first and the second sample hold circuits and a latch timing of the latch circuit can be adjusted independently.

Abstract: An amplifier includes: an operation amplifier including a positive input terminal and a negative input terminal; and a detector which detects that a difference between a voltage of the positive input terminal and a voltage of the negative input terminal is equal to or exceeds a predetermined value and outputs a detection signal.

Abstract: An inverter is configured by double gate TFTs, and an inverter is configured by double gate TFTs. Top gate terminals of the TFTs that configure the inverter are connected to an input terminal DAT(+), and bottom gate terminals are connected to an output of the inverter and an output terminal OUT. Bottom gate terminals of the TFTs that configure the inverter are connected to an input terminal DAT(?), and bottom gate terminals are connected to an output of the inverter. With this, threshold voltages of the inverters are controlled so as to facilitate switching operations of the inverters, and whereby the comparator circuit operates at a high speed. It is possible to obtain a comparator circuit that is insusceptible to a variation in the threshold voltages of the transistors and fluctuation of a common mode voltage of an input signal and capable of operating at a high speed.

Abstract: A clock detector is provided. The clock detector generally comprises a filter, a first branch, a second branch, a latch, and logic. The filter is adapted to receive a clock signal and is coupled to a low threshold inverter in the first branch and a high threshold inverter in the second branch. The latch is adapted to receive the clock signal and is coupled to the first branch, while the logic is coupled to the node between the first branch and the latch, an output of the latch, and the second branch so that it can output a clock detection signal.

Abstract: A circuit for discriminating a ‘Noisy’ state of an output of a squelch circuit is disclosed. A circuit for resolve the ‘Noisy’ state of the output of the squelch circuit is also disclosed which uses the output identification circuit. The output of the squelch circuit and a clear signal are input into a first AND gate. The output of the first AND gate is input into a first flip-flop. An inversed signal of the output of the first AND gate is input into a second flip-flop. The outputs of the first and second flip-flops are input into a discriminating unit including a second AND gate. The ‘Noisy’ state is identified by the output of the second AND gate. Based on the identification result, sensitivity of the squelch circuit is regulated.

Abstract: In one aspect, a differential signal transfer method is provided which includes converting 2M?1 original signals into 2M?1 differential signal pairs, where M is an integer of 2 or more, and wherein each pair consists of a first differential signal and a second differential signal having opposite phases, and transferring the 2M?1 differential signal pairs to 2M signal lines such that each of the 2M signal lines includes overlapping differential signals among the first differential signals and the second differential signals of the 2M?1 differential signal pairs.

Abstract: An input signal detecting circuit includes a plurality of comparators configured to output a plurality of differential output signals in response to a differential input signal, respectively; and a differential exclusive OR circuit configured to output an exclusive OR resultant signal from the plurality of differential output signals outputted from the plurality of comparators. In at least one of the plurality of comparators, a DC operation voltage is changed in response to a control signal supplied to the comparator.

Abstract: According to an embodiment of the present invention, a system is provided for driving at least one light-emitting diode (LED). The system includes an output terminal connectable to an anode of the LED and at which an output voltage can be provided for the LED. A driver loop, connectable to a cathode of the LED, is operable to maintain a LED current flowing through the LED at a desired level, thereby attenuating modulation error attributable to voltage variations at the cathode of the LED.

Abstract: A switching matrix has a first number of inputs and a second number of outputs as well as a conductor arrangement and controllable switching elements by means of which the inputs can be connected with the outputs. The controllable switching elements are fashioned such that at least two independent control signals are required to trigger a switching event.

Abstract: First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half.

Abstract: A voltage detecting circuit included in a battery device includes an input voltage comparing circuit that compares a first threshold value voltage or a second threshold value voltage lower than the first threshold value voltage with an input voltage to control the opening and closing of an output switching element, and a threshold value voltage setting circuit that compares a third threshold value voltage lower than the second threshold value voltage with the input voltage and, when the input voltage changes from a low voltage to a high voltage and intersects the third threshold value voltage, outputs a pulse for a predetermined period thereafter so that the second threshold value is selected in the input voltage comparing circuit. As a result, when the input voltage increases from the ground potential, the second threshold value is compared with the input voltage in the input voltage comparing circuit.

Abstract: There is described a method for increasing an availability and a redundancy of an analog current output as well as an analog current output with increased availability and redundancy. To improve the availability and also the redundancy behavior of an analog current output a first set of current sources is switched to active to generate an output current, one current source respectively of the first set is checked cyclically for serviceability and the other current sources respectively generate the output current in equal parts. Where unserviceability is determined, the corresponding current source is disconnected and removed from the first set. If a malfunction occurs, such as a failure of a current source for example, the output current advantageously does not drop out completely due to the allocation of generation to a number of current sources.

Abstract: A delayed peak detector detects a peak level of an input signal IN at timing lagged behind a peak detector, and a peak difference detector detects a peak difference PLD between a delayed peak level DPL and a peak level PL. A reset portion outputs a reset signal BRS for a bottom detector when a level difference between the peak level PL and a bottom level BL exceeds a predetermined value comparable with the amplitude of the input signal IN and the peak difference PLD exceeds an allowable peak difference PLM. It is thus possible to replace the bottom level BL outputted from the bottom detector with a bottom level based on a latest input signal IN.

Abstract: A comparator is provided. In a first period, input terminal of the pre-amplifier is coupled to a first voltage. A first terminal of the first capacitor is coupled to the second input terminal of the pre-amplifier. A second terminal of the first capacitor is coupled to the first input voltage in the first period, and is coupled to the second input voltage in the second period. The second capacitor is coupled between the output terminal of the pre-amplifier and an input terminal of the gain unit. The switch is coupled between the input terminal and an output terminal of the gain unit. An input terminal of the latch is coupled to the output terminal of the gain unit. The latch outputs a comparison result.

Abstract: A comparator apparatus for comparing a first and a second voltage input includes a pair of cross-coupled inverter devices, including a pull up device and a pull down device, with output nodes defined between the pull up and pull down devices. A first switching device is coupled to the first input and a second switching device is coupled to the second input, with control circuitry configured for selective switching between a reset mode and a compare mode. In the reset mode, the first and second voltage inputs are coupled to respective output nodes so as to develop a differential signal thereacross, and the pull down devices in each inverter are isolated from the pull up devices. In the compare mode, the voltage inputs are isolated from the output nodes, and the pull down devices in each inverter are coupled to the pull up devices to latch the output nodes.

Abstract: A low offset comparator includes a preamplifier and a latch. The preamplifier includes a first output offset storage stage, a cascade of input offset storage stages and a second output offset storage stage. The first output offset storage stage receives an input voltage. The cascade of input offset storage stages is connected to follow the first output offset storage stage. The second output offset storage stage is connected to follow the input offset storage stages. The latch is connected to follow the preamplifier. The low offset comparator is characterized in that the cascade of input offset storage stages, the second output offset storage stage and the first output offset storage stage are configured to sequentially leave an offset cancellation mode, and the input offset storage stages, when leaving the offset cancellation mode, are to open their unity-gain feedback loops before disconnecting their input offset storages from a ground voltage.