Abstract: A microcode-initiated high speed comparator in an optical transceiver includes an initialization and control section consisting of various register sets, an analog section with comparator hardware, and an output retrieval section. The comparator hardware performs comparison on a wide-range of selectable input values, thereby avoiding the need for a dedicated comparator for each input value. The register sets are initialized by microcode with various comparison values, allowing multiplexed comparison to be much faster than it would be if the processor was controlling in real-time the multiplexed comparison. The comparison values may correspond to optimal operational parameters of the optical transceiver or may correspond to other desired comparison values. The analog section is driven by the registers and makes a comparison between the predetermined values and actual operational parameter values.

Abstract: A voltage detecting circuit included in a battery device includes an input voltage comparing circuit that compares a first threshold value voltage or a second threshold value voltage lower than the first threshold value voltage with an input voltage to control the opening and closing of an output switching element, and a threshold value voltage setting circuit that compares a third threshold value voltage lower than the second threshold value voltage with the input voltage and, when the input voltage changes from a low voltage to a high voltage and intersects the third threshold value voltage, outputs a pulse for a predetermined period thereafter so that the second threshold value is selected in the input voltage comparing circuit. As a result, when the input voltage increases from the ground potential, the second threshold value is compared with the input voltage in the input voltage comparing circuit.

Abstract: A circuit for discriminating a ‘Noisy’ state of an output of a squelch circuit is disclosed. A circuit for resolve the ‘Noisy’ state of the output of the squelch circuit is also disclosed which uses the output identification circuit. The output of the squelch circuit and a clear signal are input into a first AND gate. The output of the first AND gate is input into a first flip-flop. An inversed signal of the output of the first AND gate is input into a second flip-flop. The outputs of the first and second flip-flops are input into a discriminating unit including a second AND gate. The ‘Noisy’ state is identified by the output of the second AND gate. Based on the identification result, sensitivity of the squelch circuit is regulated.

Abstract: A comparator comprises complementary (e.g. NMOS and PMOS) comparator cells having overlapping common mode input voltage ranges which together extend approximately from rail to rail. A digital logic arrangement, including edge detectors, gates, and a latch, is responsive to transitions at the outputs of the comparator cells to set the latch in response to the earliest rising edge and to reset the latch in response to the earliest falling edge. An output of the latch constitutes an output of the comparator. Consequently the comparator is edge-sensitive with a speed optimized for a wide common mode input voltage range. Additional logic gates can provide level-sensitive control of the latch.

Abstract: A data receiver and a data receiving method in which the data receiver generates two comparison signals based on amplitude modulated differential input signals, amplifies the comparison signals, compares amplified signals, and outputs logic operation results based on the amplitude modulated differential input signals and the comparison signals, thereby detecting data bits. Accordingly, the number of necessary amplifiers and comparators is reduced and a separate reference voltage generator is not needed, so that chip size reduction and low-power operation is accomplished.

Abstract: A single ended pseudo differential signaling method may add a 1-bit signal to n-bit data if transmitting the n-bit data. Neighboring two signals among the 1-bit signal and data signals are compared to each other to generate detection signals.

Abstract: A circuit and a method are provided to produce a novel comparator with Schmitt trigger hysteresis character. The circuit includes a current source which controls the magnitude of current flow through this comparator circuit. It has a first logic device which is turned ON by a reference voltage, and a second logic device is turned ON by a comparator input voltage. A first feedback device is turned ON by a negative comparator output. A first parallel resistor is connected in parallel to the first feedback device. A second feedback device is turned ON by a positive comparator output. A second parallel resistor is connected in parallel to the second feedback device. The first and second parallel resistors are used to provide the differential comparator with switching voltage offsets which result in the Schmitt trigger hysteresis character.

Abstract: A signal detecting circuit includes first and second differential amplifiers and a differential exclusive-OR circuit. The first differential amplifier is configured to amplify a differential input signal and to output first positive and inversion phase output signals. The second differential amplifier is configured to amplify the differential input signal and to output second positive and inversion phase output signals. A common mode voltage of the second positive and inversion phase signals is shifted. The differential exclusive-OR circuit is configured to compare the first positive phase output signal and the second inversion phase output signal, and the second positive phase output signal and the first inversion phase output signal, and to output an exclusive logical summation of the comparing results as a positive phase exclusive-OR output signal.

Abstract: A comparator is provided that compares one or more input signals in a regenerative circuit. One or more switched isolate the signal inputs after regeneration has started but before regeneration has reached such an extent that large voltage swings in the regeneration circuit are transmitted back to the signal source and corrupt the signal source or neighboring circuits. Furthermore, as controlled by a control circuit, the instant of isolating the signal source can be dependent on the degree of regeneration such as being dependent on a predetermined degree of regeneration. The comparator may be incorporated in an electronic device such as an analog-to-digital converter or a wireless receiver or transceiver.

Abstract: Disclosed herein is a method and system for calibrating line drive currents in systems that generate data signals by varying line drive currents and that interpret the data signals by comparing them to one or more reference voltages. The calibration includes varying the line drive current at a transmitting component. At different line drive currents, a receiver reference voltage is varied while the transmitting component transmits data to a receiving component. At each line drive current, the system records the highest and lowest receiver reference voltages at which data errors do not occur. The system then examines the recorded high and low receiver reference voltages to determine a desirable line drive current.

Abstract: In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch with integrated testability. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, three voting structures with inputs from the first, second, and third settable memory elements, determine the logical value held on each of the settable memory elements. Data may be scanned into and out of the second settable memory element. Data is propagated through the buffer into the third settable memory element. The third settable memory element may be used to scan data out of the triple redundant latch. The propagation delay through a latch is the only propagation delay of the triple redundant latch.

Abstract: The invention pertains to a circuit arrangement (comparator) for the discrete-time comparison of input signals (ip, vrefp) and for making available a pair of complementary output levels (vdd, vss) which corresponds to the result of the comparison on a line pair (P, N), wherein said circuit arrangement comprises a reset circuit (12) for balancing the line potentials during a reset phase, an input circuit (14) for generating a potential difference on the line pair (P, N) in accordance with an input signal difference, a first bistable flip-flop (16) for amplifying the generated potential difference and a second bistable flip-flop (20) that is connected by means of a connecting circuit (18) and serves for additionally amplifying the generated potential difference to the desired complementary output levels.

Abstract: In order to provide a comparator circuit without generating a malfunction, the comparator circuit according to the present invention may comprise a comparator circuit including a differential amplification circuit having a differential pair transistor (M1, M2) for inputting a signal as an object of comparison, and a current mirror load circuit (M3, M4, M5, M6); a latch circuit having inversion amplifiers that are configured so that an input of one amplifier becomes an input of other amplifier so as to amplify a differential output signal outputted from the current mirror load circuit in accordance with a magnitude relation of the signal as an object of comparison; an equalization transistor (M9) for equalizing a signal of the differential amplification circuit; a delay circuit (M13, M14,M15, M16) for generating a signal to delay a control signal to be inputted in a control electrode of the equalization transistor; and a control transistor (M10) for inputting an output signal of the delay circuit in the contro

Abstract: A plurality of LEDs is driven in parallel, in at least two modes. In a first mode, the LEDs are driven with a first voltage. In subsequent modes, the LEDs are driven with successively higher voltages. The forward voltage drop for each LED is monitored, and the driver switches from the first mode to successive modes based on the largest of the LED forward voltage drops. The current through each LED is controlled by directing a reference current through a first digitally controlled variable resistance circuit, and directing the LED current through a second digitally controlled variable resistance circuit having substantially a known ratio to the first variable resistance circuit and connected in series with the LED. A digital count is altered based on a comparison of the first and second currents, and the first and second variable resistance circuits are simultaneously altered based on the digital count.

Abstract: A device and method for selecting within a group of analog signals the one with the lowest or with the highest value. In one embodiment the device has a differential amplifier configuration having an input to receive a comparison signal, a plurality of inputs to receive analog signals and a corresponding plurality of outputs to provide digital voltage signals. This device also has at least one logic circuit having a plurality of input terminals, each connected to a corresponding output of the differential amplifier configuration, and having at least one output terminal.

Abstract: A method of assessing the offset on the output nodes of an amplifying channel includes generating a logic signal for signaling the existence of an offset having a level exceeding a window of permitted levels symmetric about the zero level. The window is defined by a negative limit value and by a positive limit value. The method includes establishing an interval or phase of detection by applying to an input of a detection circuit a timing pulse with a certain frequency, sensing the rising edge of the timing pulse and setting a bistable circuit, and comparing the signal on the output nodes of the amplifiers channel with the window of permitted values. The bistable circuit is reset upon the occurrence, after the initial setting, of an output signal amplitude within the window of permitted values. Failure of the bistable circuit to reset before the end of the detection phase signals an excessive offset.

Abstract: Non linear circuit for open load control in Low-Side Driver type circuits, including at least two power transistors, scaled according to an area ratio 1 to M, with M>1, wherein the power transistor having the smaller area is controlled by a circuit input signal while the transistor having the larger area is controlled by an output value of an AND type logic gate, managed by a control circuit, that is regulated by the output value of a voltage sensor, placed in parallel with the power transistor having the larger area, and by the output value of a current sensor, placed in series with the power transistor having the smaller area, so that, when a current flowing in the power transistor having the smaller area is less than a predetermined value of the threshold current, the control circuit signals the open load on an output pin.

Abstract: A circuit receives data from a high frequency data line. The circuit determines the data value by employing a decision circuit and an over-sampling circuit. The over-sampling circuit captures the data levels on the data line at spaced apart time intervals. The decision circuit employs the data levels captured by the over-sampling circuit and a previously stored value to determine the data level that should be received from the data line.

Abstract: The device for the comparison of the levels of two input signals MI, PI includes a first comparator COMP1, the switching of the comparator being expressed by a change-over of the output OUT1 of the comparator from a first logic state into a second logic state, the change-over of the output OUT1 from one logic state “0” into the other state “1” being faster than the change-over in the other direction. The device also includes a second comparator COMP2 with an identical structure, to whose input the signals to be compared are applied invertedly so that the switching operations in the comparators are inverted. The output of each comparator is applied to an associated logic circuit 1, 2 capable of accelerating the inverse switching in the other comparator for a change in the output corresponding to the fastest change-over.

Abstract: A pre-charged high-speed comparator includes a first negative phase logic switch, a second negative phase logic switch, a third negative phase logic switch, a first positive phase logic switch, a fourth negative phase logic switch, a second positive phase logic switch, a third positive phase logic switch, a fourth positive phase logic switch and a fifth positive phase logic switch. The two output terminals of the pre-charged high-speed comparator is raised to a voltage roughly half of a source voltage so that the time required for a regeneration circuit that includes the third negative phase logic switch, the first positive phase logic switch, the fourth negative phase logic switch and the second positive phase logic switch to get into the transistor active region is shortened, thereby increasing the overall operating speed of the comparator circuit.

Abstract: A signal sorter for magnitude sorting among a number of signals is disclosed that allows for magnitude sorting of a number of signals in an ascending or descending ordered manner governed by the clock controlling signals. The sorter can generate sorted outputs fast enough for real-time applications and has a circuit structure suitable for implementation as integrated circuit devices. The sorter has a signal input section, maximum-deriving section, a feedback control and voltage output section and a sorted output section. All four sections are controlled by a set of timing clock input signals to manipulate the signal magnitude sorting.

Abstract: A sense amplifier includes a bistable circuit and a control circuit. The bistable circuit has first and second input/output terminals connected to two input lines via a gating circuit. The bistable circuit has positive and negative supply nodes, one of which is connected to the output of the control circuit. An inverter is connected from the control circuit output to the gating circuit so that the control circuit activates the bistable circuit at all times except when the gating circuit connects the input/output terminals to the input lines.

Abstract: An integrated XNOR flip-flop is provided which is faster than conventional XNOR flip-flop combinations. The integrated XNOR flip-flop is faster and uses less area than conventional XNOR flip-flop combinations. The integrated circuit has few gates along the critical path and takes advantage of the set up times inherent in the flip-flop. Accordingly, the integrated XNOR flip-flop is able to perform the same function in an expedient manner. In one illustrative embodiment, a plurality of the integrated XNOR flip-flops are used to compare a tag of a cache memory with an address to determine whether the desired address is available in the cache.

Abstract: A system and method is provided having a flash analog-to-digital converter (ADC) that includes an input signal buffer, a plurality of identical voltage comparators, and a reference generator. A clock signal defines the time instances at which the instantaneous input signal voltage is compared against a plurality of reference voltages generated by the reference generator. The individual comparator consists of a an integrating amplifier stage followed by an analog latching stage and a digital latch. The integrating amplifier input is allowed to track the input signal continuously. The amplifier output voltage is forced to a voltage close to zero before each conversion cycle is initiated by the ADC clock. At the beginning of the conversion cycle, the amplifier output is released and its voltage will follow an excursion related to the integral of the input of the amplifier. At a predefined time moment later, the analog latch is activated.

Abstract: The present invention relates to an analog voltage-signal selector device of the type comprising at least one plurality of comparator circuits operating in parallel and each having at least a first and second input terminals and designed to receive respectively an analog voltage-comparison signal and analog voltage signals of predetermined value and at least one output terminal for digital voltage signals. This selector device also comprises at least one logic circuit having a plurality of input terminals each connected to a corresponding output terminal of the comparator circuits and at least one output terminal. Finally the selector incorporates at least one plurality of latches each having at least one input terminal connected to the output terminal of a corresponding comparator circuit and at least one drive terminal coupled to the output terminal of the logic circuit with each of the memory circuits having at least one output terminal corresponding to an output of the selector.

Abstract: A multiple bit dynamic comparator is described which includes logic gates that function to turn-off particular devices that are directly connected to the comparator output node and thereby isolate the output node from parasitic capacitances during a pre-charge/set-up phase. During the pre-charge/set-up phase, the output node is charged to VCC and the input signals to be compared are applied to the appropriate inputs of a plurality of comparison sub-circuits. The plurality of comparison subcircuits are coupled to the output node. Each device within the comparison sub-circuits that is directly connected to the output node of the dynamic comparator (i.e. top row of devices) has its gate coupled to a NOR gate. The inputs of the NOR gate are cross-coupled to input signals being compared such that when a match occurs between the inputs the NOR gates hold all top row devices off. As a result, the pre-charging of the output node during the pre-charge phase is unaffected by unwanted parasitic capacitances.

Abstract: A power-on reset (POR) circuit including a first single-level POR, a second single-level POR, a combining circuit, and a latch. Responsive to the voltage on a voltage supply terminal, the first single-level POR generates a first reset signal which terminates at a first trigger level voltage, and the second single-level POR generates a second reset signal which terminates at a second trigger level voltage. A combining circuit logically combines the first and second reset signals, and generates a combined output signal. This output signal controls a latch which provides the POR signal. When the supply voltage is below both trigger levels a POR signal is generated. When the supply voltage is above both trigger levels, no POR signal is generated. When the supply voltage is between trigger levels of the two POR circuits, the combining circuit leaves a floating output signal. Thus the latch does not switch.

Abstract: An arrangement for monitoring a two-wire bus line for serial transmission of digital data includes a bus subscriber receiving circuit coupled to the two-wire line and including three comparators each having two inputs and an output for producing a logical output signal in dependence of signals at the two inputs. A signal line voltage on each wire of the two-wire bus line is applied, respectively, to the two inputs of a first one of the comparators and one of the two signal line voltages, an auxiliary voltage is applied, respectively, to the two inputs of a second one of the comparators and the other of the two signal line voltages and an auxiliary voltage being applied, respectively, to the two inputs of a third one of the comparators.

Abstract: A regulated power supply can be derived from a battery supply input and a regulator, but in order to conserve battery power, alternative power supplies can be provided each with a switch responsive to the regulator to connect that alternative power supply to the output when it rises to the level of the battery supply.

Abstract: A differential comparator with a hysteresis proportional to the peak value of the input signal. The comparator operates independently of the magnitude of the supply voltage and of the ambient temperature while handling both differential and single-ended inputs and without introducing a delay between the input and the output.

Abstract: A comparator (10) provides a high speed comparison between at least two input signals and includes at least two stages (12) and (14). Each stage (12 and 14) includes a pair of transistors (24), a complementary pair of transistors (28) and an enabling transistor (26). The stages are coupled to provide positive feedback back to the first stage (12). A controller (15) operably couples to the enabling transistors. When the first input signal (16) is at a higher voltage level than the second input signal (18), the first comparison output (20) goes low. Conversely, when the second input signal (18) is at a higher voltage level than the first input signal (16), the second comparison output (22) goes low. When the first comparison output (20) goes low, the second enabling transistor (34) is disabled by the controller (15). When the second comparison output goes low, the first enabling transistor (26) is disabled by the controller (15).

Abstract: A chopper type comparator is disclosed and implements a differential configuration with inverter amplifiers each having a control terminal. The comparator, therefore, successfully cancels noise of the same phase while preventing a current from constantly flowing therethrough. The cancellation of noise of the same phase, coupled with differential signals, doubles the signal range in the same voltage range, compared to a single end configuration. Hence, a high resolution is achievable even when a power source voltage is low.

Abstract: Difference flag logic suitable for use in a FIFO memory is modified to quickly generate FIFO flag status through the use of programmable, resettable counters which eliminate the need for subtractor circuitry. A comparator is used to compare a value from a read counter with a value from a write counter. The subtractor function is replaced by offsetting the read count from the write count by a value equal to the desired FIFO flag value. Offset of the read count from the write count is accomplished by utilizing counters which provide programmable resettability. Use of programmable, resettable counters allows FIFO flag values to be chosen and implemented very easily. For instance, it is possible for a user to change from an almost full FIFO flag to a half full FIFO flag without changing any hardware at all. The counters are simply programmed and reset accordingly.

Abstract: A comparator circuit for comparing a first n-bit binary number to a second n-bit binary number to produce a signal indicating if the first n-bit binary number is greater than or equal to the second n-bit binary number. If the signal is in one logic state, then the first n-bit binary number is greater-than or equal to the second n-bit binary number. On the other hand, if the signal is in a second logic state, then the first n-bit binary number is not greater-than or equal to the second n-bit binary number.

Abstract: The median value of a set of voltage values is found by a technique that minimizes the circuitry while maximizing the speed, and also provides for dropouts. The voltage values, illustratively five in number, are applied in pairs to the inputs of ten comparators. The outputs of the comparators, and their complements, are formed into five "status words" of four bits each, such that each bit of a given status word represents the comparison of a given value with another of the values. The status word that contains two 1's and two 0's represents the median value. In a preferred circuit embodiment, this status word is rapidly determined in a series of three logic stages, wherein the highest and lowest values are eliminated in the first stage, the next highest and lowest are eliminated in the second stage, and the last stage determines the remaining status word that is associated with the median value. This technique also readily provides for dropouts by initializing the logic circuitry.

Abstract: A magnitude comparator is modified to compare the magnitudes of two large binary values more quickly and with minimum gate delays. Bit comparators are divided into groups which generate compare output signals in parallel to one another, thereby reducing magnitude comparator delay. These compare output signals are fed into a control element which determines which compare output signal is allowed to pass through as the final compare output signal. This circuitry, along with logic circuitry which indicates whether corresponding bit values within associated groups exactly match, defines a magnitude comparator block. Multiple magnitude blocks are used to facilitate the comparison of larger binary values. Each magnitude comparator block generates a compare output signal which, in turn, is an input to a corresponding gating element. Each gating element possesses a logic input signal, derived in part from its magnitude comparator block's match logic circuitry.