Abstract: This discloses an integrated circuit and at least one CMOS analog circuit including a first circuit component generating an output signal received by a second circuit component to generate a feedback signal received by the first component to regulate the output signal, where the transistors of the first circuit component consist of first MOS transistor instances compliant with a first core voltage and the feedback signal requires the transistors of the second circuit component to consist of at least one second MOS transistor instance compliant with a second core voltage above the first core voltage. The CMOS analog circuit may implement an amplifier, a transconductance amplifier and/or a telescopic amplifier. The first core voltage may at most 1.2 volts and the second core voltage may be at least three volts. The first MOS transistors may be thin oxide transistors and the second MOS transistors may be thicker oxide transistors.

Abstract: An integrated circuit comparator comprises a differential amplifier, a source follower circuit coupled to a gate terminal of a first transistor in the differential amplifier, and an output circuit. One or more source follower circuits may be utilized in connection with the differential amplifier, and one or more source follower circuits may be utilized in connection with the output circuit.

Abstract: In one aspect, a differential signal transfer method is provided which includes converting 2M?1 original signals into 2M?1 differential signal pairs, where M is an integer of 2 or more, and wherein each pair consists of a first differential signal and a second differential signal having opposite phases, and transferring the 2M?1 differential signal pairs to 2M signal lines such that each of the 2M signal lines includes overlapping differential signals among the first differential signals and the second differential signals of the 2M?1 differential signal pairs.

Abstract: A signal detection circuit is used for detecting signal squelch of a differential input signal to generate a corresponding digital output signal. The signal detection circuit includes: a reference voltage generator for generating a reference voltage of which the common mode voltage tracks the common mode voltage of the input signal; a real-time signal judgment circuit, real-time rectifying and amplifying a difference between the input signal and the reference voltage; and a deglitch circuit, sampling and/or amplifying an output signal of the real-time signal judgment circuit, and transforming sampling results into the digital output signal to reflect signal squelch of the differential input signal.

Abstract: First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half.

Abstract: A comparator used in a parallel-type A/D converter, wherein a comparator 100 includes reset transistors mra and mrb. When the comparator 100 is in the Reset state, the inverted signal /CLK of the clock signal is given to the PMOS reset transistors mra and mrb so as to forcibly reset both of the voltages at two internal nodes Va and Vb being a differential pair to a predetermined reset voltage by the reset transistors mra and mrb. The inverted signal /CLK of the clock signal is produced with a predetermined delay. Thus, when the comparator 100 is in the Reset state, the point in time at which to cancel the reset of the internal nodes Va and Vb is delayed from that at which the comparator performs a comparison operation. Therefore, even if the frequency of the clock signal and the frequency of the analog input signal are high, the voltages at the internal nodes forming a differential pair are well-balanced when the comparator is in the Reset state, thus improving the voltage comparison precision.

Abstract: A semiconductor device stabilizes an operation of an input buffer. A semiconductor device includes an input potential detection unit, an input buffer, and a current sink unit. The input potential detection unit outputs a detection signal in response to a level of an input signal. The input buffer buffers the input signal by differentially amplifying the input signal through a first current sink unit. The current sink unit receives the detection signal, and in response to the detection signal, performs an auxiliary differential amplifying operation with respect to the input signal buffered by the input buffer.

Abstract: A signal conversion circuit 2 comprises a differential amplifier portion 10 and a source follower portion 20. When differential voltage signals INp and INn are input to a first input terminal 5 and second input terminal 6 respectively, operations occurs either in a mode in which only the differential amplifier portion 10 operates, or a mode in which both the differential amplifier portion 10 and the source follower portion 20 operate, or a mode in which only the source follower portion 20 operates, according to the levels of the differential voltage signals INp and INn. The differential amplifier portion 10 and source follower portion 20 have fewer components compared with a circuit comprising two differential amplifier circuits. By this means, the circuit area can be reduced, and in addition current consumption can be reduced. Also, because the source follower portion 20 performs non-inverting amplification of the differential voltage signals INp and INn, high-speed operation is possible.

Abstract: Power-down mode is activated when equal voltages are detected on a pair of differential inputs. The voltage difference across the differential inputs is equalized by an equalizer and then applied to a multiplier and smoothed and filtered by a low-pass filter to produce an average signal. The average signal is compared to a reference voltage to detect when the voltage difference across the differential inputs is too small. A power-down signal is activated when the average signal is too small. The reference voltage compared can be generated by an equalizer, multiplier, and low-pass filter to match process, temperature, and supply-voltage variations in the primary signal path. The multipliers can be implemented with Gilbert cells. The equalizers can receive control signals to control attenuation of different frequency components.

Abstract: A comparison circuit comprising: an input circuit includes a first transistor for receiving a first signal, and a second transistor for receiving a second signal; a first current route of which the electric current is controlled by the first transistor; a second current route of which the electric current is controlled by the second transistor; a latch for amplifying potential difference between the first current route and the second current route; a comparative operation control circuit including a first switch for executing or blocking supply voltage to the drain of the first transistor, a second switch for executing or blocking supply voltage to the drain of the second transistor, and a third switch for executing supply voltage to the first current route and the second current route; a comparative operation setting circuit for controlling supply or blocking of supply of the first switch, the second switch, and the third switch.

Abstract: An input buffer circuit is disclosed. The input buffer circuit includes a buffer configured to receive an input signal and differentially amplify and buffer the received input signal, and a current regulator for regulating the amount of current in the buffer at a turn-on level which depends on a level of a voltage inputted thereto.

Abstract: A receiving circuit includes an impedance compensating circuit, a first input terminal and a second input terminal coupled to a first signal line and a second signal line, a first signal and a second signal corresponding to differential signals being transmitted at the first input terminal and the second input terminal, respectively, a signal input circuit, coupled to the first input terminal and the second input terminal, which receives the first signal and the second signal are input, and a differential-signal detector that detects whether or not the differential signals are supplied to the first input terminal and the second input terminal.

Abstract: Amplifiers with power-on trim and methods using an amplifier system having an amplifier system input and an amplifier system output, an amplifier, a comparator, a successive approximation register having an input coupled to an output of the comparator, a first switch for switching an input of the amplifier from the amplifier system input to shorting the amplifier input, a second switch for switching an output of the amplifier from the amplifier system output to an input of the comparator, an output of the successive approximation register being coupled to an N bit digital to analog (D/A) converter, the D/A converter being a non-binary converter using a radix of less than 2 for at least the most significant bits, and an output of the D/A converter being coupled to the amplifier to control the input offset of the amplifier. Novel embodiments for the amplifier, comparator and D/A converter are disclosed.

Abstract: A semiconductor device includes a reference voltage generating unit configured to produce a reference voltage by dividing a voltage difference between a positive clock terminal and a negative clock terminal, and a logic determination unit configured to determine a logic level of an external signal based on the reference voltage.

Abstract: A method and apparatus for providing a low power low voltage differential signaling driver are disclosed. In an example, a low voltage differential signaling driver circuit is described, comprising a first current source to provide current to a first differential pair of PNP transistors, a pair of transresistance amplifiers driven by a corresponding pair of transconductance stages, a second current source to provide current to a second differential pair of PNP transistors, and an output port having a common mode output voltage and a differential output voltage based on a state of the first differential pair of PNP transistors and the second differential pair of PNP transistors.

Abstract: A main driver amplifier generates first differential signals (Vdp/Vdn) based on pattern data (PAT). A replica driver amplifier generates second differential signals (Vcp/Vcn) based on the pattern data (PAT). Two subtractors generate electric potential difference signals (HP=RP?Vep) and (HN=RN?Ven), respectively. Two sample hold circuits sample the electric potential difference signals (HP and HN), and hold them thereafter, respectively. A comparison unit compares a differential amplitude signal (DA=HHP?HHN) with a predetermined threshold value (VOH). A latch circuit latches an output from the comparison unit. Sampling timings of the two sample hold circuits and a latch timing of the latch circuit, can be adjusted independently.

Abstract: For example, a gain control part and a common node control part are provided in a logic circuit including a data acquisition part that has a differential amplifier configuration and acquires a data input signal when a click signal is an “H” level and a latch part that latches a data output signal from the data acquisition part when the click signal is an “L” level. The gain control part is provided between common nodes of NMOS transistors in the differential amplifier and serves to make the gain of the differential amplifier higher in a high frequency band than in a low frequency band. When the clock signal is an “L” level, the common node control part serves to control an electrical charge so as to eliminate a potential difference between the common nodes. Thus, the transition time of the data output signal is speeded up and the setup margin is increased in the latch part. The above described technique can therefore speed up operations of various logic circuits such as a latch circuit.

Abstract: An input circuit is disclosed. The input circuit can include a cross voltage generating block that can be configured to perform charge-sharing on a pair of input signals whose phases are opposite to each other and generate a cross voltage, and an input buffer block that can be configured to buffer the pair of input signals at a voltage level corresponding to a voltage level of the cross voltage and generate an output signal.

Abstract: A fail-safe differential receiver having a differential amplifier adapted to receive first and second differential input signals and generate a differential voltage. A peak detector is coupled to the differential amplifier for generating a detect signal and a comparator is coupled to the peak detector for comparing the detect signal to a threshold voltage and providing a comparison signal. A directing circuit is coupled to the differential amplifier for receiving the first and second differential input signals and is coupled to the comparator for receiving the comparison signal. An output amplifier is coupled to the directing circuit. The directing circuit selectively directs the first and second differential input signals to the output amplifier as a function of the value of the comparison signal from the comparator.

Abstract: A data receiver and a data receiving method in which the data receiver generates two comparison signals based on amplitude modulated differential input signals, amplifies the comparison signals, compares amplified signals, and outputs logic operation results based on the amplitude modulated differential input signals and the comparison signals, thereby detecting data bits. Accordingly, the number of necessary amplifiers and comparators is reduced and a separate reference voltage generator is not needed, so that chip size reduction and low-power operation is accomplished.

Abstract: A sense amplifier comprises a first cascode transistor, a second cascode transistor, a first feedback circuit, a second feedback circuit, and a comparator. The drain of the first cascode transistor is connected directly to a first voltage source. The gate of the first cascode transistor is connected to the first feedback circuit and a first input of the comparator, and the source of the first cascode transistor is connected to the first feedback circuit and a first column decoder. The drain of the second cascode transistor is connected directly to a second voltage source. The gate of the second cascode transistor is connected to the second feedback circuit and a second input of the comparator, and the source of the second cascode transistor is connected to the second feedback circuit and a second column decoder.

Abstract: A low-current input buffer is disclosed. The buffer uses self-biased N and P channel differential pairs with their outputs tied together. The self-biasing assists in reducing current consumption. The combination of N and P-channel differential pairs results in symmetry across a wide range of reference and supply voltages.

Abstract: The invention relates to analog integrated electronic circuits using differential pairs. The proposal is for a method of automatic correction of offset voltage. The inputs (V1, V2) of the differential circuit are short circuited during a calibration phase distinct from the normal usage phase. A capacitor is charged through the difference of the output currents of the branches of the differential pair in this phase. The voltage at the terminals of the capacitor is compared with at least one threshold. During the normal usage phase following the calibration phase, the result of the comparison is kept in memory. In the normal usage phase, a correction is applied depending on the result kept in memory to a current source of a follower stage upstream of the differential pair.

Abstract: A signal conversion circuit 2 comprises a differential amplifier portion 10 and a source follower portion 20. When differential voltage signals INp and INn are input to a first input terminal 5 and second input terminal 6 respectively, operations occurs either in a mode in which only the differential amplifier portion 10 operates, or a mode in which both the differential amplifier portion 10 and the source follower portion 20 operate, or a mode in which only the source follower portion 20 operates, according to the levels of the differential voltage signals INp and INn. The differential amplifier portion 10 and source follower portion 20 have fewer components compared with a circuit comprising two differential amplifier circuits. By this means, the circuit area can be reduced, and in addition current consumption can be reduced. Also, because the source follower portion 20 performs non-inverting amplification of the differential voltage signals INp and INn, high-speed operation is possible.

Abstract: An integrated circuit comparator includes a pair of differential input transistors having gate terminals configured to receive a pair of differential input signals and a comparator output circuit electrically coupled to the pair of differential input transistors. A pair of differential offset compensation transistors are also provided. This pair of differential offset compensation transistors, which is electrically coupled to the pair of differential input transistors, has gate terminals that are configured to receive a pair of unequal dc offset voltages.

Abstract: The present disclosure relates to a differential signaling circuit including differential signaling circuitry having at least one output and one input, that can operate in multiple mode of operations while using a single, low voltage supply source. Two or more switches are included and configured to selectively couple a supply voltage to the output dependent on a mode of operation of the differential signaling circuitry. The circuit also includes a switch control biasing circuit operatively coupled to at least one of the switches and to the output of the differential signaling circuitry. The switch control biasing circuit provides a switch control biasing voltage to control a state of the switch based on a voltage level of the output. Further, a bulk biasing circuit is included and operatively coupled to the switch. The bulk biasing circuit selectively provides a bulk biasing voltage to the switch based on the voltage level of the output.

Abstract: A semiconductor device includes a reference voltage generating unit configured to produce a reference voltage by dividing a voltage difference between a positive clock terminal and a negative clock terminal, and a logic determination unit configured to determine a logic level of an external signal based on the reference voltage.

Abstract: A low voltage differential signal (LVDS) transmitter with output power control. Internal sensing circuitry monitors output current flow through the termination impedance. When a proper termination impedance is not connected to the output, the resulting improper output current flow (e.g., zero output current when no termination impedance is connected) is detected by the sensing circuitry, which causes the supply current to the output driver circuitry to be reduced. Additionally, further in response to such detection of improper output current flow, the sensing circuitry can cause the output voltage to be limited, e.g., clamped, at a predetermined maximum magnitude.

Abstract: A semiconductor device includes a differential circuit for receiving a differential signal at an input terminal and a detection circuit for outputting a detection signal when a predetermined signal is inputted to the input terminal. The detection circuit detects whether the differential signal becomes outside an electric input standard and outputs the detection signal.

Abstract: An input signal detecting circuit includes a plurality of comparators configured to output a plurality of differential output signals in response to a differential input signal, respectively; and a differential exclusive OR circuit configured to output an exclusive OR resultant signal from the plurality of differential output signals outputted from the plurality of comparators. In at least one of the plurality of comparators, a DC operation voltage is changed in response to a control signal supplied to the comparator.

Abstract: An interface such a PCI-E interface may comprise a transmitter and a compensation circuit. In one embodiment, the transmitter may comprise a transmit driver, which may use a push-pull configuration. The transmit driver may require stable voltages such as (Vdd/2+0.25) and (Vdd/2?0.25) Volts. The compensation circuit may comprise a voltage generator circuit and a dummy driver circuit. The dummy driver may be a replica of the transmit driver. A correction module may generate correction factors based on the deviation of the voltages generated by the dummy driver from the voltages generated by the voltage generator. The voltages provided to the transmit driver are corrected based on the correction factors to compensate for the deviation.

Abstract: A differential amplifier includes an amplification unit and a feedback unit. The amplification unit amplifies a voltage difference between a first input signal and a second input signal and outputs a first output signal and a second output signal. The feedback unit amplifies a voltage difference between a first feedback signal based on the first output signal and a second feedback signal based on the second output signal.

Abstract: An input circuit is disclosed. The input circuit can include a cross voltage generating block that can be configured to perform charge-sharing on a pair of input signals whose phases are opposite to each other and generate a cross voltage, and an input buffer block that can be configured to buffer the pair of input signals at a voltage level corresponding to a voltage level of the cross voltage and generate an output signal.

Abstract: A signal history controlled slew-rate transmission method and bus interface transmitter provide an improved channel equalization mechanism having low complexity. A variable slew-rate feed-forward pre-emphasis circuit changes the slew rate of the applied pre-emphasis in conformity with the history of the transmitted signal. The pre-emphasis circuit may be implemented by a pair of current sources supplying the output of the transmitter, and having differing current values. The current sources are controlled such that upon a signal value change, a high slew rate is provided and when the signal value does not change for two consecutive signal periods, the slew rate is reduced. A current source having a controlled magnitude may be employed to provide a slew rate that changes over time and is continuously reduced until another transmission value change occurs.

Abstract: Disclosed is a high-frequency signal detector circuit including a diode detector circuit for detecting an input signal by diode detection; a differential-input/differential output amplifier with a common mode feedback circuit, the amplifier including a differential amplifying circuit for differentially receiving outputs of the diode detector circuit and outputting a differential output signal, and a common mode feedback circuit for controlling the differential amplifying circuit in such a manner that a voltage corresponding to a mid-point of the differential output signal from the differential amplifying circuit will take on a voltage identical with a prescribed voltage; and a differential-input/single-ended output amplifier for receiving the differential output signal of the differential amplifying circuit and outputting a single-ended output signal.

Abstract: An amplitude detection circuit using a sinusoidal input signal inputs to produce a digital output (a one or zero) is described. The circuit uses an input field effect transistor (FET) with a gate load coupled to a gate of the input FET. A drain load may be coupled to a drain of the input FET. A source load may be coupled to a source of the input FET. A controllable variable current generator provides a current to the source of the input FET, biasing the source of the input FET to a reference voltage. An input signal conductor may be coupled to the gate of the input FET. Other embodiments are described.

Abstract: A low-current input buffer is disclosed. The buffer uses self-biased N and P channel differential pairs with their outputs tied together. The self-biasing assists in reducing current consumption. The combination of N and P-channel differential pairs results in symmetry across a wide range of reference and supply voltages.

Abstract: A differential threshold voltage level detection circuit receives a differential voltage pair as an input, applying each component of the differential pair to an individual voltage shifting circuit. Each voltage shifting circuit is configured with a regulated current producing a shifted and a non-shifted version in-phase. For a shifted set of output differential voltages, the shift magnitude is proportional to the current entering a shifting circuit and is configured to be less than a peak-to-peak magnitude of the differential voltage to be detected. A current mirror within the detector contains a current reference configured to produce a current to be passed through a voltage generator. The current magnitude is sufficient to generate a regulated voltage output to the two current regulating devices that supply the voltage shifting circuits. An overlap detector receiving both differential voltage pairs produces a signal indicating an input is at a detection threshold.

Abstract: A signal conversion circuit 2 comprises a differential amplifier portion 10 and a source follower portion 20. When differential voltage signals INp and INn are input to a first input terminal 5 and second input terminal 6 respectively, operations occurs either in a mode in which only the differential amplifier portion 10 operates, or a mode in which both the differential amplifier portion 10 and the source follower portion 20 operate, or a mode in which only the source follower portion 20 operates, according to the levels of the differential voltage signals INp and INn. The differential amplifier portion 10 and source follower portion 20 have fewer components compared with a circuit comprising two differential amplifier circuits. By this means, the circuit area can be reduced, and in addition current consumption can be reduced. Also, because the source follower portion 20 performs non-inverting amplification of the differential voltage signals INp and INn, high-speed operation is possible.

Abstract: A switching matrix has a first number of inputs and a second number of outputs as well as a conductor arrangement and controllable switching elements by means of which the inputs can be connected with the outputs. The controllable switching elements are fashioned such that at least two independent control signals are required to trigger a switching event.

Abstract: In a comparator, a differential amplifier has a pair of transistors receiving a signal to be compared for differential amplification, and a current mirror load circuit for outputting a differential output signal in accordance with the relationship in magnitude of the signal to be compared. A latch circuit has inversion amplifiers for amplifying the differential output signal. One inversion amplifier has its input interconnected to an output of the other inversion amplifier and vice versa. The comparator still further includes a transistor for equalizing signals of the differential amplifier, a transistor for enabling the inversion amplifiers to be active, and a constant current source for reducing a current flowing from a supply voltage to the ground when the inversion amplifiers are active.

Abstract: The invention relates to current switches using a differential pair of transistors and being able to operate under a low supply voltage Vcc. According to the invention, provision is made for the current switch to include two differential pairs of two transistors each (T1, T1b; T2, T2b), cascaded together, the second pair (T2, T2b) having complementary current outputs (H, Hb) that flip according to the states of the inputs (E, Eb). The first pair (T1, T1b) is connected to a ground (GND) through a current source, supplying a current of value Io and comprising a transistor (Ts1) biased by a voltage Vbias, and it is supplied by a voltage equal to N·Vbe+Vbias, where N is a whole number (preferably equal to 1) and Vbe is the base-emitter voltage of the transistor (Ts1). The second pair (T2, T2b) is connected to ground directly through a resistance (R2). The invention can be applied to the on-off control of sample-and-hold circuits, multiplexers, fast low-voltage logic circuits, etc.

Abstract: A comparator circuit includes a first comparator comparing an input signal to a first comparison value and generating a first determination signal, a second comparator comparing the input signal to a second comparison value different from the first comparison value and generating a second determination signal, and an output selecting circuit selecting a signal generated first from the first determination signal and the second determination signal, and outputting the selected signal as a determination signal.

Abstract: In general, in one aspect, the disclosure describes an apparatus that included a reference generator to receive a differential input signal and generate reference voltages having same common mode as the differential input signal. A replica bias generator is used to generate a bias signal based on the reference voltages. A comparator is used to compare the input signals to threshold voltages that are based at least in part on the bias signal.

Abstract: A fast, accurate, low offset comparator may be configured with multiple gain stages. A low gain, low input impedance, and fully differential common-gate amplifier may be configured as a first stage in the multi-stage comparator, providing a wide bandwidth for small power consumption. The inputs of the comparator may comprise a pair of differential inputs at respective source terminals of gate-coupled metal oxide semiconductor (MOS) devices configured in the input stage of the common-gate amplifier. A pair of differential outputs of the first stage may be coupled to a pair of differential inputs of a second stage, which may be a differential input current-mirror amplifier that may perform differential to single-ended conversion.

Abstract: A receiving circuit is provided for receiving a data signal and a clock signal, which are RSDS signals, and outputting an output data signal to a data driver. The receiving circuit includes a data comparator, a data intermediate circuit, a clock comparator, a clock intermediate, and a flip-flop. The data comparator, driven with a data bias current, receives the data signal, and outputs a compared data signal. The clock comparator, driven with a clock bias current, receives the clock signal, and outputs a compared clock signal. The flip-flop receives the compared data signal via the data intermediate circuit and the compared clock signal via the clock intermediate circuit. The phase difference between the compared data signal and the compared clock signal is improved by adjusting the data and the clock bias currents.

Abstract: Method and apparatus are provided for fast rail-to-rail voltage comparison. A rail-to-rail voltage comparator for indicating one of two states with an output signal in response to an input signal is provided comprising an input stage having an input configured to receive the input signal and having an output, and an amplification circuit having an input coupled to the output of the input stage. The input stage comprises a first differential amplifier having a first input-voltage range and configured to produce a first current based on the input signal, a second differential amplifier having a second input-voltage range and configured to produce a second current based on the input signal, and a summing circuit having a first input coupled to the first differential amplifier and having a second input coupled to the second differential amplifier. The first input-voltage range overlaps the second input-voltage range.

Abstract: A voltage comparator where the difference of currents from transistors is converted into voltage, which is amplified and conducted to a gate terminal of a switching transistor. A source of a limiting transistor is connected to the gate terminal. The voltage at the gate terminal when the switching transistor is quiescent is equal to a value between eight and nine tenths of the switching voltage at the gate of the transistor, at which voltage the transistor triggers a switching in the output stage. A response to an input voltage change at one direction of the sign reversal of the difference of the input voltages is fast. The voltage comparator is robust and reliable with regard to temperature variations.

Abstract: Circuits that operate with power supplies of less than 1 Volt are presented. More particularly, circuits that operate with supply voltages near or lower than the threshold voltage of the transistors in those circuits are presented. Various circuits embodiments such as operational transconductance amplifiers (1101, 1102, 1103), biasing circuits, integrators (1113, 1123, 1133), continuous-time sigma delta modulators, track-and-hold circuits, and others are presented. The techniques and circuits can be used in a wide range of applications and various transistors from metal-oxide-semiconductor to bipolar junction transistors may implement the techniques presented herein.

Abstract: A method for calculating a tolerable value for simultaneous switching noise in an input/output circuit having a differential input supplied with a power supply voltage. The method includes providing an input/output circuit having a differential input unit with a pulse signal of a predetermined duty ratio, setting a tolerable range for the duty ratio of the output signal of the input/output circuit with respect to the pulse signal, changing the power supply voltage supplied to the differential input unit of the input/output circuit, measuring the duty ratio of the output signal corresponding to the voltage change, comparing the measured duty ratio with the tolerable range, and calculating a tolerable value for the simultaneous switching noise.