Abstract: A pulse generation circuit has: an edge detector detecting a pulse edge in an input signal to generate edge detection signals; a clock generator generating a clock signal according to the edge detection signals; a frequency divider dividing the frequency of the clock signal to generate a frequency-divided clock signal; an input pad for receiving a test mode switch signal from a tester; and an output pad for outputting the frequency-divided clock signal to the tester. The edge detector can generate the edge detection signals by detecting a pulse edge not in the input signal but in the clock signal or in the inverted clock signal obtained by inverting the logic level of the clock signal when the test mode switch signal is being fed in. The signal delay time in the edge detector is adjustable according to the period of the frequency-divided clock signal as measured by the tester.

Abstract: An example method includes storing a peak voltage level, a valley voltage level, and a frequency of a signal that corresponds to an alternating current (AC) signal across a capacitor; periodically determining whether a current peak voltage level of the signal is different than the stored peak voltage level of the signal or a current valley voltage level of the signal is different than the stored valley voltage level of the signal; determining, based on whether the current peak voltage level of the signal is different than the stored peak voltage level or the current valley voltage level of the signal is different than the stored valley voltage level, whether the AC signal has been removed from the capacitor; and in response to determining that the AC signal has been removed from the capacitor, discharging the capacitor.

Abstract: The present disclosure provides a level shifter including: a level shifter section that is driven by a first power source voltage, and that, in accordance with switching of an input signal of a voltage lower than the first power source voltage, switches an output signal that has been level-shifted, from the first power source voltage to a voltage lower than the first power source voltage; and a threshold voltage changing circuit that, in accordance with a switching direction of the input signal, changes a threshold voltage of the input signal for switching the output signal.

Abstract: In order to transfer a signal for driving a high-side semiconductor power switch, a signal transfer device includes a transmitting circuit, a receiving circuit, and an insulating transformer provided between the transmitting circuit and the receiving circuit. In the insulating transformer, a secondary side of a set transformer part and a secondary side of a reset transformer part are magnetically coupled. The magnetic coupling direction is formed so that a secondary-side terminal of the transformer part and a secondary-side terminal of the transformer part can have polarities reverse to each other. Thus, it is possible to provide a signal transfer device for transferring a signal through an insulating transformer, in which occurrence of common-mode noise can be suppressed and a countermeasure circuit against the noise can be simplified.

Abstract: A low-voltage to high-voltage level shifter circuit includes an input circuit, a voltage shifting circuit, and an output circuit. The input circuit is configured to receive an input signal having a voltage range between a first voltage and a ground voltage, and to provide an inverted input signal and a delayed version of the inverted input signal. The voltage shifting circuit is coupled to the input circuit and is configured to receive the input signal, the inverted input signal, and the delayed version of the inverted input signal. The voltage shifting circuit is configured to provide an internal signal having a voltage range between a second voltage and the ground voltage, the second voltage being higher than the first voltage. The output circuit provides an output voltage in the high-voltage range for the corresponding input voltage in the low-voltage range.

Abstract: A method for detecting a hysteresis characteristic of a comparator, include: causing a controller to control an offset adjuster configured to adjust an offset amount of the comparator; causing the controller to change the offset amount from a first value toward a second value and detect a third value when a logic level of a signal output from the comparator is changed; causing the controller to change the offset amount from the second value toward the first value and detect a fourth value when the logic level is changed; and causing the controller to detect the hysteresis characteristic of the comparator based on a first difference between the third value and the fourth value.

Abstract: A measuring device for triggering a test signal with a superposed noise signal includes a trigger unit, which is connected to a recording unit, where the test signal with respectively superposed noise signal is supplied to both. The trigger unit outputs a trigger signal to the recording unit as soon as the test signal with superposed noise signal has completely run through a hysteresis range. The trigger unit is connected to a hysteresis adjustment unit, where the hysteresis adjustment unit specifies a hysteresis range to the trigger unit, and where the hysteresis range specified by the hysteresis adjustment unit is adjustable.

Abstract: A quantizer for an analog to digital converter has an input for receiving an analog input signal. A detector senses a common mode voltage component of the input signal. A reference voltage source produces a plurality of reference voltages. A voltage source biases the reference voltage source in response to the sensed common mode voltage component. Therefore, the common mode voltage in the input signal establishes the common mode voltage of the reference voltage source. A plurality of comparators are connected to the reference voltage source, wherein each of the plurality of comparators compares the input signal to one of the plurality of reference voltages and produces a output bit denoting a result of the comparing.

Abstract: An adaptive amplification circuit is provided, which includes an operational amplifier comprising a variable bias current source for providing a variable bias current for the operational amplifier, an equivalent circuit of the operational amplifier for receiving an input voltage and generating an output voltage according to the input voltage, and a bias control unit for generating a bias control signal to the variable bias current source according to the output voltage so as to adjust the variable bias current.

Abstract: Systems and methods for low-power voltage tamper detection are described. In some embodiments, an integrated circuit may include source-follower circuitry configured to produce a scaled down supply voltage. The integrated circuit may also include undervoltage detection circuitry coupled to the source-follower circuitry, the undervoltage detection circuitry configured to output a first signal having a first logic value if the scaled down supply voltage is greater than a low threshold voltage or a second logic value if the scaled down supply voltage is smaller than the low threshold voltage. Additionally or alternatively, the integrated circuit may include overvoltage detection circuitry coupled to the source-follower circuitry, the overvoltage detection circuitry configured to output a second signal having the first logic value if the scaled down supply voltage is smaller than a high threshold voltage or the second logic value if the scaled down supply voltage is greater than the high threshold voltage.

Abstract: A low output voltage driver circuit for a light-emitting device is provided according to exemplary embodiments of the present invention. Also, an offset voltage cancellation and/or level shifter is incorporated into the driver circuit to increase the accuracy of the driving current. In addition, an error detection circuit and method are employed in order to adaptively detect the minimum output voltage of the inventive driver circuit.

Abstract: In accordance with these and other embodiments of the present disclosure, an apparatus and a method may include receiving a first input configured to indicate an output voltage of an output node of a switched output stage comprising a pull-down driver device coupled at its non-gate terminals between a ground voltage and the output node and a pull-up driver device coupled at its non-gate terminals between a supply voltage and the output node. The method may also include receiving a second input configured to indicate a gate voltage of a gate terminal of a first one of the pull-up driver device and the pull-down driver device. The method may further include detecting direction of an output current flowing into or out of the output node based on the first input and the second input.

Abstract: A ping pong comparator voltage monitoring circuit which includes first and second comparators having inputs connected to a voltage Vin to be monitored, and second inputs connected to first and second nodes, respectively. A multiplexer alternately couples the first and second comparator outputs to an output in response to a periodic control signal. A ground-referenced voltage Vref1 is provided at a third node and a voltage Vref2 referenced to Vref1 is at a fourth node. A hysteresis hyst1 is switchably connected between the third and first nodes, and a hysteresis hyst2 is switchably connected between the fourth and second nodes. Hyst1 and hyst2 are switched in when the mux output toggles due to a rising Vin, and are switched out when the mux output toggles due to a falling Vin.

Abstract: A switching circuit includes a first input stage having an input for receiving a first input signal, an output, and a power terminal for receiving an increasing analog current, a second input stage having an input for receiving a second input signal, an output, and a power terminal for receiving a decreasing analog current, and an output node coupled to the outputs of the first input stage and the second input stage for providing a switched output signal. An output stage is coupled between the first and second input stages and the output node. The first and second input stages are operational amplifiers.

Abstract: A circuit includes a comparator, a programmable current source, and a control circuit. The comparator is operable to compare an internal supply voltage of the circuit to a reference voltage. The programmable current source is operable to supply a first current for the reference voltage. The control circuit is operable to control the first current through the programmable current source based on an output signal of the comparator.

Abstract: Embodiments of the present invention include an electronic circuit that reduces stress on a transistor. In one embodiment, the electronic circuit comprises a transistor and a reference generator circuit. The transistor may be a metal oxide semiconductor (MOS) transistor, for example. The MOS transistor has a gate terminal to receive an input voltage. The reference generator circuit selectively couples first and second reference voltages to a source terminal of the MOS transistor. The reference generator circuit senses the input voltage and provides the first reference voltage to the source terminal of the MOS transistor if the input voltage is greater than a threshold and the second reference voltage is coupled to the source terminal of the first MOS transistor if the input voltage is less than a threshold.

Abstract: An input buffer with a reduced sensitivity to an externally generated reference voltage includes: a first input coupled between a first load and ground, the first input being an externally generated reference voltage; a second input coupled between a second load and ground, for generating an output; and a third input coupled in parallel to the first input, the third input being an internally generated reference voltage. The output switches between high and low or vice versa when the second input exceeds a switching point which is an average of the first input and the third input according to the relative size of the first input and the third input.

Abstract: A low output voltage driver circuit for a light-emitting device is provided according to exemplary embodiments of the present invention. Also, an offset voltage cancellation and/or level shifter is incorporated into the driver circuit to increase the accuracy of the driving current. In addition, an error detection circuit and method are employed in order to adaptively detect the minimum output voltage of the inventive driver circuit.

Abstract: Described herein is a method and apparatus to wake-up analog bias signals with minimum delay. The apparatus comprises a first logic unit operable to adjust a signal level of a gated bias signal via a first predetermined signal in response to a power-down event; a comparator operable to compare the gated bias signal with an un-gated bias signal, and operable to generate an output signal indicating the comparison result; and a self-timed logic unit coupled to the comparator and operable to generate a wake-up signal in response to an end of the power-down event and the output signal.

Abstract: A device includes a comparator, and a selection circuit coupled to the inputs of the comparator. The selection circuit receives reference voltages and a variable voltage. In a normal operation mode, the selection circuit provides the variable voltage and a selected reference voltage to the comparator and the comparator provides an indication based on the variable voltage. In a test mode, the selection circuit provides a first selected reference voltage and a second selected reference voltage to the comparator for determining a switching offset voltage of the comparator.

Abstract: A half-power buffer amplifier is disclosed. A buffer stage includes a first-half buffer stage and a second-half buffer stage, wherein an output of the first-half buffer stage is controllably fed back to a rail-to-rail differential amplifier, and an output of the second-half buffer stage is controllably fed back to the rail-to-rail differential amplifier. The switch network controls the connection between the outputs of the buffer stage and an output node of the half-power buffer amplifier in a manner such that a same pixel, with respect to different frames, of a display panel is driven by the same rail-to-rail differential amplifier. In one embodiment, the rail-to-rail differential amplifier and the buffer stage comprise half-power transistors operated within and powered by half of a full range spanning from power to ground.

Abstract: A circuit includes a comparator, a programmable current source, and a control circuit. The comparator is operable to compare an internal supply voltage of the circuit to a reference voltage. The programmable current source is operable to supply a first current for the reference voltage. The control circuit is operable to control the first current through the programmable current source based on an output signal of the comparator.

Abstract: A circuit includes a comparator, a resistor divider, a control circuit, a multiplexer, and a programmable gain amplifier. The comparator is operable to measure an internal voltage of the circuit based on a selected reference voltage. The resistor divider is operable to generate reference voltages. The control circuit is operable to generate a select signal based on an output signal of the comparator. The multiplexer is operable to select one of the reference voltages from the resistor divider as the selected reference voltage based on the select signal. The programmable gain amplifier is configurable to generate a compensation voltage to compensate for an offset voltage of the comparator. The compensation voltage is provided to an input of the comparator.

Abstract: An oscillator that increases the accuracy of an output frequency, without using a charge pump, has an oscillation circuit, first and second voltage supply circuits, and a calibration value generation circuit. The first voltage supply circuit includes a resistor and a capacitor, the resistance and capacitance of which are determined so that a first voltage reaches a reference voltage within a reference time. The second voltage supply circuit includes first and second switching means, which perform switching when receiving pulse signals corresponding to the frequency of the oscillation circuit to raise the second voltage. A calibration value generation circuit provides the oscillation circuit with a calibration value that lowers the frequency when the second voltage reaches the reference voltage before the first voltage and raises the frequency when the second voltage reaches the reference voltage after the first voltage.

Abstract: A half-power buffer amplifier includes a buffer stage having a first-half buffer stage and a second-half buffer stage. An output of the first-half buffer stage is controllably fed back to a rail-to-rail differential amplifier, and an output of the second-half buffer stage is controllably fed back to the rail-to-rail differential amplifier. A switch network controls the connection between the outputs of the buffer stage and an output node of the half-power buffer amplifier in a manner such that a same pixel, with respect to different frames, of a display panel is driven by the same rail-to-rail differential amplifier.

Abstract: Circuitry includes a voltage-controlled switch having a transmitter input, a receiver input, and an output that connects to one of the transmitter input and the receiver input. Passive components form a low-pass filter that is electrically connected to the transmitter input. The passive components are part of a multilayer ceramic passive module that includes a base body made of superimposed dielectric layers and electrically conductive layers. The voltage-controlled switch is on an upper portion or a lower portion of the base body.

Abstract: In a comparator circuit having a differential amplifier, which makes a logical judgment by comparing an input voltage with a reference voltage, generates and outputs a resulting output voltage thereof, a current source generates and supplies a bias current of a predetermined minute current to the differential amplifier, and a first inverter circuit inverts a differential voltage from the differential amplifier. An adaptive bias current generator circuit detects the bias current of the current source, and a through current of the first inverter circuit. The adaptive bias current generator circuit generates and supplies an adaptive bias current for executing adaptive bias current control to the differential amplifier to allow the differential amplifier to operate with the bias current upon no logical judgment, and to allow the differential amplifier to operate by using the adaptive bias current obtained by increasing the bias current upon logical judgment.

Abstract: A circuit includes a comparator, a resistor divider, a control circuit, a multiplexer, and a programmable gain amplifier. The comparator is operable to measure an internal voltage of the circuit based on a selected reference voltage. The resistor divider is operable to generate reference voltages. The control circuit is operable to generate a select signal based on an output signal of the comparator. The multiplexer is operable to select one of the reference voltages from the resistor divider as the selected reference voltage based on the select signal. The programmable gain amplifier is configurable to generate a compensation voltage to compensate for an offset voltage of the comparator. The compensation voltage is provided to an input of the comparator.

Abstract: A circuit can include a comparator, a resistor divider, a control circuit, and a multiplexer. The comparator compares an internal supply voltage of the circuit to a selected reference voltage. The resistor divider generates reference voltages. The control circuit receives an output signal of the comparator and generates a select signal. The multiplexer transmits one of the reference voltages from the resistor divider to the comparator as the selected reference voltage in response to the select signal.

Abstract: An asymmetric DFE receiver circuit. The receiver circuit includes a voltage measuring unit configured to determine a signal voltage of a received signal, and a comparator unit configured to calculate a difference between the signal voltage and an evaluation threshold voltage and to compare the difference to the value of a midpoint voltage. The comparator unit is configured to generate a first control signal if the difference is greater than the midpoint voltage value or a second control signal if the signal voltage is less than the midpoint voltage value. The receiver includes an adjustment circuit configured to adjust the evaluation threshold voltage toward the signal voltage if the first control signal is generated and away from the signal voltage if the second control signal is generated. The rates of adjustment may vary depending upon whether the received signal is a transition bit or a non-transition bit.

Abstract: In general, a method includes comparing a first input signal with a second input signal to produce an output signal. The first input signal corresponds to an amount of light detected by a sensor, and the second input signal corresponds to an aggregated value of the output signal. The method may also include aggregating the output signal in a digital accumulator and converting a digital signal from an output of the digital accumulator to an analog signal.

Abstract: A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However, measurement of very high frequency signals, off-chip, and in a laboratory environment can be very difficult and present numerous problems. To combat problems associated with making off-chip measurements and adjustments of signal duty cycles, comparisons are made between input signals and divided input signals that allow for easy measurement and adjustment of on-chip signals, including clocking signals.

Abstract: An analog signal processing device including a voltage selector selecting a given comparison reference voltage from plural comparison reference voltages, an arithmetic unit arithmetically processing the given comparison reference voltage and an analog input signal, a comparator which has at least one or more judgment points for the plural comparison reference voltages and to which an output of the arithmetic unit is inputted, and a coupling controller controlling connections between the arithmetic unit and the comparator, wherein the arithmetic unit comprises correctable first signal processors, and the number of the first signal processors is more than is necessary for the plural comparison reference voltages by M or larger, and when a set of N of first signal processors are in a correction operation, the coupling controller connects first signal processors which are not in the correction operation in the arithmetic unit to the comparator.

Abstract: Disclosed herein is a voltage detection circuit including: a voltage detection section; a first voltage determination section; and a second voltage determination section.

Abstract: An improved regenerative clocked sampling circuit is described which uses a single clocking signal to switch the circuit between a tracking phase in which the state tracks the input signal, and a bistable phase during which the state rapidly approaches one of two states dependant on the input signal. The same clock signal also isolates the bistable circuit from the input signal source. In a preferred embodiment, these two actions are performed by the same transmission gate or gates connecting the input to the potentially bistable circuit.

Abstract: Disclosed is a signal output circuit comprising: a first transistor of an emitter follower configuration, which receives an input signal; a second transistor of an emitter follower configuration, which receives the input signal, and has an output connected to an external load (106); a comparator circuit which has an input pair connected via resistors to emitters of the first and the second transistors; a first current mirror circuit which has an input connected to an output of a first current source transistor and an output connected to an emitter of the first transistor; and a second current mirror circuit which has an input connected to a connection node of an output of a second current source transistor and an output of the comparator circuit, and has an output connected to an emitter of the second transistor.

Abstract: A random clock generator for a spread spectrum modulating device includes a random number generator for generating a plurality of random number signals according to a first square wave signal and a control signal, a reference wave generator coupled to the random number generator for generating a triangular signal and a second square wave signal according to the plurality of random number signals, and a trigger signal generator coupled to the random number generator and the reference wave generator, for generating the first square wave signal according to the second square wave signal.

Abstract: There is provided a current detection circuit capable of preventing an excessive voltage from being applied to an input terminal of a differential amplifier, without resulting in reduction in current detection accuracy. The current detection circuit includes a power MOSFET 1 (a first semiconductor switching device), a sense MOSFET 2 (a second semiconductor switching device), a differential amplifier 3, a Zener diode 33 (a first voltage clamp device), a Zener diode 34 (a second voltage clamp device), an MOSFET 6 (a variable resistance device), a depletion type MOSFET 31 (a first MOSFET), and a depletion type MOSFET 32 (a second MOSFET).

Abstract: An impedance buffer has a single comparator with a first input and a second input. A first leg has a first pull-up array in series with a reference resistor. The first input of the single comparator is electrically coupled to a node between the first pull up array and the reference resistor. A second leg has a second pull-up array in series with a pull-down array. The second leg is coupled through a switch to the second input of the single comparator.

Abstract: To detect the peaks level of an incoming signal, the difference between the voltage level of the incoming signal and a voltage developed across a capacitor is amplified. The amplified difference signal is applied to a transconductor adapted to vary its output current in response to changes in the amplified difference signal. The variations in the current generated by the transconductor are used to change a current flowing through a current mirror that charges the capacitor. The voltage developed across the capacitor represents the detected peak. The capacitor is discharged to a predefined voltage level during the reset periods. A second amplifier receiving the capacitor voltage is optionally used to develop a voltage across a second capacitor that is not reset and thus carries only the detected peak levels.

Abstract: An input stage of an integrated circuit, includes a comparator for comparing the voltage of an input signal of the input stage with a reference voltage, and supplying a binary output signal the value of which depends on the result of the comparison of the input signal with the reference voltage. The input stage comprises a feedback circuit measuring a parameter representative of the operation of the comparator, and raising the reference voltage while the measured parameter reveals a faulty operation of the comparator.

Abstract: A circuit and method for producing an output voltage that replicates an input voltage. A circuit comprises an amplifier stage configured to amplify a difference between an input voltage and a feedback voltage. An output stage is configured to produce an output voltage equal to the input voltage. The output stage configured to be driven by the difference between the input voltage and the feedback voltage. The output stage further comprises a main supply current path configured to provide a first current from a main supply source, the first current providing at least a portion of the output voltage, and a current management circuit configured to provide a second current from an auxiliary supply source, the second current providing any remaining portion of the output voltage not provided by the first current.

Abstract: In one embodiment, a circuit device that performs a certain processing operation with respect to an input signal by referring to a reference voltage and outputs the result is caused to have a function of switching the reference voltage, whereby a circuit device from which a stable output can be obtained is disclosed. The circuit device includes a comparator and a reference voltage setting circuit. The comparator compares an input voltage fed from outside with a reference voltage selected from a reference voltage set including a plurality of voltage values that are different from one another.

Abstract: A power semiconductor drive circuit device includes: an electronic control device generating a control input signal; a signal transfer circuit device having a main path and a self-diagnosis functional block; and a power semiconductor driven by the control output signal from the signal transfer circuit device. The self-diagnosis functional block includes: a feedback pulse transmitter circuit; a second signal transfer circuit; and a second receiver circuit. The second receiver circuit compares the control output signal with the control input signal so as to find out whether the control output signal is matched or unmatched with the control input signal, and then outputs a result to a comparison signal output terminal. A signal outputted to the comparison signal output terminal is transferred to the electronic control device.

Abstract: The PD converts the light into a current signal and supplies the converted a current signal to a TIA and a light intensity measuring unit. The TIA converts the current signal into a voltage signal. The CDR circuit identifies whether the voltage signal is 1 data or 0 data for reproduction. The counter counts the 1 data and 0 data, calculates their ratio. The control unit refers to light intensity data from the light intensity measuring unit and a ROM, acquires an optimum ratio, and determines whether the ratio supplied from the counter is the optimum ratio. When the ratio is not the optimum one, the control unit controls the threshold voltage setting unit to set the threshold voltage so that the ratio is the optimum one.

Abstract: In a high-speed serial link, an eye finder diagnostic circuit has improved performance by being on-chip with the existing capture latch(es) of a receive equalizer. The eye finder circuit employs an additional capture latch with its input tied to the same input node as the existing capture latch(es) of a receive equalizer. The additional capture latch has a clock input and reference voltage input. The clock input is adjusted through a phase interpolator (or variable delay line) while the reference voltage input is adjusted by a voltage generator. A digital post processing circuit then compares the output of the additional capture latch with the output of the other existing capture latch(es), in order to determine the receive eye opening. The horizontal eye opening is measured by changing the phase of the additional capture latch through the phase interpolator, while the vertical eye opening is measured by changing the reference voltage of the voltage generator of the additional capture latch.

Abstract: A voltage detecting circuit included in a battery device includes an input voltage comparing circuit that compares a first threshold value voltage or a second threshold value voltage lower than the first threshold value voltage with an input voltage to control the opening and closing of an output switching element, and a threshold value voltage setting circuit that compares a third threshold value voltage lower than the second threshold value voltage with the input voltage and, when the input voltage changes from a low voltage to a high voltage and intersects the third threshold value voltage, outputs a pulse for a predetermined period thereafter so that the second threshold value is selected in the input voltage comparing circuit. As a result, when the input voltage increases from the ground potential, the second threshold value is compared with the input voltage in the input voltage comparing circuit.

Abstract: A circuit can include a comparator, a resistor divider, a control circuit, and a multiplexer. The comparator compares an internal supply voltage of the circuit to a selected reference voltage. The resistor divider generates reference voltages. The control circuit receives an output signal of the comparator and generates a select signal. The multiplexer transmits one of the reference voltages from the resistor divider to the comparator as the selected reference voltage in response to the select signal.

Abstract: A correlated double sampling circuit includes a first capacitor and a comparator. The first capacitor may be configured to receive a ramp signal via a first end. The comparator may be configured to receive the ramp signal and an output signal of a unit pixel circuit via a differential amplifier included in the comparator. The comparator may be also be configured to compare the output signal with the ramp signal and may be configured to directly receive the output signal of the unit pixel circuit at a first input terminal of the differential amplifier. A second input terminal of the differential amplifier is connected to a second end of the first capacitor.

Abstract: Precision amplitude detection circuitry without pattern dependencies is provided that includes rectifier circuitry to output a rectified voltage signal and delay circuitry to send one or more delayed or phase-shifted versions of a differential signal input to the rectifier circuitry. The delayed versions of the differential signal input may be delayed in order to reduce or eliminate the dips in the input seen by the rectifier. This may help correct for low rectified voltage levels. The signal amplitude detection circuitry of the present invention may be incorporated on the input pin of any programmable logic resource and may be included in communication circuitry of a PLD. The precision amplitude detection circuitry may operate in the Gbps (gigabit per second) range.