Input Signal Compared To Reference Derived Therefrom Patents (Class 327/72)
  • Patent number: 10684314
    Abstract: Provided is a system for testing a reference voltage circuit applicable to a reference voltage circuit. The reference voltage circuit includes a bandgap reference voltage circuit, switching elements, a first capacitor, a second capacitor and a comparator. The testing system includes a control logic unit. In a test mode, the control logic unit adjusts an allowable value of the comparator to speed up the suitability test of the switching elements.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: June 16, 2020
    Assignee: Nuvoton Technology Corporation
    Inventors: Te-Ming Tseng, Yeh-Tai Hung, Wen-Yi Li
  • Patent number: 10627838
    Abstract: A system includes a monitored component and a comparator configured to compare a sense voltage from the monitored component with a reference voltage. The system also includes an adaptive input clamping circuit configured to limit the sense voltage input to the comparator to below an upper threshold voltage.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: April 21, 2020
    Assignee: Texas Instruments Incorporated
    Inventor: Mitsuyori Saito
  • Patent number: 10361664
    Abstract: A power amplifier circuit is capable of restraining uneven temperature distribution among a plurality of unit transistors while restraining the deterioration of the characteristics of the power amplifier circuit. The power amplifier circuit includes: a first transistor group which includes a plurality of unit transistors and which amplifies an input signal and outputs an amplified signal; a bias circuit which supplies a bias current or a bias voltage to a base or a gate of each unit transistor of the first transistor group; a plurality of first resistive elements, each of which is connected between the base or the gate of each unit transistor of the first transistor group and an output of the bias circuit; and a plurality of second resistive elements, each of which is connected between an emitter or a source of each unit transistor of the first transistor group and a reference potential.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: July 23, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Toshiki Matsui, Kenji Sasaki, Fumio Harima
  • Patent number: 10250418
    Abstract: An EHF receiver that determines an initial slicing voltage level and dynamically adjusts the slicing voltage level and/or amplifier gain levels to account for characteristics of the received EHF electromagnetic data signal. The architecture includes an amplifier, detector, adaptive signal slicer, and controller. The detector includes a main detector and replica detector that convert the received EHF electromagnetic data signal into a baseband signal and a reference signal. The controller uses the baseband signal and reference signal to determine an initial slicing voltage level, and dynamically adjust the slicing voltage level and the gain settings of the amplifier to compensate for changing signal conditions.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: April 2, 2019
    Assignee: Keyssa Systems, Inc.
    Inventors: Ian A. Kyles, Norbert Seitz
  • Patent number: 10054648
    Abstract: A power source voltage detection apparatus is provided, including a reference voltage generator connected to a differential amplifier via a first transmission line and decreases a power source voltage of a direct current power source to output a power source reference voltage, the first transmission line transmitting the power source reference voltage as a first power source voltage detection voltage; a standard voltage generator connected to the differential amplifier via a second transmission line and outputs a predetermined standard voltage, the second transmission line transmitting the standard voltage as a second power source voltage detection voltage; the differential amplifier differentially amplifying the first and second power source voltage detection voltages; and an abnormality detector which, based on the first and second power source voltage detection voltages, detects the power source voltage and detects an abnormality of the first transmission line and/or the second transmission line.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: August 21, 2018
    Assignee: KEIHIN CORPORATION
    Inventors: Shugo Ueno, Kazutaka Senoo, Kouji Suzuki
  • Patent number: 9843309
    Abstract: A system for communicating information between circuits is described. A transmit circuit provides pulse-amplitude-modulation (PAM) signals via a communication channel to a receiver. A circuit in the receiver determines digital values from the received signals using a time-varying threshold voltage, which varies during the bit-time. This approach may compensate for inter-symbol interference (ISI) to increase the voltage and timing margins of the system.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: December 12, 2017
    Assignee: Rambus Inc.
    Inventors: Jared L. Zerbe, Brian S. Leibowitz, Qi Lin
  • Patent number: 9832006
    Abstract: In one embodiment, an apparatus includes a clock channel to receive and distribute a clock signal to a plurality of data channels. At least some of the data channels may include: a first sampler to sample data; a second sampler to sample the data; and a deskew calibration circuit to receive first sampled data from the first sampler and second sampled data from the second sampler and generate a local calibration signal for use in the corresponding data channel. The apparatus may further include a global deskew calibration circuit to receive the clock signal from the clock channel, receive the first sampled data and the second sampled data from the plurality of data channels, and generate a global calibration signal for provision to the plurality of data channels. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: November 28, 2017
    Assignee: Intel Corporation
    Inventors: Chenchu Punnarao Bandi, Amit Kumar Srivastava
  • Patent number: 9813050
    Abstract: A comparator circuit's signal range can be enhanced using an input signal attenuation circuit. In an example, a comparator circuit receives an input signal and a reference signal. The input signal can be conditioned by one or both of the attenuation circuit and a conditioning circuit, and a resulting conditioned signal can be presented to a compare element. Under first operating conditions where the input signal is approximately equal to the reference signal, the attenuation circuit can be substantially bypassed and a first resulting conditioned signal can be presented to the compare element. Under second operating conditions where the input signal is substantially greater than the reference signal, the attenuation circuit receives a portion of the input signal and a different second resulting conditioned signal can be presented to the compare element.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: November 7, 2017
    Assignee: Analog Devices, Inc.
    Inventor: Christopher C. McQuilkin
  • Patent number: 9584226
    Abstract: The invention concerns an optical receiver comprising: a photodiode (102) coupled to the input of a trans-impedance amplifier (308) such that the trans-impedance amplifier receives the current (IPD) of the photodiode; a first comparator (112) adapted to compare an output voltage (VOUT) of the trans-impedance amplifier (308) with a threshold voltage (VTH); and a threshold control block (314) for generating the threshold voltage (VTH), wherein the threshold control block (314) comprises at least one capacitor coupled to the output (110) of the trans-impedance amplifier (308) via at least one switch.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: February 28, 2017
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Robert Polster, José Luis Gonzalez Jimenez
  • Patent number: 9548714
    Abstract: A controller and an output filter for a power converter, and a power converter employing at least one of the same. In one embodiment, the controller includes an error amplifier with first and second input terminals coupled to one of an operating characteristic and a reference voltage of the power converter, and a switch configured to couple the first and second input terminals to one of the operating characteristic and the reference voltage as a function of a power conversion mode of the power converter. In one embodiment, the output filter includes an output filter capacitor with a first terminal coupled to a first output terminal of a power converter, and an output filter inductor coupled between a second terminal of the output filter capacitor and a second output terminal of the power converter.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: January 17, 2017
    Assignee: Altera Corporation
    Inventors: Ahmed Mohamed Abou-Alfotouh, Mirmira Ramarao Dwarakanath, Jeffrey Demski
  • Patent number: 9537398
    Abstract: A high voltage generating circuit includes a charge pump circuit and an output voltage control circuit. The charge pump circuit raises a voltage to a high voltage higher than a power supply voltage. The output voltage control circuit controls the voltage to make the raised high voltage to be a predetermined target voltage. The output voltage control circuit includes at least two offset free comparator circuits, or at least one offset free comparator circuit and at least one differential amplifier. The offset free comparator circuit includes a coupling capacitor, a differential amplifier and a plural switch. The coupling capacitor inputs a voltage corresponding to the high voltage. The differential amplifier compares a voltage from the coupling capacitor with a predetermined reference voltage and outputs a comparison result voltage to the charge pump circuit. The switches are connected to the differential amplifier to cancel an offset of the differential amplifier.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: January 3, 2017
    Assignee: Powerchip Technology Corporation
    Inventors: Hideki Arakawa, Tomofumi Kitani
  • Patent number: 9529023
    Abstract: A signal analysis circuit and a signal analysis method thereof are disclosed. The signal analysis circuit includes a peak detector, a subtraction amplifying unit, and a compare unit. The peak detector obtains a peak value of a first voltage signal to generate a second voltage signal. The subtraction amplifying unit generates a compare voltage signal according to the second voltage signal, and amplifies a voltage value difference between the second voltage signal and the compare voltage signal to generate a third voltage signal. A peak-to-peak value of the third voltage signal is larger than a peak-to-peak value of the second voltage signal. The compare unit compares the voltage value of the third voltage signal and the voltage value of the compare voltage signal to generate an output voltage signal. In such a manner, a new signal analysis circuit can be realized.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: December 27, 2016
    Assignee: ASUSTeK COMPUTER INC.
    Inventors: Wei-Chen Tu, Yi-Ming Huang, Ming-Ting Tsai, Hsiang-Jui Hung
  • Patent number: 9525873
    Abstract: An image processing circuit and an image processing method are provided. The image processing circuit comprises a full search engine and a frame rate conversion (FRC) engine. The full search engine executes a full search to generate a sum of sum of absolute difference (SAD) distribution according to the reference image and the current image. The FRC engine analyzes a scene characteristic from the current image according to SAD distribution. The FRC engine adjusts at least one of the control parameters according to the scene characteristic. The FRC engine generates an interpolated image according to the reference image, the current image and the control parameters.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: December 20, 2016
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventors: Yen-Sung Chen, Tsui-Chin Chen, Jian-De Jiang
  • Patent number: 9367385
    Abstract: A receiver path including first, second, third, and fourth comparator modules. The first comparator module is configured to generate, based on a signal received via the receiver path, a first digital output signal indicative of a sum of first data in the received signal and a first error. The second comparator module is configured to generate, based on the signal received via the receiver path, a second digital output signal indicative of a sum of second data in the received signal and a second error. The third comparator module is configured to generate, based on the signal received via the receiver path, a third digital output signal indicative of the first data in the received signal. The fourth comparator module is configured to generate, based on the signal received via the receiver path, a fourth digital output signal indicative of the second data in the received signal.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: June 14, 2016
    Assignee: Marvell World Trade Ltd.
    Inventor: Sasan Cyrusian
  • Patent number: 9325303
    Abstract: The present disclosure illustrates a button detecting circuit and method thereof. The button detecting circuit includes a determining circuit, a voltage selector and a button module. The voltage selector is electrically connected to the determining circuit. The voltage selector has a plurality of candidate voltages arranged in sequence based on magnitudes of the candidate voltages. The button module which is electrically connected to the determining circuit via a single one pin comprises a threshold unit and a button network. The determining circuit receives the candidate voltage outputted from the voltage selector and outputs the candidate voltage to the button module for testing whether the threshold unit will be conducted to find a threshold voltage. The button module generates a scanning current based upon the threshold voltage. The determining circuit senses the scanning current and determines which one of a plurality of buttons disposed in the button network is pressed.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: April 26, 2016
    Assignee: PIXART IMAGING INC.
    Inventors: Cheng Seng Hsu, Jui Te Chiu
  • Patent number: 9294044
    Abstract: A bias circuit according to an embodiment is a bias circuit that supplies a bias voltage to an amplifying element. The bias circuit of the embodiment includes a first current source that has a characteristic of varying an output current with the surrounding temperature variations, and a second current source that has a different output characteristic from the first current source and that can control the output current. The bias circuit of the embodiment also includes a comparator for comparing the output current of the first current source with the output current of the second current source, and a bias supply part that controls the output current of the second current source on the basis of the comparison result of the comparator and supplies a bias voltage to the amplifying element in accordance with the comparison result.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: March 22, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shusuke Kawai, Masahiro Hosoya, Tong Wang, Toshiya Mitomo, Shigehito Saigusa, Tetsuro Itakura
  • Patent number: 9281824
    Abstract: In some embodiments, disclosed is an AC amplitude detector to compare the magnitude of an AC signal against a detector threshold level and to provide an indication as to whether the AC magnitude is larger or smaller than the detector threshold level.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 8, 2016
    Assignee: Intel Corporation
    Inventors: Gennady Goltman, Yongping Fan
  • Patent number: 9213669
    Abstract: Provided is a test apparatus that tests a device under test, comprising a plurality of comparators that each receive a signal under measurement output by the device under test, have a common reference level set therein, and compare a signal level of the signal under measurement to the reference level; and a signal processing section that generates a single result signal based on the plurality of comparison results output by the comparators. Also provided is a test method using the test apparatus.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: December 15, 2015
    Assignee: ADVANTEST CORPORATION
    Inventors: Takahiro Yamaguchi, Masahiro Ishida
  • Patent number: 8988114
    Abstract: Systems and methods for low-power voltage tamper detection are described. In some embodiments, an integrated circuit may include source-follower circuitry configured to produce a scaled down supply voltage. The integrated circuit may also include undervoltage detection circuitry coupled to the source-follower circuitry, the undervoltage detection circuitry configured to output a first signal having a first logic value if the scaled down supply voltage is greater than a low threshold voltage or a second logic value if the scaled down supply voltage is smaller than the low threshold voltage. Additionally or alternatively, the integrated circuit may include overvoltage detection circuitry coupled to the source-follower circuitry, the overvoltage detection circuitry configured to output a second signal having the first logic value if the scaled down supply voltage is smaller than a high threshold voltage or the second logic value if the scaled down supply voltage is greater than the high threshold voltage.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: March 24, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Sanjay K. Wadhwa, Alfredo Olmos, Fabio Duarte De Martin
  • Patent number: 8884654
    Abstract: A peak detector circuit receives an oscillating power supply signal. A capacitor is selectably coupled to the signal and charged to a value corresponding to a peak value of the signal. A switch is then opened to isolate the capacitor. A comparator continually compares the signal with the value stored on the capacitor. When the signal rises to within a selected threshold, relative to the stored value, the comparator produces a command signal to close the switch, again coupling the capacitor to the signal. The peak detector can also include a tracking circuit that controls the capacitor to track the oscillating signal while the switch is closed, a timer circuit configured to close the switch and activate the tracking circuit if more than a selected time passes without production of a command signal, and a circuit configured to control the polarity of a leakage current of the capacitor.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: November 11, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mirko Gravati, Claudio Cantoro
  • Publication number: 20140312934
    Abstract: One embodiment of the present invention relates to a method and apparatus to perform a low power activation of a system by measuring the slope of a digital signal corresponding to a motion sensor measurement value. In one embodiment, a low power activation circuit is coupled to magnetic motion sensor configured to output a magnetic signal proportional to a measured magnetic field. The low power activation circuit may comprise a digital tracking circuit configured to provide a digital signal that tracks the magnetic field and a difference detector configured to detect a difference between a current digital signal and a prior digital signal stored in a digital storage means. If the detected difference is larger than a digital reference level, an activation signal is output to awaken a system from a sleep mode.
    Type: Application
    Filed: July 1, 2014
    Publication date: October 23, 2014
    Inventor: Mario Motz
  • Patent number: 8850097
    Abstract: USB apparatus suitable for interconnection with a USB host having a D? bus coupled to ground via a pull-down resistance, the USB apparatus including a microcontroller having a first port and a second port, the first port being coupled via a resistance to a voltage source and a switch, operated by the microcontroller via the second port, selectably interconnecting the first port and the bus of the USB host.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: September 30, 2014
    Assignee: Verifone, Inc.
    Inventors: Yuan Fuat Chin, Kian Tiong Yeo, Song Gee Lim
  • Patent number: 8816722
    Abstract: An object is to widen detection range of current. A current detection circuit includes a first resistor, which is connected to a first connection terminal and a second connection terminal; a second resistor, which is connected to the first resistor; a third resistor, which is connected to the first resistor; a first transistor, a source of which is connected to the second resistor; a second transistor, a source of which is connected to the third resistor, and a drain and a gate of which is connected to a gate of the first transistor; a third transistor, a source of which is connected to the source of the second transistor, and a gate of which is connected to the drain of the first transistor; and a fourth resistor, which is connected to the drain of the third transistor, and to which a voltage is input.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: August 26, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tatsuji Nishijima
  • Patent number: 8779748
    Abstract: An error amplification circuit includes an integrated circuit and a phase compensation capacitor. The integrated circuit includes an error amplifier to amplify a difference between a predetermined reference voltage and an input feedback voltage for output; a current generator circuit to generate a bias current for supply to the error amplifier; a phase compensation resistor; a bias-current control terminal; and a phase compensation terminal connected to an output terminal of the error amplifier via the phase compensation resistor. The phase compensation capacitor is connected to the phase compensation terminal, the phase compensation capacitor being provided outside the integrated circuit.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: July 15, 2014
    Assignee: Ricoh Company, Ltd.
    Inventor: Takashi Gotoh
  • Patent number: 8761300
    Abstract: According to one embodiment, a peak detector having extended dynamic range comprises a first differential output coupled to a supply voltage of the peak detector by a first load and coupled to ground by first and second switching devices, and a second differential output coupled to the supply voltage by a second load and coupled to ground by third and fourth switching devices. The control terminals of the first, second, third, and fourth switching devices receive a common bias voltage, and the respective first and second control terminals are configured as differential inputs of the peak detector. In some embodiments, corresponding first power terminals of the first and second switching devices share a first common node further shared by the first differential output, and corresponding first power terminals of the third and fourth switching devices share a second common node further shared by the second differential output.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: June 24, 2014
    Assignee: Broadcom Corporation
    Inventors: Ahmad Mirzaei, Hooman Darabi
  • Patent number: 8754673
    Abstract: An integrated circuit device includes a reference voltage generator, which is configured to generate an adaptive reference voltage (Vref) that varies inversely relative to changes in magnitude of a data signal (DATA) received at an input thereof. This reference voltage generator includes a totem pole arrangement of at least two variable impedance elements having control terminals capacitively coupled (by respective capacitors) to the input. A current mirror is electrically coupled to the totem pole arrangement of at least two variable impedance elements. A comparator is also included. The comparator has a first input terminal that receives the adaptive reference voltage and a second input terminal that receives the data signal.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: June 17, 2014
    Assignee: Integrated Device Technology inc.
    Inventors: Wei Wang, Yumin Zhang
  • Publication number: 20140077842
    Abstract: Embodiments of a power-on and brown-out detector are described. In an embodiment, a power-on and brown-out detector for a power supply includes a power-on detection module, a brown-out detection module, and a logic module. The power-on detection module is connected to the power supply and is configured to generate a power-on signal in response to a voltage increase of the power supply. The brown-out detection module is connected to the power supply and is configured to generate a brown-out signal in response to a voltage charge by the power supply and a subsequent voltage decrease of the power supply. The logic module is configured to generate a control signal in response to the power-on signal and the brown-out signal. The power-on detection module is further configured to be activated or deactivated by the control signal. Other embodiments are also described.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Applicant: NXP B.V.
    Inventors: JUNMOU ZHANG, JIAN QING
  • Patent number: 8653865
    Abstract: A voltage change detection device is provided, which can reduce a deviation of a detection potential and can detect a voltage change within a predetermined detection potential even when the threshold voltage of a field effect transistor is deviated. The voltage change detection device includes a first field effect transistor, a second field effect transistor, and a detection signal generator. The first field effect transistor has a drain connected to a power supply potential, a source connected to a first constant current source or a first resistor at a first node, and a gate connected to a fixed voltage. The second field effect transistor has a drain and a gate connected to the power supply potential and a source connected to a second constant current source or a second resistor at a second node.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: February 18, 2014
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Kikuo Utsuno
  • Publication number: 20130321029
    Abstract: An input decision circuit includes a comparator outputting either one of a high voltage or a low voltage on the basis of the result of a comparison between a reference voltage and an input voltage, a base voltage source acting as a base common to the reference voltage and the input voltage, a constant current source supplying a constant current to a constant current path from a DC power supply to the base voltage source, and a resistor inserted in the constant current path. A constant voltage is produced across the resistor for the reference voltage with the electric potential of the base voltage source acting as a base. This provides an input decision circuit in which a threshold voltage is hard to shift even when the driving voltage of the comparator or the electric potential of the ground acting as the base voltage source is varied.
    Type: Application
    Filed: May 16, 2013
    Publication date: December 5, 2013
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yuya ABE, Takanori KOHAMA
  • Patent number: 8598935
    Abstract: A system and method for providing an accurate current reference using a low-power current source is disclosed. A preferred embodiment comprises a system comprises a first section and a second section. The first section comprises a first simple current reference, an accurate current reference, and a circuit that generates a digital error signal based upon a comparison of an output of the first simple current reference and an output of the accurate current reference. The second section comprises a second simple current reference providing a second reference current, an adjustment circuit providing an adjustment current based upon the digital error signal, and a circuit biased with current equivalent to a summation of the second reference current and the adjustment current. The first simple current reference and the second simple current reference may be equivalent circuits.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: December 3, 2013
    Assignee: Infineon Technologies AG
    Inventor: Paolo Del Croce
  • Patent number: 8581641
    Abstract: A power-up signal generation circuit includes: a first section signal generation unit configured to sense a level of an external voltage and a level of an internal voltage and generate a first section signal; a second section signal generation unit configured to output a second section signal by buffering the first section signal when the internal voltage is lowered to below a minimum level; and a selective output unit configured to output the first section signal as a power-up signal, wherein the selective output unit outputs the second section signal as the power-up signal when a power-up section is ended and a mode register setting operation is performed.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: November 12, 2013
    Assignee: SK Hynix Inc.
    Inventor: Yong Deok Cho
  • Patent number: 8536908
    Abstract: An apparatus and method for testing is provided. An integrated circuit includes a comparison circuit that is arranged to trip based on a power supply signal reaching a trip point. The integrated circuit also includes an analog-to-digital converter that is arranged to convert the power supply signal into a digital signal. The integrated circuit also includes a storage component that stores a digital value associated with the digital signal, and provides the power supply value at an output pin of the integrated circuit. The integrated circuit includes a latch that is coupled between the analog-to-digital converter and the storage component. The latch is arranged to open when the comparison circuit trips, such that, when the comparison circuit trips, the storage component continues to store a digital value such that the digital value corresponds to the voltage associated with the power supply signal when the comparison circuit tripped.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: September 17, 2013
    Assignee: Spansion LLC
    Inventors: Hor Ching-Kooi, Teoh Boon-Weng, Ong Mee-Choo
  • Patent number: 8531491
    Abstract: The present invention discloses a current-matching circuit including a hierarchical tree structure having two or more levels, each of which includes multiple matching devices, wherein each matching device at a preceding level corresponds to a predetermined number of matching devices at a next level. Respective matching devices at a last level control currents in respective current channels; the channels of the same group are matched with one another in current.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: September 10, 2013
    Assignee: Richtek Technology Corporation
    Inventor: Jing-Meng Liu
  • Patent number: 8497711
    Abstract: An envelope detecting method performing squelch detection on a pair of differential signal includes: by a voltage divider, providing a real-time reference signal according to a sum of the pair of differential signals; and comparing two comparison signals associated with the real-time reference signals and the pair of differential signals to generate a squelch detection signal.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: July 30, 2013
    Assignee: MStar Semiconductor, Inc.
    Inventor: Yi-Cheng Hsieh
  • Patent number: 8497712
    Abstract: A circuit includes a comparator, a programmable current source, and a control circuit. The comparator is operable to compare an internal supply voltage of the circuit to a reference voltage. The programmable current source is operable to supply a first current for the reference voltage. The control circuit is operable to control the first current through the programmable current source based on an output signal of the comparator.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: July 30, 2013
    Assignee: Altera Corporation
    Inventors: Andy Nguyen, Ling Yu
  • Patent number: 8487660
    Abstract: A temperature stable comparator circuit, comprised of: a branch C having a first end, a second end, a first type-1 device and first type-2 device, wherein the first type-1 device and the first type-2 device are connected to a node O; a branch B having a first end, a second end, a second type-1 device, a second type-2 device, and a resistor; and a branch A having a first end, a second end, a third type-2 device and a current-control device; wherein the first ends of the branch A, branch B, and branch C are commonly connected, and the second ends of the branch B and branch C are commonly connected.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: July 16, 2013
    Assignee: Aptus Power Semiconductor
    Inventor: Brian Harold Floyd
  • Patent number: 8476938
    Abstract: The device for generating three mode signals includes: a voltage setting block including an input terminal receiving three input signals of driving voltage, open, and ground and setting three voltages according to the three input signals; and an output block including two output terminals and a second node B receiving the three voltages from the voltage setting block, and outputting three combined signals by comparing an input voltage with a reference voltage, whereby only a small number of resistors and amplifiers generates three mode signals to further reduce the chip size than the related art and the external power source is not required to solve the problems of the related art due to noise.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: July 2, 2013
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Joon Youp Sung, Jung Sun Kwon, Jae Shin Lee, Seung Kon Kong, Jung Hyun Kim, Bo Hyun Hwang
  • Publication number: 20130154688
    Abstract: A method for detecting a position with respect to a mobile working machine includes providing a current signal in a boundary conductor, which surrounds the defined area, in accordance with a boundary signal that is provided, the boundary signal corresponding to a pseudo-accident signal; and receiving a detection signal of a magnetic field. The method further includes generating a reconstructed boundary signal from the detection signal; providing a reference signal which has a bit pattern corresponding to the boundary signal provided; carrying out a correlation method in order to determine a time-based correlation offset between the reference signal and the reconstructed boundary signal and a correlation value between the reference signal and the reconstructed boundary signal, which are displaced in relation to each other by the correlation offset determined; and determining a position inside or outside the defined area as a function of the correlation value determined.
    Type: Application
    Filed: February 28, 2011
    Publication date: June 20, 2013
    Applicant: Robert Bosch GmbH
    Inventors: Steffen Petereit, Amos Albert
  • Publication number: 20130141969
    Abstract: A semiconductor integrated circuit includes a first constant current output circuit that outputs a first constant current from a first constant current terminal to a first output terminal. The semiconductor integrated circuit includes an error current output circuit that outputs an error current from an error current terminal to the first output terminal.
    Type: Application
    Filed: February 21, 2012
    Publication date: June 6, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Yoshihide NAKAJIMA
  • Patent number: 8446179
    Abstract: A non-linear effect of a rectifier element is enhanced, an input amplitude is increased by further taking advantage of a resonance circuit, and a rectification efficiency of a rectifier circuit for detection is improved, so that the gain of an amplifier circuit at a latter stage can be set low. RF input terminals 101, 102 are applied with signals at phases opposite to each other. A signal at terminal 102 is applied to a gate of transistor M1 through capacitor C3, and a signal at terminal 101 is applied to node N1 connected with a source of transistor M1 and a gate and a drain of transistor M2 through capacitor C1. 301, 302 designate terminals applied with DC biases, and L1, C15 and L2, C16 are series resonance circuits. Half-wave double voltage rectifier circuits comprised of M1, M2, C1-C3, R1 are connected in cascade at a plurality of stages.
    Type: Grant
    Filed: November 29, 2006
    Date of Patent: May 21, 2013
    Assignee: NEC Corporation
    Inventors: Tadashi Maeda, Tomoyuki Yamase
  • Patent number: 8436659
    Abstract: Embodiments of the present invention include an electronic circuit that reduces stress on a transistor. In one embodiment, the electronic circuit comprises a transistor and a reference generator circuit. The transistor may be a metal oxide semiconductor (MOS) transistor, for example. The MOS transistor has a gate terminal to receive an input voltage. The reference generator circuit selectively couples first and second reference voltages to a source terminal of the MOS transistor. The reference generator circuit senses the input voltage and provides the first reference voltage to the source terminal of the MOS transistor if the input voltage is greater than a threshold and the second reference voltage is coupled to the source terminal of the first MOS transistor if the input voltage is less than a threshold.
    Type: Grant
    Filed: June 19, 2009
    Date of Patent: May 7, 2013
    Assignee: Marvell International Ltd.
    Inventor: Kah Hooi Lim
  • Patent number: 8384446
    Abstract: A power-up signal generation circuit includes: a first section signal generation unit configured to sense a level of an external voltage and a level of an internal voltage and generate a first section signal; a second section signal generation unit configured to output a second section signal by buffering the first section signal when the internal voltage is lowered to below a minimum level; and a selective output unit configured to output the first section signal as a power-up signal, wherein the selective output unit outputs the second section signal as the power-up signal when a power-up section is ended and a mode register setting operation is performed.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: February 26, 2013
    Assignee: SK Hynix Inc.
    Inventor: Yong Deok Cho
  • Patent number: 8373445
    Abstract: This transmission input circuit is provided with an adjustment processing section which turns ON a switch at an empty timing where transmission current from a slave device is not flowing, to allow a reference current to flow from a constant current circuit to a current detection resistor, generates in the current detection resistor a target adjustment voltage, in which a threshold voltage corresponding to the reference current is added to a load current detection voltage corresponding to the load current, and adjusts a digital value so that a reference voltage output from a digital variable resistor matches with the target adjustment voltage.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: February 12, 2013
    Assignee: Hochiki Corporation
    Inventor: Mitsuhiro Kurimoto
  • Patent number: 8362808
    Abstract: A transmission input circuit of the present invention is provided with: a current detection resistor which receives an input of a line current flowing through a transmission line and generates a line current detection voltage; a constant current circuit which generates a predetermined reference current; a first switch which performs a switching operation at an empty timing where a transmission current is not flowing, to thereby allow the reference current to flow from the constant current circuit to the current detection resistor, and generate a reference voltage, in which a threshold voltage corresponding to the reference current is added to a load current detection voltage corresponding to the load current; a capacitor which is connected to the current detection resistor via the first switch; a second switch which performs a switching operation in synchronization with the first switch to thereby sample-hold the reference voltage generated by the current detection resistor in the capacitor; and a comparator
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: January 29, 2013
    Assignee: Hochiki Corporation
    Inventor: Mitsuhiro Kurimoto
  • Patent number: 8339176
    Abstract: A system and method for providing an accurate current reference using a low-power current source is disclosed. A preferred embodiment comprises a system comprises a first section and a second section. The first section comprises a first simple current reference, an accurate current reference, and a circuit that generates a digital error signal based upon a comparison of an output of the first simple current reference and an output of the accurate current reference. The second section comprises a second simple current reference providing a second reference current, an adjustment circuit providing an adjustment current based upon the digital error signal, and a circuit biased with current equivalent to a summation of the second reference current and the adjustment current. The first simple current reference and the second simple current reference may be equivalent circuits.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: December 25, 2012
    Assignee: Infineon Technologies AG
    Inventor: Paolo Del Croce
  • Patent number: 8330526
    Abstract: A low voltage detector (100) includes a voltage and current reference circuit (102); a power supply voltage monitor circuit (104), coupled to the voltage and current reference circuit and to a power supply; and a voltage comparator (106), coupled to the voltage and current reference circuit and to the power supply voltage monitor circuit. The voltage and current reference circuit includes a self-cascode MOSFET structure (SCM) (110) that produces a reference voltage. The power supply voltage monitoring circuit includes another SCM (140) that produces a monitor voltage, related to the power supply voltage. The reference voltage and the monitor voltage have a same behavior with changes in temperature, thereby allowing the trip point of the low voltage detector to minimally vary with temperature. The low voltage detector is disposed on an integrated circuit (101), and the transistors of the low voltage detector consist of only CMOS transistors.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: December 11, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Andre Luis Vilas Boas, Alfredo Olmos, Fabio de Lacerda, Edgar Mauricio Camacho Galeano
  • Patent number: 8325848
    Abstract: According to one embodiment, a peak detector having extended dynamic range comprises a first differential output coupled to a supply voltage of the peak detector by a first load and coupled to ground by first and second switching devices, and a second differential output coupled to the supply voltage by a second load and coupled to ground by third and fourth switching devices. The control terminals of the first, second, third, and fourth switching devices receive a common bias voltage, and the respective first and second control terminals are configured as differential inputs of the peak detector. In some embodiments, corresponding first power terminals of the first and second switching devices share a first common node further shared by the first differential output, and corresponding first power terminals of the third and fourth switching devices share a second common node further shared by the second differential output.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: December 4, 2012
    Assignee: Broadcom Corporation
    Inventors: Ahmad Mirzaei, Hooman Darabi
  • Patent number: 8310280
    Abstract: A half-power buffer amplifier is disclosed. A buffer stage includes a first-half buffer stage and a second-half buffer stage, wherein an output of the first-half buffer stage is controllably fed back to a rail-to-rail differential amplifier, and an output of the second-half buffer stage is controllably fed back to the rail-to-rail differential amplifier. The switch network controls the connection between the outputs of the buffer stage and an output node of the half-power buffer amplifier in a manner such that a same pixel, with respect to different frames, of a display panel is driven by the same rail-to-rail differential amplifier. In one embodiment, the rail-to-rail differential amplifier and the buffer stage comprise half-power transistors operated within and powered by half of a full range spanning from power to ground.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: November 13, 2012
    Assignee: Himax Technologies Limited
    Inventors: Hung-Yu Huang, Chen-Yu Wang
  • Publication number: 20120280720
    Abstract: A method for deskewing a differential signal is provided. A common-mode voltage of a differential signal and an average for the common-mode voltage of the differential signal are measured. A difference between first and second portions of the differential signal is determined, and deskew information is derived from the common-mode voltage and the average. The deskew information can then be combined with the difference to deskew the differential signal.
    Type: Application
    Filed: May 4, 2011
    Publication date: November 8, 2012
    Applicant: Texas Instruments Incorporated
    Inventor: Robert F. Payne
  • Patent number: 8305113
    Abstract: A method for deskewing a differential signal is provided. A common-mode voltage of a differential signal and an average for the common-mode voltage of the differential signal are measured. A difference between first and second portions of the differential signal is determined, and deskew information is derived from the common-mode voltage and the average. The deskew information can then be combined with the difference to deskew the differential signal.
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: November 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Robert F. Payne