Abstract: A peak voltage detector is used to detect the absolute value of the peak differential amplitude of a differential input signal. The peak voltage detector includes a differential amplifier receiving the differential input signal and generating a corresponding pair of differential output signals. The voltage detector also includes a capacitor on which an output signal is generated. A first differential comparator generates a first signal whenever the differential voltage from the differential amplifier is greater than the voltage of the output signal. A second differential comparator generates a second signal whenever the negative of the differential voltage from the differential amplifier is greater than the voltage of the output signal. A current source applies current to the capacitor responsive to receiving either the first or second signal. The amplitude of the feedback voltage is thus equal to the absolute value of the peak differential amplitude of the input signal.

Abstract: The invention discloses baseline wandering correction techniques. A baseline wandering correction device comprises a differentiator differentiating a data signal to generate a differentiated signal, a operation signal coupling to the differentiator and proceeding with an operation based on the data signal according to the differentiated signal to generate an operated signal, an extracting module coupling to the operation module and determining a first and a second threshold value according to the operated signal, a comparing signal coupling to the extracting module and comparing the operated signal with the first and second threshold values to generate a first and a second processing signal, and a latch module latching the first and second processing signals to generate an output signal.

Abstract: There is disclosed a circuit and a process for detecting peak-to-peak voltage. The circuit comprises a first comparator having an output coupled to a first capacitor, a non-inverting input for receiving a high frequency AC waveform, and an inverting input, a second comparator having an output coupled to a second capacitor, and a first second input, an operational amplifier having a non-inverting input coupled to the inverting input of the first comparator, and an inverting input coupled to the first input. The process comprises charging a first capacitor when a high frequency AC waveform voltage is greater than a buffered voltage of the first capacitor, charging a second capacitor when an inverted buffered voltage of the second capacitor is greater than the high frequency AC waveform voltage, and outputting a voltage based on the buffered voltage of the first capacitor and the inverted buffered voltage of the second capacitor.

Abstract: A voltage detecting circuit included in a battery device includes an input voltage comparing circuit that compares a first threshold value voltage or a second threshold value voltage lower than the first threshold value voltage with an input voltage to control the opening and closing of an output switching element, and a threshold value voltage setting circuit that compares a third threshold value voltage lower than the second threshold value voltage with the input voltage and, when the input voltage changes from a low voltage to a high voltage and intersects the third threshold value voltage, outputs a pulse for a predetermined period thereafter so that the second threshold value is selected in the input voltage comparing circuit. As a result, when the input voltage increases from the ground potential, the second threshold value is compared with the input voltage in the input voltage comparing circuit.

Abstract: The present invention reliably removes a signal change associated with a noise component from a comparison signal of a comparator. A comparator circuit includes a comparator and a timer circuit. After a reversal of the comparison signal, if the level of the comparator is sustained at least from a first time to a second time, an output signal is reversed and output. The timer circuit includes a memory unit that is shifted to a memory state in which the reversal of the comparison signal is stored at the first time if the reversal is verified. If the comparison signal is reversed during the interval between the first time and second time, the memory state is cleared.

Abstract: An internal voltage generator that generates an internal voltage for a Delay Locked Loop (DLL) and an internal clock generator including the same, and an internal voltage generating method for a DLL. The internal voltage generator includes a standby voltage generator that generates the DLL internal voltage as a reference voltage level, a controller that generates an active control signal in response to a power-down signal and an active signal, and an active voltage generator that generates the DLL internal voltage of the reference voltage level in response to the active control signal. After the power-down mode is ended, the active voltage generator is additionally operated during a predetermined time when the DLL is initially enabled. It is therefore possible to generate stabilized DLL internal voltages.

Abstract: A voltage detecting circuit included in a battery device includes an input voltage comparing circuit that compares a first threshold value voltage or a second threshold value voltage lower than the first threshold value voltage with an input voltage to control the opening and closing of an output switching element, and a threshold value voltage setting circuit that compares a third threshold value voltage lower than the second threshold value voltage with the input voltage and, when the input voltage changes from a low voltage to a high voltage and intersects the third threshold value voltage, outputs a pulse for a predetermined period thereafter so that the second threshold value is selected in the input voltage comparing circuit. As a result, when the input voltage increases from the ground potential, the second threshold value is compared with the input voltage in the input voltage comparing circuit.

Abstract: A peak detector is provided. Current switches are utilized and controlled by output of a plurality of error amplifiers respectively, such that charging currents are adjusted for a charge element in response to operations of the current switches respectively. Therefore, the overshooting charge is avoided and the time for charge is optimized.

Abstract: An adaptive hysteresis receiver processes a high speed digital signal. A differential receiver circuit compares the high speed digital signal to a reference voltage to generate an output signal. A register circuit latches the output signal, according to a clock signal, to produce a control signal. A reference voltage generator generates the reference voltage, from a plurality of voltages defining a deep hysteresis level and a shallow hysteresis level, in response to the output signal and the control signal.

Abstract: A semiconductor device, includes a lower layer side insulation film; a wiring pattern formed on the lower layer side insulation film; a base insulation film formed on the lower layer side insulation film and the wiring pattern; and a plurality of metal thin film resistance elements formed on the base insulation film; wherein a connection hole is formed in the base insulation film on the wiring pattern; the wiring pattern and the metal thin film resistance element are electrically connected in the connection hole; the metal thin film resistance element has a belt shape part arranged separately from the connection hole and a connection part continuously formed with the belt shape part and connected to the wiring pattern in the connection hole; and the connection parts of at least two of the metal thin film resistance element are formed in the single connection hole with a gap in between said connection parts.

Abstract: A method is disclosed for controlling a first transistor in a half-bridge circuit which also includes a second transistor. The transistors can be controlled by applying drive voltages to their gates. During a switch-off operation of the second transistor, the amplitude of the drive voltage of the second transistor is compared with a first threshold value and a second threshold value. A switch-on operation for the first transistor is started following a specified first period which begins at a first time when the drive voltage of the second transistor undershoots the first threshold value. The first threshold value is set in accordance with a second period which begins at a second time when the amplitude of the drive voltage of the second transistor undershoots the second threshold value. The second period ends at another time when the first transistor adopts a specified initial operating state during the switch-on operation.

Abstract: Reference network embodiments are disclosed that provide reference signals to, for example, switched-capacitor multiplying digital-to-analog converters (MDACs) in pipelined analog-to-digital converters (ADCs). These embodiments are configured to maintain accuracy of the levels of the reference signals in the presence of high speed charge-injection and charge-extraction currents which are presented by the MDACs.

Abstract: A single ended input circuit can receive an input signal and generate a correction voltage corresponding to a common mode voltage of the input signal. A comparison of the input signal can be adjusted in response to the correction voltage. In one arrangement, an input circuit (100) can include a compare section (102) with first input (104-0) and second input (104-1). The first input (104-0) can receive an input signal (IN). The second input (104-1) can receive a reference voltage generated by a common mode detect and hold (CMDH) section (106). A (CMDH) section (106) can include an integrator circuit (108), an analog-to-digital (A/D) converter circuit (110), a digital hold circuit (112), and a digital-to-analog (D/A) converter (114). A correction voltage generated by integrating the input signal can be applied as the generated reference voltage.

Abstract: There is disclosed a circuit and a process for detecting peak-to-peak voltage. The circuit comprises a first comparator having an output coupled to a first capacitor, a non-inverting input for receiving a high frequency AC waveform, and an inverting input, a second comparator having an output coupled to a second capacitor, and a first second input, an operational amplifier having a non-inverting input coupled to the inverting input of the first comparator, and an inverting input coupled to the first input. The process comprises charging a first capacitor when a high frequency AC waveform voltage is greater than a buffered voltage of the first capacitor, charging a second capacitor when an inverted buffered voltage of the second capacitor is greater than the high frequency AC waveform voltage, and outputting a voltage based on the buffered voltage of the first capacitor and the inverted buffered voltage of the second capacitor.

Abstract: In satisfying the above need, as well as overcoming the enumerated drawbacks and other limitations of the related art, the present invention provides an improved switched driver circuit. As disclosed above, there is a need to compensate for the high impedance load characteristics in certain implementations of hysteretic switching constant current drivers. The switching waveform of switching constant current driver circuits may be modified in such a way that retains the important dither characteristics and improves system level performance.

Abstract: An On-Off control circuit between the IEEE1394a and IEEE1394b compliant physical layer (PHY) output driver circuitry and the glass fiber optical physical medium dependent (PMD) sub-layer within the architecture of the IEEE 1394b standard addresses the stability issue incurred by electronic circuit's inherent noise that interferes with the connection detecting procedure defined by the connection management protocol (CMP) of the IEEE 1394b standard. The circuit includes of a voltage divider to provide a reference voltage of about 50% of the output common mode voltage, a voltage comparator, and a feedback coupled to the positive input of the comparator to eliminate possible oscillation. The negative input of the comparator may be connected to the mid point of TPB termination network and the positive input of the comparator may be connected to the output of the voltage dividing circuit. The output of the comparator may be connected to the transmission enable bar input of the optical transceiver.

Abstract: Provided is a pass gate circuit capable of operating stably in a transition phase of an input signal, a self-refresh circuit including the pass gate circuit, and a method of controlling the pass gate circuit. The pass gate circuit according to the present invention includes a pass gate unit and a pass gate control unit. The pass gate unit delays an input signal for a fixed duration and outputs the delayed input signal as an output signal in response to a switching control signal. The pass gate control unit outputs the switching control signal, and in response to an internal control signal, determines the existence of a transition in the input signal, and enables or disables the switching control signal according to the determination. The pass gate circuit, the self-refresh circuit including the same, and the control method of the pass gate circuit are capable of operating stably in the transition phase of the input signal.

Abstract: A signal processing circuit includes a comparator having a fixed and a variable reference input for detection of a positive quasi-sinusoidal waveform pulse. A signal detection circuit includes a low pass input filter, a voltage input clamp, a variable detection threshold, and a zero crossing detector. The circuit produces an approximately square wave output substantially coinciding with the positive pulse of the quasi-sinusoidal waveform received, from a variable reluctance sensor. The circuit has a positive to negative zero crossing detector armed by a variable threshold of the positive quasi-sinusoidal pulse, thus providing variable noise immunity and a fixed phase relationship between the input and output signal for an input signal having a variable amplitude.

Abstract: A method for tracking the MOS oxide thickness by the native threshold voltage of a “native” MOS transistor without channel implantation for the purpose of compensating MOS capacitance variations is achieved. The invention makes use of the fact that in MOS devices the threshold voltage is proportionally correlated to the oxide thickness of said MOS device. Said threshold voltage can therefore be used to build a reference voltage Vx+Vth which accurately tracks the MOS capacitance variations in integrated circuits. Circuits are achieved to create a frequency reference and a capacitance reference using said method. Additionally a method is introduced to create a capacitance reference in integrated circuits using said MOSFET capacitors.

Abstract: An input circuit in a DRAM includes a differential amplifier circuit amplifying a potential difference between a potential of an input signal and a reference potential, an inverter outputting an inversion signal of an output signal of the differential amplifier circuit, a latch circuit holding an output signal in a preceding cycle, and two resistive elements for switching the reference potential in accordance with an output signal of the latch circuit. Thus, the reference potential is switched in accordance with the logic level of the input signal in the preceding cycle, allowing accurate determination of the logic level of the input signal.

Abstract: An input receiver with hysteresis including a differential sense amplifier, a reference circuit having a reference node providing a reference signal at a nominal threshold voltage level, and a switching stack device. The amplifier has a first input which receives an input signal, a second input coupled to the reference node, and an output which provides an output signal having first and second states indicative of the input signal. The switching stack device operates to adjust the reference signal based on the output signal between upper and lower threshold levels in an opposite direction of the input signal. The reference circuit may be a voltage divider that divides a power voltage signal to develop the reference signal. The switching stack device may include a P-channel device and an N-channel device coupled to the voltage divider to adjust the threshold voltage level of the reference signal.

Abstract: A voltage follower comprising a first field-effect transistor (MN1) whose gate forms the input of the voltage follower. Further provided is a second field-effect transistor (MN2) whose drain connected to the gate forms the output of the voltage follower. The sources of the two field-effect transistors (MN1, MN2) are connected to each other and to the drain of a third field-effect transistor (MN3) serving as current source and to the gate of which a predefined bias voltage is applied. The invention employs in addition a fourth field-effect transistor (MN4) whose source-drain path is circuited between the output of the voltage follower and the drain of the third field-effect transistor (MN3) and whose gate is connected to the gate of the third field-effect transistor (MN3). As compared to prior art voltage followers the voltage follower in accordance with the invention comprises a wider voltage range in which it can be put to use. This can be made use of e.g.

Abstract: A precision current source is disclosed that includes a voltage setting circuit that precisely sets the voltage across a range setting resistor to set the current flowing in a load resistance connected in series with the range setting resistor. The voltage setting circuit precisely sets the voltage across the range setting resistor as a function of an input reference voltage. The voltage setting circuit includes an instrumentation amplifier that determines the voltage across the range setting resistor and the difference between this voltage and the reference voltage is used drive a drive voltage amplifier. The drive voltage amplifier output adjusts to minimize the difference between the reference voltage and the voltage across the range setting resistor. Other embodiments include the use of a DC blocking capacitor to allow only AC coupling and various nulling. circuits to remove any charge buildup on a DC blocking capacitor.

Abstract: A differential pair input receiver (30) having variable reference voltages that may be customized by the designer so as to increase and decrease noise margins of the amplifier. This input receiver (30) includes a complementary self-biased differential amplifier (10) and a dynamic hysteresis voltage reference circuit (20), wherein the complementary self-biased differential amplifier (10) has an input node (Input2), a reference output node (S2), and a dynamic voltage reference node (VDYNREF). The dynamic hysteresis voltage reference circuit (20) connects between the reference output node (S2) and the dynamic voltage reference node (VDYNREF) to provide a reference voltage (Vref) at the dynamic voltage reference node(VDYNREF). The reference voltage (Vref) serves as a threshold for the complementary self-biased differential amplifier (10), such that the output transitions from high-to-low and low-to-high when the input is equal to the reference voltage (Vref).

Abstract: An input buffer circuit for use with an analog-to-digital converter is provided. The input buffer circuit comprises a first amplifier configured with a second amplifier to improve the overall gain of the input buffer circuit. The first amplifier comprises a differential pair of transistors configured with a second pair of transistors comprising a current mirror arrangement, wherein one of the differential pair of transistors of the first amplifier is configured in a diode-connected arrangement to provide a first feedback loop, while the second amplifier comprises a differential pair of transistors configured with another pair of transistors also comprising a current mirror arrangement, with the second amplifier and the current mirror arrangement of the first amplifier comprising a second feedback loop.

Abstract: A peak detector circuit providing a comparator that produces a low voltage output by pulling the output to common when an input signal exceeds a reference voltage and that produces a floating output by not conducting when the input signal does not exceed the reference voltage. A low output from the comparator generates a base current sufficient to drive a PNP transistor, which in turn drives current to a DC output capacitor. Until the input signal exceeds the reference voltage, neither the comparator nor the PNP transistor need to conduct and, consequently, the peak detector consumes relatively little power. The peak detector can be beneficially employed in a network interface unit or other transmission line unit.

Abstract: The present invention implements a signal processing function without the use of a DSP (digital signal processor) or ADC. A reference signal is produced that relates to a DAC output code. The reference signal is used as a starting point, and is compared to the input signal. A feedback signal is produced that is used to adjust the reference. The invention can be used to implement signal processing functions such as peak detection, noise filtering, peak suppression, and the like. The invention can implement these functions with a minimal complexity and a minimal die area.

Abstract: A low power differential comparator wherein the input stage bias is used not only to set a bias level but is also used to set the hysteresis level of the differential comparator circuit. The positive and/or negative inputs to the differential comparator circuit are referred to ground to reduce the total DC current draw, e.g., by a factor of 7. The multiple use of the input stage bias and grounded connections to the positive and/or negative inputs reduce the overall current requirements of the differential comparator circuit substantially while maintaining full operating speed as compared to conventional differential comparator circuits. In one embodiment using the low power differential comparator circuit, a clock receiver implements hysteresis which is relatively independent from variations in environmental factors such as temperature, and from power supply variations. In this embodiment, the input stage of a low power comparator circuit is biased by the output of a bias circuit.

Abstract: A circuit receives data from a high frequency data line. The circuit determines the data value by employing a decision circuit and an over-sampling circuit. The over-sampling circuit captures the data levels on the data line at spaced apart time intervals. The decision circuit employs the data levels captured by the over-sampling circuit and a previously stored value to determine the data level that should be received from the data line.

Abstract: The present vehicle data system collects, encodes, transmits, decodes, and displays engine and vehicle operation information. In one mode, an engine control unit of an outboard boat motor receives a plurality of engine and vehicle operation parameters from a plurality of sensors. The engine control unit encodes the plurality of parameters in a single signal and transmits the encoded signal to a display unit over a signal line. The display unit decodes the encoded signal to extract the plurality of parameters and displays the extracted parameters to the vehicle operator.

Abstract: An automatic input threshold selector includes a maximum value level decision circuit, and an input threshold setting circuit. The maximum value level decision circuit decides, among m+1 level layers defined by m maximum value decision levels, a level layer to which the maximum value of an input signal belongs. The input threshold setting circuit sets an input threshold by selecting one of n input threshold candidates in response to the level layer to which the input signal maximum value belongs. These circuits are implemented as a simple combination of a voltage comparator, logic gates and the like. This makes it possible to solve a problem of a conventional automatic input threshold selector in that its circuit scale and power consumption is rather large because it includes a peak-hold circuit and a bottom-hold circuit.

Abstract: The present vehicle data system collects, encodes, transmits, decodes, and displays engine and vehicle operation information. In one mode, an engine control unit of an outboard boat motor receives a plurality of engine and vehicle operation parameters from a plurality of sensors. The engine control unit encodes the plurality of parameters in a single signal and transmits the encoded signal to a display unit over a signal line. The display unit decodes the encoded signal to extract the plurality of parameters and displays the extracted parameters to the vehicle operator.

Abstract: A CMOS amplifier includes a FET differential input stage, with the input transistors' sources connected to a common tail current. A first current mirror reflects the drain current from one input FET to the other at a first node. A pair of FETs are connected to conduct respective currents in response to the voltage at the first node. One of the currents drives a load at a second node, which is connected to one of the input stage gates such that the output voltage tracks an input voltage applied to the other input stage gate. The other current is reflected via a second current mirror to provide the common tail current. By properly sizing the FETs to achieve particular current densities, the tail current is automatically varied to adjust the operating point of the differential input stage such that, when the amplifier is in equilibrium, the drain voltages of the input FETs are kept equal over a wide range of output currents.

Abstract: A hysteresis circuit has a comparator which compares a threshold voltage and an input voltage. The threshold voltage is supplied from a voltage dividing circuit having resistors. A constant current circuit is connected to a voltage divided point of the voltage dividing circuit through a switch. The ON and OFF of the switch is controlled by an output of the comparator. When the switch is turned ON, a constant current flows to the voltage divided point, so that the value of the threshold voltage supplied from the voltage dividing circuit to the comparator is changed.

Abstract: An improved pulse detection circuit provides for a reduced delay response and noise immunity. The pulse detection circuit includes a comparator with a biasing circuit providing first and second biasing signal states. The biasing signal states are adjustably delayed relative to the detected signal.

Abstract: A hysteresis comparator circuit and a waveform generating circuit reduce a power consumption of a DC/DC converter so as to improve a power consumption efficiency when the DC/DC converter is operated with a relatively small load. The hysteresis comparator circuit is connected to a reference voltage source providing a reference voltage. A hysteresis comparator compares an input voltage with one of a first threshold voltage and a second threshold voltage. A hysteresis voltage generating circuit selectively generates one of the first and second threshold voltages by controlling a state of electric charge stored in each of the capacitors. An electric charge stored in the capacitors is provided from the reference voltage source.

Abstract: A multiplier circuit multiplies a reference voltage to increase the level of the reference voltage. A feedback circuit of the multiplier circuit stabilize the multiplier circuit such that a feedback voltage of said feedback circuit tends to equalize the reference voltage. The feedback circuit is free from capacitance which would unstabilize the feedback circuit. A voltage divider outside of the feedback circuit reduces the multiplied voltage of the multiplier circuit.

Abstract: A preamplifier circuit couple to a magneto-resistive (MR) head used in the read circuitry of a magnetic storage device includes differential amplifiers coupled to receive an input from the MR head and to provide output signals. The preamplifier is designed to provide a low noise level. To minimize noise, transistors of the differential amplifiers provide high current gain and have large device geometries.

Abstract: The invention provides a voltage regulating device for regulating the operating voltage of a CPU in a computer system. The voltage regulating device includes a voltage identification signal regulator and a voltage identification signal bridge. The voltage identification signal regulator is controlled by a controlling signal to output a voltage identification regulating signal to the voltage converter. In this case, the voltage converter outputs the operating voltage of the CPU according to the voltage identification regulating signal. Meanwhile, a voltage monitor is used to monitor the operating voltage. When the voltage identification signal regulator outputs the voltage identification regulating signal, a voltage identification signal bridge blocks a default voltage identification signal output from the voltage identification signal setting device.

Abstract: A detector circuit may detect a peak value of at least one input voltage and may provide the peak value as an output for use by other circuitry capable of being coupled to the detector circuit. Pairs of differential inputs may be employed, using n-channel transistors (in one example), and using diodes to capture the peak at a shared output node. Each differential pair has two constant current devices connecting the source/drain paths to the terminal of a voltage supply. This circuit enables the use of high input voltages which may be at or near the upper power supply (e.g., V.sub.DD). The circuit is in effect a negative peak detector, capturing the most negative value of at least one input level and holding that level, with a slow leakage of the held value back toward the upper voltage supply with a time constant that is generally set much slower than the input signal transition frequency. A similar circuit may be implemented using p-channel transistors in the differential pairs, to detect positive peaks.

Abstract: The present invention discloses a Schmitt-trigger circuit with less power consumption by reducing the amount of the required DC current. The Schmitt-trigger circuit disclosed in the present invention basically encompasses a comparison circuit, a first current cutting circuit, and a second current cutting circuit. The comparison circuit receives the input signal and then generates the output signal. Both the first and second current cutting circuits feed in the output signal, and then generate feedback signals to feed the comparison circuit for cutting the DC current path when the input signal rises or falls to predetermined trigger points. When there is only one of the first and second current cutting circuits is required, the higher or lower trigger point can be adjusted without necessary to vary the size-ratio of the PMOS and NMOS transistors.

Abstract: A circuit to provide a burn-in reference voltage that is stable with respect to temperature and manufacture. The burn-in reference voltage circuit produces a burn-in reference voltage related to an external reference voltage. The circuit includes a feedback circuit to produce a feedback voltage that tends to the internal reference voltage in response to a deviation of the feedback voltage, from the internal voltage. The feedback voltage is mirrored to produce a mirrored voltage having the same magnitude as the feedback voltage but measured with respect to the external reference voltage.

Abstract: In the design of an integrated circuit for comparing serial data signals, the number of transistor elements can be reduced by implementing the comparison gate (12) based on the associated truth table rather than by using a general comparison gate component. Using this method, an exclusive OR gate (22) can be implemented using two transistor elements (221, 222), an exclusive NOR gate (52) can be implemented using two transistor elements (521, 522), an AND gate (62) can be implemented using a single transistor element (621), and an OR gate (72) can be implemented using a single transistor element (721). The reduced number of elements used to implement the comparison gates can provide a transistor element saving in the associated circuit.

Abstract: A precision analog circuit ensures precision matching between two or more resistive elements. In order that the two or more resistive elements are truly matched, a first electrical value, such as V.sub.DS, of the two or more resistive elements are equal and a second electrical value, such as V.sub.GS, of the two or more resistive elements are equal so that a ratio of the first resistive element to the second resistive element is a predetermined value regardless of the voltage coefficients of the resistive elements.

Abstract: A Schmitt trigger circuit has an input device and an amplifier. The input device has a current adder device having a P-type current mirror circuit and a N-type current mirror circuit connected in parallel. The P-type current mirror circuit has a positive constant current source for converting an external input signal to a positive constant current and a first output current control transistor for controlling an output current from the positive constant current source. The N-type current mirror circuit has a negative constant current source for converting the external input signal to a negative constant current and a second output current control transistor for controlling an output current from the negative constant current source. The amplifier amplifies the output signal from the input device and generates the feed-back control signal to be used for controlling and driving the first output current control transistor and the second output current control transistor.

Abstract: A differential input buffer (14) and method of construction are provided. The differential input buffer (14) includes a differential amplifier (54, 56, 50, 52, 62, 64) connected to receive an input signal (IN). A local reference voltage generator (68, 70, 72) is connected to the differential amplifier (54, 56, 50, 52, 62, 64) and is connected to receive an external voltage reference (BLR) and to provide a local reference voltage (VREF) to the differential amplifier (54, 56, 50, 52, 62, 64). The local reference generator (68, 70, 72) is adjustable during construction to produce a desired level for the local reference voltage (VREF). The differential input buffer (14) also includes a hysteresis element (66, 74) that is connected to provide feedback to the differential amplifier (54, 56, 50, 52, 62, 64) and includes a buffer stage (76, 78, 80, 82, 84, 86) that is connected to receive an output of the differential amplifier (54, 56, 50, 52, 62, 64) and to drive an output signal (OUT).

Abstract: An improved pulse detection circuit provides for a reduced delay response and noise immunity. The pulse detection circuit includes a comparator with a hysteresis circuit providing a hysteresis response on the order of a minimum pulse width and a reference circuit having a time constant which is a function of unexpected signal input level.

Abstract: An analog video buffer utilizes a complementary push-pull CMOS source follower video buffer with a feedback driver. The CMOS source follower provides a low impedance output node with high driving capabilities, high switching speed, and rail-to-rail linearity and the feedback driver isolates the output node from the feedback needed for the design of the video buffer to provide a transient response without ringing or overshoot.

Abstract: A drive signal generating circuit for a sense amplifier compatible with a semiconductor memory device by driving a sense amplifier using both voltage applied from the outside and voltage outputted from a voltage generator. In a conventional circuit, when operating voltage of a sense amplifier is lowered, it is difficult to operate the sense amplifier in high speed as efficiency is lowered. Further, when only using output voltage outputted from the voltage generator, refresh characteristic of the memory cell is lowered because load is great and the sense amplifier is unstably operated in initial sensing state.

Abstract: An extractor for digital data transmitted at a first determined frequency (f0) through a video channel after a burst of 0s and 1s emitted at a first frequency (f0). A comparator (1) compares the input signal with a threshold level. A threshold level is provided by an up/down counter (12) operating at a frequency (F0) multiple of the first frequency, the up/down counting input of which is connected to the output of the comparator (1), and a digital/analog converter (16) receiving the output of the up/down counter and supplying the threshold level (V.sub.T).