Abstract: A control signal may be produced in response to an assertion of a switch signal by asserting the control signal, waiting an adaptive delay after the assertion of the switch signal, de-asserting the control signal in response to the expiration of the adaptive delay, and re-asserting the control signal in response to a current generated according to the control signal becoming zero. The adaptive delay may be adjusted according to a voltage generated using the current. A circuit may include an XOR gate producing the control signal from a switch signal and an output of a Set-Reset Flip-Flop (SRFF), a zero-detect circuit that resets the SRFF when a current generated using the control circuit becomes zero, and a delay circuit to set the SRFF an adaptive delay after assertion of the switch signal and to adjust the adaptive delay according to a voltage generated by the current.

Abstract: A circuit and method for linear constant current control for an LED lamp, and an LED device are provided. The power compensation for the input linear power network is performed. When the triac dimmer is connected into the AC linear power network, constant current bleed-off is performed on the current passing through. In the meanwhile, when the triac dimmer detection module detects that a dimmer is connected in, the corresponding bleeder current is switched off, thereby improving the efficiency of the system. In this way, the input power of the system remains basically unchanged as the input voltage changes, besides, the constant current output drives the LED lamp, such that it is solved the problem that in the existing LED lighting and driving technique, the brightness of the entire LED lamp would change in case of voltage fluctuation of the linear power network.

Abstract: According to an embodiment of a switch device, the switch device includes a first switch, a second switch and an evaluation circuit. The evaluation circuit is configured to evaluate a temporal behavior of a node between the first switch and the second switch to detect a possible fault condition of at least one of the first switch or the second switch. A corresponding fault detection method for a switch device having a first switch and a second switch is also provided.

Abstract: An analog-to-digital converter (ADC) circuit includes a first ADC stage comprising a first successive approximation register (SAR) circuit that is configured to convert a current analog input signal into a first digital signal corresponding to a most-significant-bits (MSB) portion of a current digital output signal, and to generate a residual voltage corresponding to a voltage value difference between the current analog input signal and the first digital signal; a second ADC stage, coupled to the first ADC stage, comprising an amplifier circuit that is configured to amplify the residual voltage; and a third ADC stage, coupled to the second ADC stage, comprising a second SAR circuit that is configured to convert the amplified residual voltage into a second digital signal corresponding to a least-significant-bits (LSB) portion of the current digital output signal when the first SAR circuit receives a subsequent analog input signal.

Abstract: A state-detection circuit facilitates the detection of the state of an input pin relative to several different types of input circuits. According to an example embodiment, a state-detection circuit includes a plurality of comparators and circuit components, configured to provide a plurality of binary output signals that collectively indicate a state of an input pin to which the comparators are coupled. The state-detection circuit is configured to facilitate the detection of several different types of input circuits, based upon the binary output signals.

Abstract: A digital interface system that includes a first circuit that transmits a set of voltage levels and a second circuit that receives the set of voltage levels and generates a set of voltage differential levels based on the set of voltage levels. The set of voltage differential levels corresponds to a first predetermined value. Each of the voltage levels is different from another of the voltage levels.

Abstract: Methods, circuits, and systems for determining the presence of a chopped input signal are disclosed. A digital signal generator can produce multiple digital signals when an alternating current (AC) signal input reaches multiple threshold voltages. The times at which the threshold voltages are reached can be determined by looking at the times at which the digital signals go high and low. The differences between the times at which the digital signals go high and low are used to determine if the AC signal input is a leading or trailing edge chopped signal. The AC input signal is a leading edge chopped signal when the difference between the times at which the digital signals go high is less than a predetermined time threshold, and is a trailing edge chopped signal when the difference between the times at which the digital signals go low is less than a predetermined time threshold.

Abstract: A level sensitive comparing device includes: a first comparator, a second comparator, and a determination circuit. The first comparator is arranged for comparing an input signal with a first reference level to generate a first comparison signal. The second comparator is arranged for comparing the input signal with a second reference level to generate a second comparison signal, wherein the second reference level is different from the first reference level. The determination circuit is coupled to the first comparator and the second comparator, and is arranged for determining whether the first comparison signal is allowed to appear at an output of the level sensitive comparing device according to at least the first comparison signal and the second comparison signal, wherein the determination circuit is composed of digital components only.

Abstract: Aspects of the instant disclosure are directed toward apparatuses that generate a power-related adjustment signal in response to the power signal. Digital-input-signal pads are included to communicate digital signals with a circuit external to the apparatus. Further, digital-input processing circuitry receives the digital signals from the digital-input-signal pad, and processes the received digital signals. Additionally, configuration circuitry applies the power-related adjustment signal to signals received at the digital-input-signal pad and, in response, detects the digital signals received.

Abstract: A decoder includes a first sub-decoder that receives a first level voltage set and outputs voltages selected according to lower L-bits of N-bit data, a second sub-decoder that receives a second level voltage set and outputs voltages selected according to the lower L-bits, a third sub-decoder that selects, according to higher M-bits, one voltage from the voltages selected by the first and second sub-decoders, a fourth sub-decoder that outputs voltages selected according to lower P-bits from among a third level voltage set, a fifth sub-decoder that selects one voltage selected according to higher Q-bits from the voltages output from the fourth sub-decoder, and a sixth sub-decoder that controls conduction and non-conduction based on K-bits, between one output among outputs of the first sub-decoder, and one output among outputs of the fourth sub-decoder; output of the third sub-decoder and output of the fifth sub-decoder are connected to an output terminal; the first, second, and third sub-decoders are configured

Abstract: A threshold comparator with hysteresis includes a comparator circuit, having a first input, for receiving an input voltage, a second input, and an output, which supplies an output voltage having a first value and a second value. A current generator, controlled by the output voltage, supplies a current to the first input in the presence selectively of one between the first value and second value of the output voltage. A selector circuit connects the second input of the comparator circuit to a first reference voltage source, which supplies a first reference voltage, in response to first edges of the output voltage, and to a second reference voltage source, which supplies a second reference voltage, in response to second edges of the output voltage, opposite to the first edges.

Abstract: A method and an associated apparatus for a signal rectification and timing circuit. A variable amplitude input signal is generated. An upper threshold level is determined and a lower threshold level is determined. The variable amplitude input signal and the upper threshold level are input into a first comparator. The variable amplitude input signal and the lower threshold level are input into a second comparator. A first digital output signal is generated in the first comparator using a hysteresis circuit and a second digital output signal is generated in the second comparator using a hysteresis circuit. The first digital output signal and the second digital output signal are input into a logic array. A digital level pulse output signal is generated in the logic array that has a digital transition where the variable amplitude input signal passed through a threshold level.

Abstract: In an adjustable voltage examining module, while a logic tester issues an input signal to an audio module under test, upper/low-threshold reference signals are simultaneously issued to an adjustable voltage comparing circuit. While the adjustable voltage comparing circuit receives a signal under test returned by the to-be-examined audio module after a while, the adjustable voltage comparing circuit loads both an high-threshold reference voltage and a low-threshold reference voltage respectively indicated by the reference upper/low-threshold signal so as to compare both the upper and low-threshold reference voltages with the signal under test. Therefore, while the signal under test is examined to acquire a voltage level between voltage levels of the upper and low-threshold reference signals, precise operations of the audio module under test are assured, and time wasted by continuously-issued interrupt is saved.

Abstract: In one general aspect, an apparatus can include a first voltage detect circuit configured to produce an output signal at a first power supply voltage, and configured to be in a non-monitoring state at a second power supply voltage greater than the first power supply voltage. The apparatus can include a second voltage detect circuit configured to change from a non-monitoring state to a monitoring state and configured to produce an output signal at a third power supply voltage between the first power supply voltage and the second power supply voltage. The apparatus can also include a combination circuit configured to produce a power-on-reset signal based on a logical combination of the output signal produced by the first voltage detect circuit and the output signal produced by the second voltage detect circuit.

Abstract: Methods, circuits, and systems for determining the presence of a chopped input signal are disclosed. A digital signal generator can produce multiple digital signals when an alternating current (AC) signal input reaches multiple threshold voltages. The times at which the threshold voltages are reached can be determined by looking at the times at which the digital signals go high and low. The differences between the times at which the digital signals go high and low are used to determine if the AC signal input is a leading or trailing edge chopped signal. The AC input signal is a leading edge chopped signal when the difference between the times at which the digital signals go high is less than a predetermined time threshold, and is a trailing edge chopped signal when the difference between the times at which the digital signals go low is less than a predetermined time threshold.

Abstract: A voltage sensing device with which high-precision voltage sensing is possible without the need to obtain a unique correction constant for each device. A pair of voltage input nodes NCk and NCk-1 is selected from voltage input nodes NC0-NCn in switch part 10, and they are connected to sensing input nodes NA and NB in two types of patterns with different polarity (forward connection, reverse connection). Sensing input nodes NA and NB are held at reference potential Vm by voltage sensing part 20, and current Ina and Inb corresponding to the voltage at voltage input nodes NCk and NCk-1 flows to input resistors RIk and RIk-1. Currents Ina and Inb are synthesized at different ratios in voltage sensing part 20, and sensed voltage signal S20 is generated according to the synthesized current Ic. Sensed voltage data S40 with low error is generated according to the difference between the two sensed voltage signals S20 generated in the two connection patterns.

Abstract: A decoder includes a first sub-decoder that receives a first level voltage set and outputs voltages selected according to lower L-bits of N-bit data, a second sub-decoder that receives a second level voltage set and outputs voltages selected according to the lower L-bits, a third sub-decoder that selects, according to higher M-bits, one voltage from the voltages selected by the first and second sub-decoders, a fourth sub-decoder that outputs voltages selected according to lower P-bits from among a third level voltage set, a fifth sub-decoder that selects one voltage selected according to higher Q-bits from the voltages output from the fourth sub-decoder, and a sixth sub-decoder that controls conduction and non-conduction based on K-bits, between one output among outputs of the first sub-decoder, and one output among outputs of the fourth sub-decoder; output of the third sub-decoder and output of the fifth sub-decoder are connected to an output terminal; the first, second, and third sub-decoders are configured

Abstract: A method and circuit for detecting a current and compensating for an offset voltage. The circuit includes two comparators where one of the comparators has two input terminals and the other comparator has three input terminals. An input terminal of each of the two comparators are commonly connected together, the other input terminal of the two-input comparator is coupled for receiving a first reference voltage, and a second input terminal of the three-input comparator is coupled for receiving a second reference voltage. During a first portion of the period of a sense signal the two comparators operate in a sensing mode and during a second portion of the period of the sense signal the comparator having the three input terminals operate in a current nullification mode or an offset voltage compensation mode. An offset compensation signal is generated during the second portion of the sense signal.

Abstract: A signal receiver circuit includes a first level detector for offset-controlling a first output node in response to a pair of first reference signals. A second level detector offset-controls a second output node in response to a pair of second reference signals.

Abstract: An apparatus for supplying an overdriving signal in a memory apparatus. The apparatus includes: a voltage detecting block that outputs a plurality of detection signals according to the level of an external voltage, and a pulse generator that outputs the overdriving signals having different pulse widths according to the plurality of detection signals.

Abstract: A window comparator of an A.C. input voltage, including, between two terminals of application of a voltage representative of the voltage to be measured, two first transistors of a first type, each first transistor being assembled as a current mirror on the second transistor having a first conduction terminal connected to one of the application terminals, the two second transistors having a second common conduction terminal; and two third transistors of a second type assembled as a current mirror between the common conduction terminal of the second transistors and a current source, a D.C. voltage being applied on a first terminal of the current source and an output signal being provided by a second terminal of the current source.

Abstract: A signal receiver circuit includes a first level detector for offset-controlling a first output node in response to a pair of first reference signals. A second level detector offset-controls a second output node in response to a pair of second reference signals.

Abstract: A comparator generates lower and upper reference voltages to establish an amplitude hysteresis. A first comparator circuit generates a first comparison signal indicating whether an input signal is above the upper reference voltage. A second comparator circuit generates a second comparison signal indicating whether the input signal is below the lower reference voltage. Further, the first and second comparison signals may be low-pass filtered to establish a time hysteresis. A latch is set to a first state if the first control signal indicates the input signal is above the upper reference voltage. The latch is set to a second state if the second control signal indicates the input signal is below the lower reference voltage. In some embodiments, the comparator has a rail-to-rail common mode input voltage range, a low-power mode of operation, and is self-biased to compensate for temperature, voltage, and process characteristics.

Abstract: A comparator includes a first inverter which is inserted between a power source terminal and one end of a first variable resistor, includes a first FinFET provided with a first gate terminal for receiving a positive phase output signal, and a second gate terminal for receiving a clock signal changing between a first level and a second level, inverts the positive phase output signal, and outputs a negative phase output signal, and a second inverter which is inserted between the power source terminal and one end of a second variable resistor, includes a second FinFET provided with a third gate terminal for receiving the negative phase output signal, a fourth gate terminal for receiving the clock signal, and the same polarity as the first FinFET, inverts the negative phase output signal, and outputs the positive phase output signal.

Abstract: A cascade comparator and a control method thereof are provided. By applying multi-phase clock signals to a plurality of comparators when the plurality of comparators are cascaded together so that each comparator is regenerated before the preceding comparator is reset, a hold switch does not need to be provided between the comparators. Therefore, it is possible to reduce the size and parasitic components of a circuit, operate the circuit at a high speed, remove a glitch caused by any hold switch, and accordingly improve system linearity.

Abstract: A circuit for classification of analog input signals, comprising an analog memory component, such as a floating gate, used to store a threshold value; a threshold detection module used to determine whether the analog input signal exceeds the threshold value; a time delay module used to delay a processing of the analog signal; a time-amplitude window calculation module used to determine whether an amplitude of the analog input signal is between a lower limit and an upper limit of an amplitude window; and an output module indicating whether the amplitude of the analog signal is between the lower and the upper limit, wherein the indication is used to determine whether the analog input signal belongs to one of a plurality of analog signal classes. The classification is implemented in the analog domain, eliminating the need for sampling and digitizing the analog signal, consequently minimizing circuit area and power.

Abstract: An apparatus, device, and method for loss of signal detection in a receiver are provided. A reference circuit is operable to rectify a reference signal. An input circuit is operable to rectify an input signal. A comparator is operable to compare outputs of the reference circuit and the input circuit and to generate an output signal based on the comparison. The output signal indicates whether the input signal falls within threshold limits defined by the reference signal. A second reference circuit and a second input circuit could also be used, and the reference circuits and input circuits can be selectively enabled and disabled based on which of multiple differential pairs is enabled in a receiver receiving the input signal. The differential pairs can be used in the receiver to generate an output signal based on the input signal.

Abstract: A capacitor charging circuit and method including a plurality of serially connected capacitors and parallel monitor circuits connected in parallel on a one-to-one basis to the capacitors. Each one of parallel monitor circuits applies a direct-current source voltage to a capacitor and bypasses a charge current of the capacitor when the charge voltage of the capacitor exceeds a reference voltage. Each of the parallel monitor circuits includes a reference voltage circuit, a voltage detecting circuit, a comparator, a bypass switching circuit, and a voltage limiter. The reference voltage circuit generates the reference voltage. The voltage detecting circuit detects the charge voltage of the capacitor. The comparator compares the reference voltage with an output voltage from the voltage detecting circuit and controls the bypass switching circuit to bypass the charge voltage using the voltage limiter to limit a voltage applied to the bypass switching circuit.

Abstract: An internal supply voltage generation circuit includes first and second driving circuits and a resistive device. The first driving circuit receives a feedback voltage from a first node and generates a first output voltage based on first and second reference voltages to provide the first output voltage to the first node. The first output voltage is maintained between the first and second reference voltages. The second driving circuit receives a feedback voltage from a second node voltage and generates a second output voltage based on third and fourth reference voltages to provide the second output voltage to the second node. The second output voltage is maintained between the third and fourth reference voltages, and the second output voltage of the second node is provided as an internal supply voltage. The resistive device is coupled between the first and second nodes.

Abstract: An output signal is controlled with adjustable hysteresis in response to a variable voltage input signal. One or more signals derived from the input signal are respectively compared with first and second reference voltages of different magnitudes. The output signal changes from a first state to a second state when one of the derived signals reaches a first reference voltage level threshold, and changes from the second state to the first state when a second one of the derived signals reaches a second reference level voltage threshold. A first derived signal may be varied to have a voltage magnitude that is greater or lesser than the voltage magnitude of a second derived signal while maintaining a positive hysteresis level. The circuit may be configured to output a signal representing an undervoltage and/or overvoltage condition of the input signal.

Abstract: Circuitry including a BGREF (bandgap voltage reference) comparator including a plurality of MOS transistors that compare a resistor divided supply voltage to a function of at least two process parameter voltages.

Abstract: A capacitor charging circuit and method including a plurality of serially connected capacitors and parallel monitor circuits connected in parallel on a one-to-one basis to the capacitors. Each one of parallel monitor circuits applies a direct-current source voltage to a capacitor and bypasses a charge current of the capacitor when the charge voltage of the capacitor exceeds a reference voltage. Each of the parallel monitor circuits includes a reference voltage circuit, a voltage detecting circuit, a comparator, a bypass switching circuit, and a voltage limiter. The reference voltage circuit generates the reference voltage. The voltage detecting circuit detects the charge voltage of the capacitor. The comparator compares the reference voltage with an output voltage from the voltage detecting circuit and controls the bypass switching circuit to bypass the charge voltage using the voltage limiter to limit a voltage applied to the bypass switching circuit.

Abstract: A charge balancing modulation system for digitizing the output of a variable impedance sensor utilizes synchronous excitation of the input sensor and AC coupling of the analog input signal. The modulation system also implements correlated double sampling to provide low noise and highly accurate analog-to-digital conversions. In one embodiment, the modulation system includes an excitation source for providing a switched current to the input sensor and generating an input voltage step in response, and an integrator including an input capacitor, an amplifier and an accumulation capacitor. The input capacitor AC couples the analog input signal to the integrator. The integrator is controlled by switches operating in complementary state for enabling correlated double sampling operation or enabling data dependent charge accumulation operation. The modulation system generates an output data stream exhibiting a ones density proportional to the magnitude of the average input voltage step.

Abstract: In a computer system, a passive component minimization of connector pins configuration includes a motherboard and daughterboard. The daughterboard includes a selection switch coupled via passive components to a single connector pin, according to a prescribed state of multiple states of the daughterboard. In one embodiment, the passive components include three series connected resistors collectively coupled to the daughterboard connector pin. The motherboard includes a supply voltage and pull-up resistor circuit coupled to a single connector pin, and further includes decoding circuitry coupled to the motherboard connector pin for decoding a voltage level of the motherboard connector pin into binary data.

Abstract: Circuitry is disclosed for detection of open inputs on an enhanced differential receiver. A pulldown terminator is coupled to the inputs of the enhanced differential receiver. If the differential inputs are not actively driven, the voltage on both differential inputs will be pulled to a predetermined voltage. When the voltage on the differential inputs reach a reference voltage, an active device detects that the reference voltage has been reached, and produces a predetermined logic value on an output of the enhanced differential receiver. The enhanced differential receiver is not subject to oscillation when not actively driven. Delay through the enhanced differential receiver is not substantially greater than delay through a conventional differential receiver consisting of only a differential amplifier.

Abstract: A power level detection circuit detects the voltage level of a power source. The power level detection circuit has a first voltage level detector having an input coupled to the power source and outputting a first signal representative of an upper boundary, a second voltage level detector having an input coupled to the power source and outputting a second signal representative of a desired detection level, and a third voltage level detector having an input coupled to the power source and outputting a third signal representative of a lower boundary. The power level detection circuit also has a control circuit coupled to the first, second and third signals for outputting a power level detection signal if there is a change in the second signal, and when the power level is greater than the level of the third signal and less than the level of the first signal.

Abstract: A receiver circuit is connected to a differential serial bus having first and second signal conductors. The receiver circuit includes a fault detection circuit which generates a difference signal representing a difference between a first signal on the first conductor and a second signal on the second conductors. A comparing circuit includes a plurality of comparators for comparing the difference signal, the first signal and the second signal to predetermined voltage levels. The comparing circuit also includes a plurality of logic units coupled to outputs of the comparators. A signal select circuit has a pair of inputs coupled to the first and second conductors, logic inputs coupled to logic outputs of the comparing circuit, and a signal output. The signal select circuit and the comparing circuit cooperate to control communication of the first and second conductors with the signal output as a function of fault conditions on the first and second conductors.

Abstract: An A/D converter having a plurality of thresholding circuits corresponding to bits of output digital data, each of which includes odd number of inverters serially connected from a first stage to a last stage. The first stage inverter of the thresholding circuits have thresholds equal to a weights of the bits. The inverters of the last stage are of thresholds different from those of the first stage.

Abstract: A signal reception apparatus in the spread spectrum communication system requires only a small amount of circuitry and consumes a small amount of electric power. A quadrature detector decomposes received signals into in-phase components and quadrature components, and supplies them to a complex-type matched filter. The complex-type matched filter de-spreads the in-phase components and the quadrature components and sends them to a multi-path selector. The multi-path selector selects, from among the received de-spread signals, multiple paths having high levels of signal electric powers and sends the received signals of the selected paths to multiple phase correction blocks. Analog operation circuits calculate phase errors of the received signals of two successive pilot symbol blocks for each path. An analog operation circuit corrects the phases of the received signals of the information symbol block that has been received between the two successive pilot symbol blocks.

Abstract: A discriminator capable of generating a multi-level signal with less restrictions is provided. In a discriminator D1, a wave-shaping circuit 3 shapes the waveform of one branched multi-level signal MS, according to a control signal CS from a control signal generator 10 so that a detector 4 that follows the wave-shaping circuit 3 can correctly detect a first reference level RL1. The detector 4 detects the first reference level RL1 from an output signal OS3 from the wave-shaping circuit 3. A reference level generator 5 generates a second reference level RL2 of the multi-level signal MS. A threshold generator 6 generates thresholds Th1, Th2, and Th3 as much as required according to the first and second reference levels RL1 and RL2. Comparators 82 to 84 compares the amplitude of the other branched multi-level signal MS with the thresholds Th1, Th2, and Th3. A control signal generator 10 generates a control signal CS according to the comparison results from the comparators 82 to 84.

Abstract: A circuit arrangement for evaluating a binary signal defined by two current thresholds, particularly the output signal of an active sensor [(1′)], comprises a current source [(IQ′_,IQ11,IQ12,IQ13)] that can consist of individual current sources and is connected in series to the signal source, namely the sensor [(1′)]. The current source is inserted between the battery terminal [(IGW)] and the sensor terminal [(A1)] and serves simultaneously as a current limiter in case of a short circuit between the sensor terminal [(A1)] and ground [(GND)].

Abstract: A three input comparator facilitates the comparison of a signal to the greater of two different reference voltages in a manner which mitigates propagation delay. A first differential pair of transistors facilitates comparison of the two reference voltages to one another, while second and third differential pairs of transistors facilitate comparison of the signal to the higher of the two reference voltages.

Abstract: A sense-amplifier circuit comprising a plurality of sub-sense-amplifiers corresponding to respective reference potentials can operate fast when used for a multivalued information memory. The sense amplifier circuit is composed of sub-sense-amplifiers having different polarities according to corresponding reference potentials: a sub-sense-amplifier SN3 having the highest reference potential is of N (polarity) type and a sub-sense-amplifier SP1 having the lowest reference potential is of P (polarity) type. All sub-sense-amplifiers can operate according to improved characteristics assuring a reduced access time.

Abstract: An input buffer of the present invention includes: a plurality of receiver circuits for performing different phase adjustments on an input signal, and outputting the differently phase-adjusted signals; a pattern detection circuit for detecting a period of time for which a voltage of the input signal has remained unchanged; and a signal selection circuit for selecting one of the output signals received from the receiver circuits based on the detection result from the pattern detection circuit.

Abstract: At least two level detectors compare a multilevel signal to respective prescribed voltage levels to produce corresponding streams of bits. These bit streams are repeatedly delayed in respective digital delay lines, and bits from the digital delay lines are output in parallel to multilevel decoder logic. The multilevel decoder logic converts the parallel bits into a plurality of corresponding two-level decoded bits and performs error detections for an invalid transition in the multilevel signal. The decoded bits may be descrambled and block decoded.

Abstract: A dual-threshold voltage comparator circuit utilizes a single input pin of an integrated circuit and an external resistor network. Appropriate selection of the resistors comprising the resistor network permits independent setting of the dual thresholds of the comparator.

Abstract: A multivalued FSK demodulation window comparator includes an MSB comparator, an LSB comparator, a reception electric field strength detector, and a reference voltage generating circuit. The MSB comparator determines at least the polarity of a frequency shift of a radio frequency. The LSB comparator determines the absolute value of the frequency shift of the radio frequency. The reception electric field strength detector detects the strength of a radio signal and outputs a signal corresponding to the detected strength. The reference voltage generating circuit changes the reference voltages of the LSB comparator in accordance with an output voltage from the reception electric field strength detector. When the output voltage from the reception electric field strength detector is not higher than a predetermined level, a reference voltage from the reference voltage generating circuit changes.

Abstract: A comparator including one or more transconducting inverters, each inverter biased to operate in a subthreshold state so as to have a desired high transconductance. In preferred embodiments, the transconducting inverter is biased in subthreshold by a bias voltage whose value is independent of process and environmental variations (so that the subthreshold current density in the inverter remains fixed despite supply voltage variations and other process and environmental variations). The bias voltage is generated by servoing an unregulated supply voltage so that the bias voltage has lower magnitude (relative to ground potential) than the supply voltage. The reduced-magnitude, regulated bias voltage precisely regulates at least one transistor in each inverter by forcing a constant current density therein, thereby causing the cell to operate in subthreshold.

Abstract: An image processor includes a quantizing unit which quantizes input image data to data of at least three or more levels. A memory stores the quantized data on a picture unit basis, and an output unit outputs the stored image on the picture unit basis. The quantizing unit quantizes the image data of a present picture in accordance with the quantized data of a previous picture stored in the memory, and quantizes the input image data of one pixel to the data of three or more levels by using a plurality of threshold values each including an upper threshold value, a standard threshold value and a lower threshold value.

Abstract: In an interface circuit having a transmitting side circuit, a receiving side circuit and a transmission path connecting the transmitting side circuit and the receiving side circuit in a transmission system for transmitting a predetermined signal between the transmitting and receiving sides, the receiving side circuit has a receiver circuit having threshold control section for independently controlling a logical threshold value corresponding to rise of a received transmitting signal from low level to high level and a logical threshold value corresponding to fall of the received transmitting signal from high level to low level, and a control circuit for controlling the logical threshold values of the receiver circuit through the threshold control section in response to a voltage change in the transmitting signal.