Abstract: An integrated circuit with a power-on-reset circuit includes an inverter circuit connected between the first and second supply node, a cascode-connected series of transistors MCn, for n going from 1 to N, connected between the first supply node and the input node of the inverter, and a resistive element connected between the input node of the inverter and the second supply node. The transistors in the cascode-connected series of transistors MCn pull up the input node voltage above a trip point voltage when the voltage between the input node and the first supply node is more than a threshold of the cascode-connected series. A circuit connected between the first and second supply nodes is responsive to a POR pulse output by the inverter.

Abstract: A fraud detecting method for use in an in-vehicle network system including a plurality of electronic control units that communicate with each other via a network includes detecting whether a state of a vehicle satisfies a first condition or a second condition, and switching, upon detecting that the state of the vehicle satisfies the first condition or the second condition, an operation mode of a fraud-sensing electronic control unit connected to the network between a first mode in which a first type of detecting process for detecting a fraudulent message in the network is performed and a second mode in which the first type of detecting process is not performed.

Abstract: A method and a device for defibrillation. When a shock is generated, energy is transmitted from the low-voltage range to a high-voltage range, at least one current surge being generated in the low-voltage range, stepped up to the high-voltage range and guided to electrodes. An energy supply, power electronics and an energy storage device are used in the low-voltage range.

Abstract: A computing system can be dynamically configured to operate with an eGPU that is connected to the computing system via a USB-C port. An eGPU manager, which may be a BIOS service, can be provided on a computing system and configured to detect when an eGPU has been connected to a USB-C port. When the eGPU manager detects an eGPU, it can employ an identifier of the eGPU and possibly characteristics of the eGPU and/or the computing system to query a lookup table for values for configuration settings that are optimal for the particular eGPU. The eGPU manager can then set the configuration settings to the obtained values so that the computing system will boot and/or operate properly while the eGPU is connected.

Abstract: A voltage detector (200) for monitoring an input signal and outputting a detection signal at an output when a voltage of the input signal meets a first threshold having: an input configured for receiving the input signal; a voltage reference circuit for receiving an input voltage and producing a reference voltage having a maximum value independent of the input voltage; and a trigger configured to compare the input signal and the reference voltage and to output a detection signal to the output when the voltage of the input signal reaches the first threshold. The voltage reference circuit comprises a reset input connected to either the input or the output and is configured to reduce the reference voltage when a predetermined reset signal is received.

Abstract: A method includes selecting at least one first voltage that defines subsets of DC voltages from among an ordered set of DC voltages, comparing the first voltage with a DC reference voltage, selecting one of the subsets based on a result of the comparing, and comparing each voltage of the selected subset with the reference voltage.

Abstract: A semiconductor apparatus includes a reference voltage generating circuit and a buffer. The reference voltage generating circuit may generate, based on a voltage setting signal, a first reference voltage and a second reference voltage, which has the same level as the first reference voltage or has a lower level than the first reference voltage by an amount of a unit level. The buffer may generate an output signal based on the first reference voltage, the second reference voltage and an input signal.

Abstract: Methods and systems are described for receiving a sampling signal, pre-charging a pair of output nodes prior to a sampling interval, initiating the sampling interval by enabling a current source according to a first transition of the received sampling signal, generating a differential output voltage at the pair of output nodes by discharging the pair of output nodes according to a differential input signal, the pair of output nodes discharged according to current drawn by the current source during the sampling interval, terminating the sampling interval by disabling the current source in response to a second transition of the received sampling signal, and inhibiting a recharge of the pair of output nodes for a hold time after termination of the sampling interval and prior to initiation of a subsequent sampling interval.

Abstract: A signal processing chain, such as an audio chain, produces an analog output signal from a digital input signal. The signal processing chain is operated by generating a first flag signal for the analog output signal and one or more second flag signals for the digital input signal. Each flag signal assumes a first level or a second level and is set to the first level when a signal from which the flag is generated has a value within an amplitude window. An amount the first flag signal for the analog output signal and the second flag signal for the digital input signal match each other may be calculated for issuing an alert flag which indicates an impaired operation of the signal processing chain.

Abstract: Methods and systems are described for receiving a sampling signal, pre-charging a pair of output nodes prior to a sampling interval, initiating the sampling interval by enabling a current source according to a first transition of the received sampling signal, generating a differential output voltage at the pair of output nodes by discharging the pair of output nodes according to a differential input signal, the pair of output nodes discharged according to current drawn by the current source during the sampling interval, terminating the sampling interval by disabling the current source in response to a second transition of the received sampling signal, and inhibiting a recharge of the pair of output nodes for a hold time after termination of the sampling interval and prior to initiation of a subsequent sampling interval.

Abstract: The disclosure relates to an integrated circuit comprising: a first voltage terminal; a second voltage terminal; and a plurality of logic cells, comprising one or more field effect transistors having a p-type channel and one or more field effect transistors having an n-type channel. The plurality of logic cells comprises a regular subset of cells and a spare subset of cells. Electrical connectors are arranged to: connect the gates of the regular subset of cells in order to provide a functional logic arrangement; connect the gates of the one or more field effect transistors having a p-type channel of the spare subset of cells to the first voltage terminal; and connect the gates of the one or more field effect transistors having an n-type channel of the spare subset of cells to the second voltage terminal.

Abstract: A nonvolatile memory device includes a memory cell array that stores data, and control logic. The control logic is configured to control a read operation, a program operation, or an erase operation on the data. The control logic is configured to detect a first power noise based on one of voltage sources to be provided to the memory cell array and a first reference voltage and detect a second power noise based on the one voltage source of the voltage sources and each of the first reference voltage and a second reference voltage. The control logic is configured to determine whether to perform at least one of an operation period of the read operation, an operation period of the program operation, or an operation period of the erase operation, based on whether at least one of the first and second power noises is detected.

Abstract: A low dropout voltage (LDO) regulator including: a coarse loop circuit configured to receive an input voltage, generate a coarse code and adjust a coarse current according to the coarse code; a digital controller configured to receive the coarse code and generate a fine loop control signal according to the coarse code; and a fine loop circuit configured to receive the input voltage and the fine loop control signal and adjust a fine current according to the input voltage and the fine loop control signal, wherein the coarse current and the fine current adjust a level of an output voltage.

Abstract: A signal level detector comprising and a Burst-Mode Trans Impedance Amplifier (BM-TIA) using the same. The signal level detector includes a level detector configured to detect peak voltage of an input voltage signal, a reference voltage generator configured to generate second reference voltage by receiving first reference voltage, a comparator configured to compare the peak voltage and the second reference voltage and output a discrimination value according to a comparison result, and a latch configured to store the differential output from the comparator, wherein the level detector and the reference voltage generator have differential amplifier in the same structure.

Abstract: A mode-controlled voltage excursion detector apparatus for monitoring a supply voltage of a power supply applied to a load and a method of operating thereof is described. A voltage monitor is configured to detect an excursion event if the supply voltage exceeds or falls below at least one defined threshold, to generate an excursion event signal upon detection of the excursion event and to provide the generated excursion event signal to the excursion event output for being outputted via an excursion event output. A sensitivity control module is configured to receive a signal indicative of potential voltage excursions. A sensitivity control module is further operatively coupled to the sensitivity control input and configured to disable the outputting of an excursion event signal generated during a defined period of time in response to the reception of the signal, which triggers the disabling of the outputting.

Abstract: There is provided a human interface device including a control chip and a plurality of control components. The control chip includes a voltage detection circuit coupled to the plurality of control components via a multiplexing pin and detects a voltage value on the multiplexing pin through the voltage detection circuit thereby identifying an operating state of the plurality of control components.

Abstract: A power selector for switching power supplies is implemented using a variety of methods and devices. According to an example embodiment of the present disclosure, an arrangement provides power to a circuit by selecting between a first supply and a second supply. The first power circuit provides a regulated level of power to the integrated circuit (IC) having an operating power level specified as a circuit operating level for providing power to the IC. The second power circuit provides power to the IC. A power-signal arbitration circuit for assessing VDDREG and whether the second power circuit is to provide power to the IC as an alternative to the first power circuit providing power to the IC is based on a threshold power level indicative of the specified operating power level and the regulated level of power. Based on the power-signal arbitration circuit's assessment, providing an arbitration-control signal to the power-signal switching circuit.

Abstract: The present invention relates to a watchdog timer dedicated to the display controller of a voltage detector wherein the watchdog determines a malfunction in the microcontroller and triggers a visual warning to be displayed via the display controller. This prevents inaccurate voltage information from being displayed in the case of a microcontroller malfunction and thereby the user from being exposed to the risk of extreme injury through, for example, a high-voltage shock.

Abstract: A key press detecting circuit and method detect the status of multiple keys through a single pin. In an embodiment, a constant current is provided to apply to a key module through a single pin, to generate a voltage at the single pin that is related to the equivalent resistance of the key module observed from the single pin, and the voltage of the single pin is compared with a set of reference values to identify the status of the plurality of keys. In another embodiment, a variable current is provided to apply to a key module through a single pin in such a way that the variable current is adjusted to maintain a constant voltage at the single pin, and the variable current is compared with a set of reference values to identify the status of the plurality of keys.

Abstract: A state-detection circuit facilitates the detection of the state of an input pin relative to several different types of input circuits. According to an example embodiment, a state-detection circuit includes a plurality of comparators and circuit components, configured to provide a plurality of binary output signals that collectively indicate a state of an input pin to which the comparators are coupled. The state-detection circuit is configured to facilitate the detection of several different types of input circuits, based upon the binary output signals.

Abstract: Techniques for obtaining a propagation delay through first and second transmission lines having substantially equal propagation delays may include: providing a first signal to the first transmission line; providing a second signal to the second transmission line; detecting an incident edge of the first signal on the first transmission line; detecting a reflected edge of the second signal on the second transmission line; and determining the propagation delay based on times of detection of the incident edge and detection of the reflected edge.

Abstract: Methods and circuits for undiscoverable physical chip identification are disclosed. Embodiments of the present invention provide an intrinsic bit element that comprises two transistors. The two transistors form a pair in which one transistor has a wide variability in threshold voltage and the other transistor has a narrow variability in threshold voltage. The wide variability is achieved by making a transistor with a smaller width and length than the other transistor in the pair. The variation of the threshold voltage of the wide variability transistor means that in the case of copies of intrinsic bit elements being made, some of the “copied” wide variability transistors will have significantly different threshold voltages, causing some of the intrinsic bit elements of a copied chip to read differently than in the original chip from which they were copied.

Abstract: A rail-to-rail comparator including a first comparison unit connected to a first terminal and configured to compare differential input signals to differential reference voltages; a second comparison unit connected to a second terminal and configured to compare the differential input signals to the differential reference voltages; and an output unit configured to be driven in response to a clock signal and to generate a complementary output signal according to comparison results of the first and second comparison units.

Abstract: A key press detecting circuit and method detect the status of multiple keys through a single pin. In an embodiment, a constant current is provided to apply to a key module through a single pin, to generate a voltage at the single pin that is related to the equivalent resistance of the key module observed from the single pin, and the voltage of the single pin is compared with a set of reference values to identify the status of the plurality of keys. In another embodiment, a variable current is provided to apply to a key module through a single pin in such a way that the variable current is adjusted to maintain a constant voltage at the single pin, and the variable current is compared with a set of reference values to identify the status of the plurality of keys.

Abstract: A comparator includes a first comparison unit configured to compare an input signal with a first signal and a second comparison unit configured to compare the input signal with a second signal having a voltage value lower than a voltage value of the first signal in a case where a voltage value of the input signal is lower than the voltage value of the first signal and compare the input signal with a third signal having a voltage value higher than a voltage value of the first signal in a case where a voltage value of the input signal is higher than the voltage value of the first signal.

Abstract: A voltage detecting system is configured for detecting a voltage supplied to an electronic device. The voltage detecting system includes a voltage measuring circuit configured to measure the voltage, a voltage converting circuit electrically coupled to the voltage, and a voltage comparing circuit. The voltage measuring circuit has a first measuring range and a second measuring range that is wider than the first measuring range. The voltage converting circuit is capable of the converting the voltage to an output voltage according to a predetermined ratio. The voltage comparing circuit compares the output voltage with a reference voltage. If the output voltage is greater than the reference voltage, the voltage comparing circuit informs the voltage measuring circuit to select the second measuring range. If the output voltage is not greater than the reference voltage, the voltage comparing circuit informs the voltage measuring circuit to select the first measuring range.

Abstract: A sensing circuit having a reduced bias clamp and method of operating the sensing circuit are provided. The sensing circuit may include a reference path and a sensing path. The sensing path may include a first transistor, clamping capacitor and a pair of switches. The reference path may include a second transistor, clamping capacitor and another pair of switches. A common gain stage receiving a bias voltage charges the clamping capacitors for the respective paths in a charging mode. The clamping capacitors may be charged in a serial or partially parallel manner during the charging mode. Each path may be coupled to a comparator, which may sense current or voltage changes between the paths during a sense mode. The sensing circuit may be configured to provide for sensing current or voltage changes between multiple sensing and/or reference paths in a parallel or serial manner.

Abstract: A switching regulator circuit and a reference compensation module employed for compensating a reference signal in the switching regulator circuit. The switching regulator circuit with a reference ground having an average offset voltage referenced to a package ground pin, wherein the average offset voltage is proportional to an output current of the switching regulator circuit with a first factor. The reference compensation module may be configured to receive a second reference signal having a bandgap reference voltage with respect to the reference ground and a reference compensation signal proportional to the output current with a second factor, and configured to provide the first reference signal based on compensating the second reference signal with the reference compensation signal to substantially cancel out the average offset voltage from the first reference signal with respect to the ground pin.

Abstract: A power supervisor circuit is provided. The circuit includes a first sample circuit that periodically samples a first reference voltage derived from a high output rail of a voltage source and generates a first sampled output voltage. The circuit includes second sample circuit that periodically samples a second reference voltage associated with a low output rail of the voltage source and generates a second sampled output voltage. A voltage supervisor in the circuit generates a trip point signal when a combination of the first and second sampled output voltage crosses a predetermined threshold indicating that the voltage source output voltage has fallen below a desired output voltage.

Abstract: A power supervisor circuit is provided. The circuit includes a first sample circuit that periodically samples a first reference voltage derived from a high output rail of a voltage source and generates a first sampled output voltage. The circuit includes second sample circuit that periodically samples a second reference voltage associated with a low output rail of the voltage source and generates a second sampled output voltage. A voltage supervisor in the circuit generates a trip point signal when a combination of the first and second sampled output voltage crosses a predetermined threshold indicating that the voltage source output voltage has fallen below a desired output voltage.

Abstract: An integrated circuit includes a plurality of semiconductor devices. Each of the semiconductor devices includes an internal voltage generation unit configured to generate a plurality of internal voltages, a voltage select output unit configured to output a default voltage of a plurality of internal voltages to a preset pad in response to an initial value of a select code, and selectively output the other voltages of the plurality of internal voltages to the pad in response to variations of the select code, and a stack operation control unit configured to control the voltage select output unit to output the default voltage to the pad in response to a stack signal and a predetermined value of the select code, instead of the initial value of the select code, and whether or not to activate the stack signal is determined according to whether or not the plurality of semiconductor devices are stacked.

Abstract: A circuit for detecting out-of-band signals is disclosed. In one embodiment, the circuit includes a first differential circuit configured to level shift and positively rectify a differential input signal to produce a first output component of a differential output signal. The detector further includes a second differential circuit configured to level shift and negatively rectify the differential input signal to produce a second output component of the differential output signal. A third differential circuit is configured to level shift and output first and second fixed voltages based on an input reference voltage and a ground voltage. The circuit is configured to provide the differential output signal and the first and second fixed voltages to an indicator circuit configured to assert an indication responsive to detecting that a differential voltage of the differential output signal is greater than a differential voltage of the first and second fixed voltages.

Abstract: A level sensitive comparing device includes: a first comparator, a second comparator, and a determination circuit. The first comparator is arranged for comparing an input signal with a first reference level to generate a first comparison signal. The second comparator is arranged for comparing the input signal with a second reference level to generate a second comparison signal, wherein the second reference level is different from the first reference level. The determination circuit is coupled to the first comparator and the second comparator, and is arranged for determining whether the first comparison signal is allowed to appear at an output of the level sensitive comparing device according to at least the first comparison signal and the second comparison signal, wherein the determination circuit is composed of digital components only.

Abstract: The present invention discloses a power supply input voltage detection circuit. The power supply converts an input voltage to an output voltage by a transformer which includes a primary winding and a secondary winding. The primary winding is coupled to a power switch, which receives a switching signal to adjust the output voltage. The power switch is coupled to a sensing circuit; when the power switch turns ON, the sensing circuit generates a current sense signal according to current through the primary winding. The input voltage detection circuit includes: a rising time detection circuit, which detects a period, of time during which the current sense signal rises from a low reference level to a high reference level to generate a timing signal; and a determination circuit, which generates a determination signal according to the timing signal for determining whether the input signal is a high voltage or a low voltage.

Abstract: Aspects of the instant disclosure are directed toward apparatuses that generate a power-related adjustment signal in response to the power signal. Digital-input-signal pads are included to communicate digital signals with a circuit external to the apparatus. Further, digital-input processing circuitry receives the digital signals from the digital-input-signal pad, and processes the received digital signals. Additionally, configuration circuitry applies the power-related adjustment signal to signals received at the digital-input-signal pad and, in response, detects the digital signals received.

Abstract: Several circuits and methods for field-based communication are provided. In an embodiment, a field-based communication circuit includes a receiver circuit, a detection circuit and a control circuit. The receiver circuit is configured to receive a field input signal from a field source. The detection circuit includes a voltage detection circuit and a current detection circuit configured to detect a voltage signal and a current signal, respectively associated with the field input signal. The control circuit is configured to trigger a selection of one of the voltage detection circuit and the current detection circuit based on a detection of a signal magnitude of one of the voltage signal and the current signal relative to at least a first predetermined threshold level, wherein the selection of one of the voltage detection circuit and the current detection circuit facilitates a demodulation of one of the voltage signal and the current signal.

Abstract: An integrated circuit includes a plurality of semiconductor devices. Each of the semiconductor devices includes an internal voltage generation unit configured to generate a plurality of internal voltages, a voltage select output unit configured to output a default voltage of a plurality of internal voltages to a preset pad in response to an initial value of a select code, and selectively output the other voltages of the plurality of internal voltages to the pad in response to variations of the select code, and a stack operation control unit configured to control the voltage select output unit to output the default voltage to the pad in response to a stack signal and a predetermined value of the select code, instead of the initial value of the select code, and whether or not to activate the stack signal is determined according to whether or not the plurality of semiconductor devices are stacked.

Abstract: In some embodiments, a reset circuit for an electronic circuit equipped with a backup power capacitor includes a first detector arranged to detect a predetermined first voltage of the backup capacitor, a second detector arranged to detect a predetermined second voltage of the backup capacitor, the second voltage being lower than the first voltage, and a controller arranged to control an output of a reset request signal based on detection results of the first detector and the second detector. The controller is configured to output the reset request signal when the first detector detects the first voltage after the second detector detected the second detector.

Abstract: Methods and circuits for undiscoverable physical chip identification are disclosed. Embodiments of the present invention provide an intrinsic bit element that comprises two transistors. The two transistors form a pair in which one transistor has a wide variability in threshold voltage and the other transistor has a narrow variability in threshold voltage. The wide variability is achieved by making a transistor with a smaller width and length than the other transistor in the pair. The variation of the threshold voltage of the wide variability transistor means that in the case of copies of intrinsic bit elements being made, some of the “copied” wide variability transistors will have significantly different threshold voltages, causing some of the intrinsic bit elements of a copied chip to read differently than in the original chip from which they were copied.

Abstract: A system and method for providing an accurate current reference using a low-power current source is disclosed. A preferred embodiment comprises a system comprises a first section and a second section. The first section comprises a first simple current reference, an accurate current reference, and a circuit that generates a digital error signal based upon a comparison of an output of the first simple current reference and an output of the accurate current reference. The second section comprises a second simple current reference providing a second reference current, an adjustment circuit providing an adjustment current based upon the digital error signal, and a circuit biased with current equivalent to a summation of the second reference current and the adjustment current. The first simple current reference and the second simple current reference may be equivalent circuits.

Abstract: A key press detecting circuit and method detect the status of multiple keys through a single pin. In an embodiment, a constant current is provided to apply to a key module through a single pin, to generate a voltage at the single pin that is related to the equivalent resistance of the key module observed from the single pin, and the voltage of the single pin is compared with a set of reference values to identify the status of the plurality of keys. In another embodiment, a variable current is provided to apply to a key module through a single pin in such a way that the variable current is adjusted to maintain a constant voltage at the single pin, and the variable current is compared with a set of reference values to identify the status of the plurality of keys.

Abstract: A first embodiment of the present invention is a system for generating a voltage comprising a comparator operable to compare an operation voltage to a reference voltage, control logic operable to selectively output as a control signal an incremented signal or a decremented signal based on a comparison of the operation voltage to the reference voltage by the comparator, and a device module operable to increase or decrease the operation voltage based on the control signal.

Abstract: Circuitry includes a pre-amplifier having a differential output, where the differential output corresponds to a common mode voltage; a multiplexer including sets of transistors, each of which has a control input; a comparator including input terminals, a first terminal of the input terminals to receive a signal that is based on an output of the multiplexer, and a second terminal of the input terminals to receive a threshold voltage; a compensation circuit to produce a divided voltage that varies in accordance with variations in the common mode voltage; and an amplifier to receive a predefined voltage and to use the divided voltage to affect the predefined voltage to produce the threshold voltage for the comparator. Signals in the differential output of the pre-amplifier are applicable to corresponding control inputs in the sets of transistors.

Abstract: In a power detector, a comparator for detection receives an input signal and a reference voltage, and compares the input signal to the reference voltage around the switching time of active and inactive states of the output of the comparator in accordance with an output of an input switching signal generator. Except for the switching time, an input voltage for non-use of the comparator is inputs to the comparator for detection, and the differential inputs are fixed to the same potential. Therefore, aging reduction in the accuracy of power detection caused by BT degradation is effectively mitigated.

Abstract: A method and an associated apparatus for a signal rectification and timing circuit. A variable amplitude input signal is generated. An upper threshold level is determined and a lower threshold level is determined. The variable amplitude input signal and the upper threshold level are input into a first comparator. The variable amplitude input signal and the lower threshold level are input into a second comparator. A first digital output signal is generated in the first comparator using a hysteresis circuit and a second digital output signal is generated in the second comparator using a hysteresis circuit. The first digital output signal and the second digital output signal are input into a logic array. A digital level pulse output signal is generated in the logic array that has a digital transition where the variable amplitude input signal passed through a threshold level.

Abstract: A circuit for detecting out-of-band signals is disclosed. In one embodiment, the circuit includes a first differential circuit configured to level shift and positively rectify a differential input signal to produce a first output component of a differential output signal. The first differential circuit is further configured to generate and provide a common mode voltage of the differential input signal as a second component of the differential output signal. The circuit further includes a second differential circuit configured to level shift and output first and second fixed voltages based on an input reference voltage and a ground voltage. The circuit is configured to provide the differential output signal and the first and second fixed voltages to an indicator circuit configured to assert an indication responsive to detecting that a differential voltage of the differential output signal is greater than a differential voltage of the first and second fixed voltages.

Abstract: According to one embodiment, a semiconductor integrated circuit includes a semiconductor integrated circuit a voltage regulator providing a prescribed power-supply voltage, a plurality of delay test circuits, each of the delay test circuits being configured in each of areas where electrical current flows in response to each of operation modes, a test control unit executing a delay test using the delay test circuit under a test mode while decreasing a power-supply voltage in a stepwise fashion, a supply voltage decision unit deciding the power-supply voltage of the operation mode on a basis of the delay test, a memory unit storing the power-supply voltage of each operation mode, a supply voltage configuration unit reading out the power-supply voltage corresponding to the operation mode from the memory unit, and the supply configuration unit arranging the power-supply voltage as an output voltage of the voltage regulator when each of the operation modes starts to execute.

Abstract: A device for sensing a binary signal includes a device configured to measure a signal level of the signal, a device configured to determine whether the measured signal level is “low” or “high”, a device configured to provide a variable input impedance, and a device configured to control the input impedance in response to the measured signal level. The variable input impedance may be provided by way of a transistor and a resistor, and by controlling the duty ratio of the transistor using pulse width modulation. Preferably, the input impedance is controlled to be low for low signal levels and to be high for high signal levels, which results in a more reliable sensing of binary signals. The device may be used for detecting the state of contact transducers suffering from parasitic resistances caused by moist and/or polluted environments. Further, a method of sensing a binary signal is provided.

Abstract: In an adjustable voltage examining module, while a logic tester issues an input signal to an audio module under test, upper/low-threshold reference signals are simultaneously issued to an adjustable voltage comparing circuit. While the adjustable voltage comparing circuit receives a signal under test returned by the to-be-examined audio module after a while, the adjustable voltage comparing circuit loads both an high-threshold reference voltage and a low-threshold reference voltage respectively indicated by the reference upper/low-threshold signal so as to compare both the upper and low-threshold reference voltages with the signal under test. Therefore, while the signal under test is examined to acquire a voltage level between voltage levels of the upper and low-threshold reference signals, precise operations of the audio module under test are assured, and time wasted by continuously-issued interrupt is saved.

Abstract: An input buffer with a reduced sensitivity to an externally generated reference voltage includes: a first input coupled between a first load and ground, the first input being an externally generated reference voltage; a second input coupled between a second load and ground, for generating an output; and a third input coupled in parallel to the first input, the third input being an internally generated reference voltage. The output switches between high and low or vice versa when the second input exceeds a switching point which is an average of the first input and the third input according to the relative size of the first input and the third input.