Abstract: A signal reception apparatus has an automatic level selection function. A comparing circuit compares a level of an input signal with a plurality of sensing levels and outputs a plurality of sensing signals in accordance with the compared result. An auto select level controller receives the plurality of sensing signals from the comparing circuit and selects one of the plurality of sensing levels in response to the plurality of sensing signals. The auto select level controller includes a plurality of flip flop stages. Each of the plurality of flip flop stages has a plurality of flip flops connected in series and is coupled to a corresponding one of the plurality of sensing signals from the comparing circuit. A circuit receives the output signals from the plurality of flip flop stages and selects one of the plurality of sensing levels in response to the inputted sensing signals.

Abstract: An analog type multistage switching circuit with a small circuit size and a small consumed electric power to having a plurality of thresholding circuits arranged in parallel to which an input voltage and a reference voltage are impressed through capacitive couplings which add the input voltage and reference voltage with weighting.

Abstract: A computational circuit wherein addition is performed by a capacitive coupling or resistive coupling circuit. A quantizing circuit is realized by plurality of thresholding circuit receiving analog input voltages. Each thresholding circuit includes an inverter and a capacitive coupling circuit.

Abstract: In an analog-to-digital converter, a plurality of divided output currents are produced by dividing at a predetermined ratio each of a plurality of comparison output currents that are produced for each reference potential, and an output voltage generated by each divided comparison output current is further divided by an output means into a plurality of output voltages. A combination of output voltages which are in reversed-phase, and the relationship of which in magnitude is reversed at an intermediate potential between first and second reference potentials, is selected from the plurality of output voltages produced by the above division. According to this construction, comparison outputs of an input analog signal with respect to arbitrary virtual potentials between the two reference potentials actually given can easily be obtained.

Abstract: In an analog-to-digital converter, a plurality of divided output currents are produced by dividing at a predetermined ratio each of a plurality of comparison output currents that are produced for each reference potential, and an output voltage generated by each divided comparison output current is further divided by an output means into a plurality of output voltages. A combination of output voltages which are in reversed-phase, and the relationship of which in magnitude is reversed at an intermediate potential between first and second reference potentials, is selected from the plurality of output voltages produced by the above division. According to this construction, comparison outputs of an input analog signal with respect to arbitrary virtual potentials between the two reference potentials actually given can easily be obtained.

Abstract: A comparator circuit in an analog computational device includes a complement circuit that receives a first analog input. The complement circuit outputs a quantized complement of the first input to first and second addition circuits. A second analog input is also provided to the first and second addition circuits. The first and second addition circuits add the complement circuit output to the second analog input and provide a low output if the result of the addition exceeds threshold values set for the first and second addition circuits. The outputs of the first and second addition circuits are provided to a judging circuit to determine which is greater.

Abstract: A multi-stage sense amplifier for read-only memory having a memory array consisting of a large number of memory cell units. The sense amplifier includes a sense amplifier for sensing the currents flowing through the transistor of the memory cell units of the read-only memory. The memory cell unit transistors are programmed with one of four current capacity characteristics. The sense amplifier also includes three current comparators coupled to the sense amplifier, with each of the comparators having a current comparing unit for comparing the sensed current flowing through the memory cell unit transistors to the current flowing through the comparators. An output of each of the three comparators is provided for identifying whether or not the current of a four capacity characteristics flowing through the memory cell unit transistors is larger than the current flowing through the comparator.

Abstract: A control circuit for maintaining the mean value of the amplitudes of control pulses having a first level and data pulses having a second level includes a detector for providing the control pulses and the data pulses. A reference voltage source provides first, second and third reference voltages having three different levels. A plurality of comparators each receive both the control pulses and the data pulses. A first comparator also receives the lowest of the reference voltages and provides regulation pulses when the control pulses reach the level of the lowest reference voltage. A second comparator receives the second highest reference voltage and provides level limiting pulses to maintain the level of the regulation pulses constant. A third of the comparators receives the highest reference voltage and provides data pulses when the third reference voltage is reached.

Abstract: A counter circuit converts a full count to a zero count and a zero count to a full count. An incrementing counter circuit according to the present invention has a plurality of threshold circuits with stepwise thresholds. An output of the highest threshold circuit is used as a cut off signal for other threshold circuits. A decrementing counter circuit according to the present invention has a plurality of threshold circuits from the lowest threshold to the highest thresholds. An output of the lowest threshold circuit is used as a closing signal for other threshold circuits.

Abstract: Peak and valley voltages of signals from at least two analog sensors are held by the circuit. A plurality of threshold voltages is generated from the previous peak and valley voltages of the respective analog sensors. The signal of each sensor is compared to the respective threshold voltages to produce a sequences of output transitions for each sensor. The output transitions are combined such that each sequence of output transitions from each analog sensor occurs between sequences of the other analog sensor (or sensors). An optional peak and valley reset is also disclosed.

Abstract: An adaptive threshold decision device for multistate modulation produces, at a symbol frequency, symbols dependent on the levels of a received demodulated baseband signal. It comprises a voltage divider, an adder for adding the baseband signal to a midpoint voltage which is substantially the mean of lower and upper voltages applied to the terminals of the voltage divider to produce a transposed signal, plural comparators for comparing the transposed signal with plural voltages at terminals of the voltage divider thereby producing comparison result signals, an encoder for deriving control words according to the comparison result signals, and control circuits for respectively and independently controlling at least the lower and upper voltages according to the control words.

Abstract: A reference period generating circuit is provided which generates a pulse having a width corresponding/to a reference period T.sub.1 in response to the input of a trigger pulse. A switch, a first resistor and a second resistor are connected in series between the first and second reference voltages. The node between the first and second resistors is connected to an inverting terminal of an operational amplifier. A non-inverting terminal thereof is connected to a third reference voltage. A clamping circuit is provided to clamp the output voltage of the operational amplifier to a predetermined value. By comparing the output voltage with a predetermined reference value by means of a comparator, a pulse representative of a timing period is generated.

Abstract: The CMOS high-voltage sensor circuit has a voltage reference including, for example, of four N-channel MOS transistors; one pass-gate P-channel transistor; one current-mirror P-channel MOS transistor; and a conventional high-voltage sensor including, for example, of two P-channel MOS transistors and one N-channel MOS transistor. The sensor circuit of this invention generates a high-voltage signal at the output if the input voltage is greater than both the reference voltage plus two P-channel threshold voltages and the supply voltage Vcc plus two P-channel threshold voltages. The power-up or power-down sequence may be in any order without adversely affecting the operation of the circuit of this invention.

Abstract: A circuit for generating multiple clock edges from a single input clock is disclosed. This circuit has a digital clock input which causes a capacitor to charge and discharge with constant current sources, providing a linear voltage ramp. This linear voltage ramp is monitored by several comparators, each of which have a different reference voltage level, the outputs of which provide the multiple clock edges needed. In this manner, several outputs are generated, each of which has the same fundamental frequency as the input clock signal, but with varying duty cycles and delays from the clock edges of the input clock. In this manner, several clock edges are available for use in synchronous digital systems such as state machines that require precise timing relationships between inputs and clock signals.