Abstract: In described examples, a source circuit can have an input and an output. The input can be adapted to be coupled to an input voltage source configured to provide an input voltage. The source circuit can be configured to output power at an output based on a power delivery mode. The source circuit can include a timer and power delivery (PD) controller. The PD controller can be configured to control the power delivery mode responsive to the input voltage and the timer. The PD controller can be further configured to set a respective power delivery mode and initiate the timer for a timer duration based on the input voltage relative to an input voltage threshold. The PD controller can be further configured to continue operating in the respective power delivery mode for the timer duration.

Abstract: A detection and measurement unit for detecting electromagnetic interference, the detection and measurement unit being configured to receive a representative digital signal. The detection and measurement unit includes a detection subunit configured to compare the amplitude of the representative digital signal with a first triggering threshold and a second stopping threshold. The second stopping threshold corresponds to an amplitude less than that of the first triggering threshold. The detection subunit is configured to detect an electromagnetic pulse on each detection of the passage of the amplitude of the representative digital signal through the second stopping threshold in a falling edge after the amplitude of the representative digital signal.

Abstract: A heating, ventilation and air conditioning (HVAC) controller, a method of detecting multiplexed input signals and an HVAC system employing the controller or the method. In one embodiment, the HVAC controller includes: (1) a signal conditioner configured to convert received alternating current (AC) input signals into corresponding square wave signals of a digital logic voltage, (2) a multiplexer coupled to the signal conditioner and configured to select one of the square wave signals and (3) a sample analyzer coupled to the multiplexer and configured to evaluate multiple samples of the selected one of the square wave signals to derive a binary state.

Abstract: A system can comprise a memory device and sequencing circuitry configured to provide enable signals to a number of voltage regulators in association with providing sequenced power signals to the memory device. The system can include voltage threshold detection circuitry configured to: detect primary supply voltage events; and responsive to detecting a primary supply voltage event, deassert a timer enable signal provided to timing circuitry. The timing circuitry is configured to, responsive to the deassertion of the timer enable signal: deassert a primary enable signal provided to the sequencing circuitry; and maintain the primary enable signal in a deasserted state for a particular amount of time prior to reasserting the primary enable signal.

Abstract: The present invention relates to a technology capable of compensating for a frequency error in a quadrature relaxation oscillator. The quadrature relaxation oscillator generates a signal at a desired frequency by using a resistor and a capacitor which are less sensitive to a PVT (Process, Voltage, Temperature) variation, generates a signal at a desired frequency by compensating for an error from design, which is caused by a mismatch between circuits due to a characteristic of a semiconductor process, through a feedback lop, and removes noise.

Abstract: A virtual image generation system and method is provided. A plurality of synthetic image frames of the three-dimensional scene are rendered, and sequentially displayed to an end user. Each of the displayed image frames has a non-uniform resolution distribution.

Abstract: A receiver includes a first input buffering circuit configured to output a first signal by comparing an input signal and a first offset signal; a second input buffering circuit configured to output a second signal by comparing the input signal and a second offset signal; and a signal mixing circuit configured to output an output signal with a corrected duty ratio by combining the first signal and the second signal.

Abstract: An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, and a gate electrode of the high-voltage depletion-mode transistor is electrically coupled to the source electrode of the low-voltage enhancement-mode transistor. The on-resistance of the enhancement-mode transistor is less than the on-resistance of the depletion-mode transistor, and the maximum current level of the enhancement-mode transistor is smaller than the maximum current level of the depletion-mode transistor.

Abstract: A circuit for filtering narrow pulse and compensating wide pulse, including a signal shaping circuit, a filter circuit, and a pulse width compensating circuit. The signal shaping circuit processes an input signal and transmits the input signal to the filter circuit. The filter circuit filters off narrow pulses of the input signal. The pulse width compensating circuit compensates the wide pulses of the input signal and outputs an output signal.

Abstract: A state-detection circuit facilitates the detection of the state of an input pin relative to several different types of input circuits. According to an example embodiment, a state-detection circuit includes a plurality of comparators and circuit components, configured to provide a plurality of binary output signals that collectively indicate a state of an input pin to which the comparators are coupled. The state-detection circuit is configured to facilitate the detection of several different types of input circuits, based upon the binary output signals.

Abstract: The power supply voltage transition comparison circuit includes a comparator evaluation voltage setting circuit, a comparator, a voltage evaluation circuit, and an evaluation voltage setting value output circuit. The comparator evaluation voltage setting circuit generates a divided voltage of one of a power supply voltage and a reference voltage. The comparator compares the other of the power supply voltage and the reference voltage with the divided voltage. The voltage evaluation circuit evaluates the power supply voltage based on a result of a comparison between the other voltage and the divided voltage. The evaluation voltage setting value output circuit changes a ratio between the one voltage and the divided voltage based on a result of an evaluation of the power supply voltage.

Abstract: Provided is a sensor device capable of removing the influence of each offset voltage of a sensor element, a differential amplifier, and an amplifier of the sensor device, to thereby detect a physical quantity with high precision.

Abstract: A comparator includes a first comparison unit configured to compare an input signal with a first signal and a second comparison unit configured to compare the input signal with a second signal having a voltage value lower than a voltage value of the first signal in a case where a voltage value of the input signal is lower than the voltage value of the first signal and compare the input signal with a third signal having a voltage value higher than a voltage value of the first signal in a case where a voltage value of the input signal is higher than the voltage value of the first signal.

Abstract: A level sensitive comparing device includes: a first comparator, a second comparator, and a determination circuit. The first comparator is arranged for comparing an input signal with a first reference level to generate a first comparison signal. The second comparator is arranged for comparing the input signal with a second reference level to generate a second comparison signal, wherein the second reference level is different from the first reference level. The determination circuit is coupled to the first comparator and the second comparator, and is arranged for determining whether the first comparison signal is allowed to appear at an output of the level sensitive comparing device according to at least the first comparison signal and the second comparison signal, wherein the determination circuit is composed of digital components only.

Abstract: The present invention discloses a power supply input voltage detection circuit. The power supply converts an input voltage to an output voltage by a transformer which includes a primary winding and a secondary winding. The primary winding is coupled to a power switch, which receives a switching signal to adjust the output voltage. The power switch is coupled to a sensing circuit; when the power switch turns ON, the sensing circuit generates a current sense signal according to current through the primary winding. The input voltage detection circuit includes: a rising time detection circuit, which detects a period, of time during which the current sense signal rises from a low reference level to a high reference level to generate a timing signal; and a determination circuit, which generates a determination signal according to the timing signal for determining whether the input signal is a high voltage or a low voltage.

Abstract: Aspects of the instant disclosure are directed toward apparatuses that generate a power-related adjustment signal in response to the power signal. Digital-input-signal pads are included to communicate digital signals with a circuit external to the apparatus. Further, digital-input processing circuitry receives the digital signals from the digital-input-signal pad, and processes the received digital signals. Additionally, configuration circuitry applies the power-related adjustment signal to signals received at the digital-input-signal pad and, in response, detects the digital signals received.

Abstract: A dead-time generating circuit includes a constant current circuit; a current generating circuit generating a capacitor-charge current; and a control circuit receiving a dead time control signal and a comparator signal. The control circuit generates a dead time generating signal based on the dead time control signal and the comparator signal, and a charge/discharge signal based on the dead time generating signal. Charging or discharging of a capacitor is controlled by the capacitor-charge current in accordance with the charge/discharge signal. A voltage of the capacitor is compared with a threshold voltage in order to generate a comparator signal when the voltage of the capacitor exceeds the threshold voltage. The control circuit generates the charge/discharge signal for a duration starting from a time when the delay time has elapsed from the rise or fall timing of the dead time control signal until the control circuit receives the comparator signal.

Abstract: In some embodiments, a reset circuit for an electronic circuit equipped with a backup power capacitor includes a first detector arranged to detect a predetermined first voltage of the backup capacitor, a second detector arranged to detect a predetermined second voltage of the backup capacitor, the second voltage being lower than the first voltage, and a controller arranged to control an output of a reset request signal based on detection results of the first detector and the second detector. The controller is configured to output the reset request signal when the first detector detects the first voltage after the second detector detected the second detector.

Abstract: A squelch detection circuit for high-speed serial communication includes: an input level shifter configured to receive signals inputted through signal lines and shift the received signals to a predetermined potential level; a comparator configured to receive signals outputted from the input level shifter, and compares the received signals to determine whether data signals are noise or signal components; and a reset signal generator configured to receive the signals outputted from the input level shifter, convert the received signals into a single signal, and then generate a reset signal for an elastic buffer. The squelch detection circuit may detect a squelch state and provide a reset value for an elastic buffer in a USB 2.0 interface, and may reduce power consumption as much as possible in a suspend mode.

Abstract: A method and an associated apparatus for a signal rectification and timing circuit. A variable amplitude input signal is generated. An upper threshold level is determined and a lower threshold level is determined. The variable amplitude input signal and the upper threshold level are input into a first comparator. The variable amplitude input signal and the lower threshold level are input into a second comparator. A first digital output signal is generated in the first comparator using a hysteresis circuit and a second digital output signal is generated in the second comparator using a hysteresis circuit. The first digital output signal and the second digital output signal are input into a logic array. A digital level pulse output signal is generated in the logic array that has a digital transition where the variable amplitude input signal passed through a threshold level.

Abstract: According to one embodiment, a semiconductor integrated circuit includes a semiconductor integrated circuit a voltage regulator providing a prescribed power-supply voltage, a plurality of delay test circuits, each of the delay test circuits being configured in each of areas where electrical current flows in response to each of operation modes, a test control unit executing a delay test using the delay test circuit under a test mode while decreasing a power-supply voltage in a stepwise fashion, a supply voltage decision unit deciding the power-supply voltage of the operation mode on a basis of the delay test, a memory unit storing the power-supply voltage of each operation mode, a supply voltage configuration unit reading out the power-supply voltage corresponding to the operation mode from the memory unit, and the supply configuration unit arranging the power-supply voltage as an output voltage of the voltage regulator when each of the operation modes starts to execute.

Abstract: A comparator (10) includes a first input transistor (M0) having a drain coupled to a gate and drain of a first diode-connected transistor (M2) and a gate of a first current mirror output transistor (M4), and a second input transistor (M1) having a drain coupled to a gate and drain of a second diode-connected transistor (M3) and a gate of a second current mirror output transistor (M5). Sources of the first and second current mirror output transistors are connected to a supply voltage (VDD). Gates of the first and second input transistors are coupled to first (VIN?) and second (VIN+) input signals, respectively. Sources of the first and second diode-connected transistors are coupled to drains of the first and second current mirror output transistors, respectively. A latch circuit (M8,M9) is coupled to the drains of the first and second current mirror output transistors.

Abstract: In an adjustable voltage examining module, while a logic tester issues an input signal to an audio module under test, upper/low-threshold reference signals are simultaneously issued to an adjustable voltage comparing circuit. While the adjustable voltage comparing circuit receives a signal under test returned by the to-be-examined audio module after a while, the adjustable voltage comparing circuit loads both an high-threshold reference voltage and a low-threshold reference voltage respectively indicated by the reference upper/low-threshold signal so as to compare both the upper and low-threshold reference voltages with the signal under test. Therefore, while the signal under test is examined to acquire a voltage level between voltage levels of the upper and low-threshold reference signals, precise operations of the audio module under test are assured, and time wasted by continuously-issued interrupt is saved.

Abstract: A comparator (10) includes a first input transistor (M0) having a drain coupled to a gate and drain of a first diode-connected transistor (M2) and a gate of a first current mirror output transistor (M4), and a second input transistor (M1) having a drain coupled to a gate and drain of a second diode-connected transistor (M3) and a gate of a second current mirror output transistor (M5). Sources of the first and second current mirror output transistors are connected to a supply voltage (VDD). Gates of the first and second input transistors are coupled to first (VIN?) and second (VIN+) input signals, respectively. Sources of the first and second diode-connected transistors are coupled to drains of the first and second current mirror output transistors, respectively. A latch circuit (M8,M9) is coupled to the drains of the first and second current mirror output transistors.

Abstract: A squelch detection circuit for high-speed serial communication includes: an input level shifter configured to receive signals inputted through signal lines and shift the received signals to a predetermined potential level; a comparator configured to receive signals outputted from the input level shifter, and compares the received signals to determine whether data signals are noise or signal components; and a reset signal generator configured to receive the signals outputted from the input level shifter, convert the received signals into a single signal, and then generate a reset signal for an elastic buffer. The squelch detection circuit may detect a squelch state and provide a reset value for an elastic buffer in a USB 2.0 interface, and may reduce power consumption as much as possible in a suspend mode.

Abstract: The present invention discloses a power supply input voltage detection circuit. The power supply converts an input voltage to an output voltage by a transformer which includes a primary winding and a secondary winding. The primary winding is coupled to a power switch, which receives a switching signal to adjust the output voltage. The power switch is coupled to a sensing circuit; when the power switch turns ON, the sensing circuit generates a current sense signal according to current through the primary winding. The input voltage detection circuit includes: a rising time detection circuit, which detects a period, of time during which the current sense signal rises from a low reference level to a high reference level to generate a timing signal; and a determination circuit, which generates a determination signal according to the timing signal for determining whether the input signal is a high voltage or a low voltage.

Abstract: First and second resistor series divide a predetermined voltage range to generate first reference voltages and second reference voltages, respectively. First and second switch controlling circuits select respective ones of the first reference voltages and the second reference voltages. A comparing unit generates a logical signal representing a logical value by comparing a combined transistor current based on the selected first and second reference voltages with a transistor current based on an input signal. The first switch controlling circuit specifies two adjacent first reference voltages where the logical value is inverted by sequentially selecting the first reference voltages, and determines to select one of the adjacent reference voltages. Te second switch controlling circuit specifies two adjacent second reference voltages where the logical value is inverted by sequentially selecting the second reference voltages, and determines to select one of the adjacent reference voltages.

Abstract: In one form, a power detector includes first and third transistors of a first conductivity type, and second and fourth transistors of a second conductivity type. A control electrode of the first transistor receives a first bias voltage plus a positive component of a differential input signal. The second transistor is coupled in series with the first transistor and has a control electrode receiving a second bias voltage plus a negative component of the differential input signal. The third transistor is biased using the first bias voltage plus the negative component. The fourth transistor is coupled in series with the third transistor and is biased using the second bias voltage plus the positive component. A common interconnection point of the first and third transistors forms an output node. In another form, a power detector compares an output of a power detector core to multiple threshold voltages in corresponding comparators.

Abstract: A power-on reset circuit includes a first monitor circuit that monitors a power supply voltage, an output circuit that outputs a reset release signal upon detection, by the first monitor circuit, of the power supply voltage exceeding a first predetermined value, and a control circuit having lower current consumption than the first monitor circuit, wherein the control circuit includes a second monitor circuit that monitors the power supply voltage, a suppression circuit that suppresses current flowing through the first monitor circuit upon detection, by the second monitor circuit, of the power supply voltage exceeding a second predetermined value higher than the first predetermined value, and an output fixing circuit that fixes the output of the output circuit to a predetermined potential upon detection, by the second monitor circuit, of the power supply voltage exceeding the second predetermined value.

Abstract: Supply voltage sequencing circuitry includes a first sequencer (10-1) that produces an active level of a Power Good signal PG if a first supply voltage VOUT1 exceeds an upper threshold V90% while a control signal EN_PG is active, and produces an inactive level of PG if EN_PG is inactive. The PG level is latched when a control signal EN is inactive. A Power Down signal PD is produced if VOUT1 is less than a lower threshold V10% while EN is inactive. An active level of PD is produced when EN is active. A power-up sequence of supply voltages VOUT1, VOUT2, and VOUT3 monitored by the first sequencer and similar second (10-2) and third (10-3) sequencers, respectively, is determined by connection of PG of each of the first and second sequencers to control the supply voltage monitored by the next sequencer.

Abstract: According to one embodiment of the present invention, it is possible to realize a signal transmitter which is capable of reducing power consumption and which can be easily designed. A differential transmitter block outputs differential output signals fixed to a predetermined logic signal to a differential receiver block and disconnects terminating resistors from a signal transmission path in an idle state. In the differential receiver block, a differential comparator outputs a logic determined by symbols of the differential output signal from the differential transmitter block, and an operating state detector detects the idle state upon detection that time successively outputting a predetermined logic by the differential comparator reaches a predetermined time, and controls switches so as to disconnect the terminating resistors from the signal transmitter in the receiving side upon detection of the idle state.

Abstract: A method and circuit for detecting a current and compensating for an offset voltage. The circuit includes two comparators where one of the comparators has two input terminals and the other comparator has three input terminals. An input terminal of each of the two comparators are commonly connected together, the other input terminal of the two-input comparator is coupled for receiving a first reference voltage, and a second input terminal of the three-input comparator is coupled for receiving a second reference voltage. During a first portion of the period of a sense signal the two comparators operate in a sensing mode and during a second portion of the period of the sense signal the comparator having the three input terminals operate in a current nullification mode or an offset voltage compensation mode. An offset compensation signal is generated during the second portion of the sense signal.

Abstract: A signal receiver circuit includes a first level detector for offset-controlling a first output node in response to a pair of first reference signals. A second level detector offset-controls a second output node in response to a pair of second reference signals.

Abstract: An electronic device compares a first voltage with a selected first reference voltage or second reference voltage. The electronic device includes a comparator having a first input receiving the first voltage, a second input receiving the selected reference voltage and an output providing an output signal based on a comparison. A control stage connected to the output of the comparator generates a control signal based on the output of the comparator. The electronic device selects either the first reference voltage or the second reference voltage in response to the control signal thus comparing the first voltage with the selected reference voltage.

Abstract: A peak detection/digitization circuit includes a plurality of level detect units, each having a comparator and a flip-flop with a clock input responsive to the output of the comparator. For a detection period, each level detect unit configures a data output signal of the flip-flop to a first data state responsive to a start of the detection period. Further, each level detect unit is configured to enable the comparator responsive to the data output signal having the first data state or a second data state, respectively. While the comparator is enabled during the detection period, the level detect unit configures the data output signal of the flip-flop responsive to a comparison of an input signal to a corresponding reference voltage level by the comparator. The data output signals of the flip-flops of the level detect units at the end of the detection period are used to determine a digital value representative of a peak voltage level of the input signal.

Abstract: Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a latch based analog to digital converter is disclosed that includes a first interleave with a set of comparators, a selector circuit and a latch. The set of comparators is operable to compare an analog input with respective reference voltages, and is synchronized to a clock phase. The selector circuit is operable to select an output of one of the set of comparators based at least in part on a selector input. A first interleave output is derived from the selected output. The latch receives a second interleave output from a second interleave and is transparent when the clock phase is asserted. The selector input includes an output of the latch.

Abstract: A window comparator of an A.C. input voltage, including, between two terminals of application of a voltage representative of the voltage to be measured, two first transistors of a first type, each first transistor being assembled as a current mirror on the second transistor having a first conduction terminal connected to one of the application terminals, the two second transistors having a second common conduction terminal; and two third transistors of a second type assembled as a current mirror between the common conduction terminal of the second transistors and a current source, a D.C. voltage being applied on a first terminal of the current source and an output signal being provided by a second terminal of the current source.

Abstract: A clock generation circuit, includes, in part, a comparator, a logic unit, and a switching circuit. The switching circuit generates a signal that is applied to the comparator. If the input voltage level of the signal applied to the comparator is greater than a first reference voltage, the comparator asserts its first output signals. If the input voltage level of the signal applied to the comparator is less than a second reference voltage, the comparator asserts its second output signal. The output signals of the comparator form a first pair of feedback signals applied to the switching circuit. The logic unit responds to the output signals of the comparator to generate a second pair of oscillating feedback signals that are also applied to the switching circuit. The switching circuit varies a capacitor voltage in response to a reference current and in response to the two pairs of feedback signals it receives.

Abstract: A signal receiver circuit includes a first level detector for offset-controlling a first output node in response to a pair of first reference signals. A second level detector offset-controls a second output node in response to a pair of second reference signals.

Abstract: A comparator generates lower and upper reference voltages to establish an amplitude hysteresis. A first comparator circuit generates a first comparison signal indicating whether an input signal is above the upper reference voltage. A second comparator circuit generates a second comparison signal indicating whether the input signal is below the lower reference voltage. Further, the first and second comparison signals may be low-pass filtered to establish a time hysteresis. A latch is set to a first state if the first control signal indicates the input signal is above the upper reference voltage. The latch is set to a second state if the second control signal indicates the input signal is below the lower reference voltage. In some embodiments, the comparator has a rail-to-rail common mode input voltage range, a low-power mode of operation, and is self-biased to compensate for temperature, voltage, and process characteristics.

Abstract: A design structure for an on-chip duty cycle measurement system may be embodied in a machine readable medium for designing, manufacturing or testing an integrated circuit. The design structure may embody an apparatus that measures the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit. The design structure may specify that the DCM circuit includes a capacitor driven by a charge pump and that a reference clock signal drives the charge pump. The design structure may specify that the clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The design structure may specify that the DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store.

Abstract: A method and a circuit arrangement are disclosed for determining radiation intensity using counting detectors or detector elements, in which x-ray radiation photons, which are either absorbed or absorbed in part, generate electrical signals, the pulse number and pulse height of which is correlated to an incident radiation intensity, and the radiation intensity is at least determined by counting the pulses. According to at least one embodiment of the invention, the signal pulses incident on at least one detector or detector element are detected simultaneously by at least one continuously operating pulse height discriminator and by at least one pulse height discriminator operating in a clocked fashion, with the number of incident signal pulses being determined with the aid of these two items of detection information.

Abstract: The invention discloses baseline wandering correction techniques. A baseline wandering correction device comprises a differentiator differentiating a data signal to generate a differentiated signal, a operation signal coupling to the differentiator and proceeding with an operation based on the data signal according to the differentiated signal to generate an operated signal, an extracting module coupling to the operation module and determining a first and a second threshold value according to the operated signal, a comparing signal coupling to the extracting module and comparing the operated signal with the first and second threshold values to generate a first and a second processing signal, and a latch module latching the first and second processing signals to generate an output signal.

Abstract: An up-conversion mixer includes a first and a second hybrid couplers and a first and a second traveling-wave mixers is disclosed. The first hybrid coupler receives an input intermediate frequency (IF) signal and produces a first IF signal (IF1) and a second IF (IF2) signal, the second IF signal being 180 degree off-phase compared to the first IF signal. The first traveling-wave mixer mixes the first IF signal (IF1) and a first local oscillator (LO1) signal to produces a first radio frequency signal (RF1). The second traveling-wave mixer mixes the second IF signal (IF2) and a second local oscillator signal (LO2) to produces a second RF signal (RF2). The second hybrid coupler to combines the first RF signal and the second RF signal to produce an output RF signal. The use of the traveling-wave mixers allow for a wide bandwidth operation of the up-conversion mixer.

Abstract: An image rejection mixer including a first and a second hybrid couplers and a first and a second traveling-wave mixers is disclosed. The first hybrid coupler divides an input radio frequency (RF) signal to a first RF signal and a second RF signal, the second RF signal being in quadrature to the first RF signal. The first traveling-wave mixer mixes the first RF signal and a local oscillator (LO) signal to produces a first intermediate frequency (IF) signal. The second traveling-wave mixer mixes the second RF signal and the local oscillator signal to produces a second IF signal. The second hybrid coupler combines the first IF signal and the second IF signal to produce an upper sideband of the IF signals and a lower sideband of the IF signals. The use of the traveling-wave mixers allow for a wide bandwidth operation of the image rejection mixer.

Abstract: A multi-level comparator with fixed power consumption is disclosed. By using the switch character of differential pair and parallelizing single side of common source amplifier with multi-level input, the power of the multi-level comparator can be fixed by the current bias. This result shows that the multi-level comparator is able to heighten input stages at fixed power. Therefore, the multi-level comparator has the functionalities of several different comparators while maintaining fixed power consumption.

Abstract: An apparatus, device, and method for loss of signal detection in a receiver are provided. A reference circuit is operable to rectify a reference signal. An input circuit is operable to rectify an input signal. A comparator is operable to compare outputs of the reference circuit and the input circuit and to generate an output signal based on the comparison. The output signal indicates whether the input signal falls within threshold limits defined by the reference signal. A second reference circuit and a second input circuit could also be used, and the reference circuits and input circuits can be selectively enabled and disabled based on which of multiple differential pairs is enabled in a receiver receiving the input signal. The differential pairs can be used in the receiver to generate an output signal based on the input signal.

Abstract: Determining voltage level validity for a power-on reset condition is described. A supply voltage is applied to an integrated circuit. An oscillating signal is generated responsive to the supply voltage applied. A counting occurs responsive to oscillations of the oscillating signal. A triggering occurs responsive to reaching a first voltage level of the supply voltage for the power-on reset condition. A first count of the counting occurs responsive to the triggering. A second count is selected responsive to the first count. A second level is accepted as having at least met a threshold for the supply voltage responsive to the counting reaching the second count for the power-on reset condition.

Abstract: An output signal is controlled with adjustable hysteresis in response to a variable voltage input signal. One or more signals derived from the input signal are respectively compared with first and second reference voltages of different magnitudes. The output signal changes from a first state to a second state when one of the derived signals reaches a first reference voltage level threshold, and changes from the second state to the first state when a second one of the derived signals reaches a second reference level voltage threshold. A first derived signal may be varied to have a voltage magnitude that is greater or lesser than the voltage magnitude of a second derived signal while maintaining a positive hysteresis level. The circuit may be configured to output a signal representing an undervoltage and/or overvoltage condition of the input signal.

Abstract: The discrimination phase margin monitor circuit (10) of the present invention comprises a first discrimination circuit (11 and 12) discriminating an input data signal using a clock signal extracted from the input data signal, a second discrimination circuit (13 and 14) discriminating the input data signal using a clock signal with a frequency different from that of the clock and an operation circuit (15 and 16) calculating the exclusive OR of the output signal of the first discrimination circuit and that of the second discrimination circuit and obtaining a phase margin monitor output signal by averaging the exclusive ORs.