Abstract: A system and method is disclosed for providing a clock and data recovery circuit that comprises a low jitter data receiver. The low jitter data receiver comprises a phase interpolator, an amplifier unit and a data sampling comparator. The phase interpolator and the amplifier unit provide the data sampling comparator with a single ended clock signal that is relatively immune to power supply noise. The data sampling comparator samples an input data stream with minimal jitter due to power supply noise. The data sampling comparator consumes less static power than a current mode logic D flip flop and also has output levels that are compatible with complementary metal oxide semiconductor (CMOS) logic.

Abstract: In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch with integrated testability. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, three voting structures with inputs from the first, second, and third settable memory elements, determine the logical value held on each of the settable memory elements. Data may be scanned into and out of the second settable memory element. Data is propagated through the buffer into the third settable memory element. The third settable memory element may be used to scan data out of the triple redundant latch. The propagation delay through a latch is the only propagation delay of the triple redundant latch.

Abstract: A hysteresis comparing device with constant hysteresis width and the method thereof, which can respectively receive a first signal and a second signal and can output a digital signal. The hysteresis comparing device includes a threshold voltage generator, a multiplexer, and a next stage comparator. The threshold voltage generator is used to receive the first signal and output an upper threshold voltage and a lower threshold voltage. The multiplexer is used to receive the upper threshold voltage and the lower threshold voltage, and output a multiplexing signal according to the digital signal. The multiplexing signal is either the upper threshold voltage or the lower threshold voltage. The next stage comparator has one terminal used to receive the multiplexing signal, and another terminal used to receive the second signal. The next stage comparator outputs the digital signal. The hysteresis comparing device with constant hysteresis width can suppress the effect from the glitch.

Abstract: A data receiver and data receiving method using signal integration and capable of reducing high-frequency noises generated upon high-speed data detection.

Abstract: An improved input buffer circuit and method configured for voltage detection is provided that can facilitate use of a mid-level voltage for testing purposes. An exemplary input buffer configured for voltage detection comprises a reference generator and a multi-state detector. The reference generator is configured to generate at least two reference voltages to be provided as input signals to the multi-state detector. The multi-state detector is suitably configured to receive an input reference signal, and through comparison of the input reference signal to the two reference voltages, provide output signals to three output terminals representing a high, low and mid-level state of operation. An exemplary input buffer circuit can comprise two differential pairs of transistors configured in a back-to-back arrangement and sharing a common node, thus resulting in lower current requirements.

Abstract: A power level detection circuit detects the voltage level of a power source. The power level detection circuit has a first voltage level detector having an input coupled to the power source and outputting a first signal representative of an upper boundary, a second voltage level detector having an input coupled to the power source and outputting a second signal representative of a desired detection level, and a third voltage level detector having an input coupled to the power source and outputting a third signal representative of a lower boundary. The power level detection circuit also has a control circuit coupled to the first, second and third signals for outputting a power level detection signal if there is a change in the second signal, and when the power level is greater than the level of the third signal and less than the level of the first signal.

Abstract: A power-down signal is encoded into a differential pair of lines between two chips. When the differential transmitter powers down, it enters a high-impedance state and floats the differential lines. A shunt resistor between a pair of differential lines equalize the voltages on the differential lines so they float to a same voltage when a differential transmitter is disabled and enters a high-impedance state. The condition of equal voltages on the differential lines is detected by an equal-voltage detector that generates a power-down signal when the differential lines are at equal voltages for a period of time. The period of time can be greater than the cross-over time during normal switching to prevent false power-downs during normal switching. Standard differential drivers can signal power-down using the high-impedance state, which is detected by equal voltages on the differential lines. A sensitive dual-differential amplifier and a simpler detector are disclosed.

Abstract: A comparator comprises a switching means for supplying two different threshold voltages to the comparator upon a first and a second control signal, respectively. The second control signal is enabled by a rising or a falling edge of the comparator output that is coupled to a control means providing the second control signal. The time interval that a varying input signal requires to change its amplitude crossing and in between the two threshold voltages can thus be detected by two subsequent rising or falling edges of the comparator output without the adverse influence of the comparator's meta-stability.

Abstract: An apparatus and method for processing a differential-type signal transmitted through a pair of data lines. First, a voltage range defined by an upper reference and a lower reference and a logic pattern are provided. Then, the signal is tested to generate logic data responsive to the voltage range. Next, the logic data are utilized to compare with the logic pattern so as to generate a test result when the signal enters a transition cycle.

Abstract: A hysteresis comparing device with constant hysteresis width, which can respectively receive a first signal and a second signal and can output a digital signal. The hysteresis comparing device includes a threshold voltage generator, a multiplexer, and a next stage comparator. The threshold voltage generator is used to receive the first signal and output an upper threshold voltage and a lower threshold voltage. The multiplexer is used to receive the upper threshold voltage and the lower threshold voltage, and output a multiplexing signal according to the digital signal. The multiplexing signal is either the upper threshold voltage or the lower threshold voltage. The next stage comparator has one terminal used to receive the multiplexing signal, and another terminal used to receive the second signal. The next stage comparator outputs the digital signal. The hysteresis comparing device with constant hysteresis width can suppress the effect from the glitch.

Abstract: A power-down signal is encoded into a differential pair of lines between two chips. When the differential transmitter powers down, it enters a high-impedance state and floats the differential lines A shunt resistor between a pair of differential lines equalize the voltages on the differential lines so they float to a same voltage when a differential transmitter is disabled and enters a high-impedance state. The condition of equal voltages on the differential lines is detected by an equal-voltage detector that generates a power-down signal when the differential lines are at equal voltages for a period of time. The period of time can be greater than the cross-over time during normal switching to prevent false power-downs during normal switching. Standard differential drivers can signal power-down using the high-impedance state, which is detected by equal voltages on the differential lines. A sensitive dual-differential amplifier and a simpler detector are disclosed.

Abstract: A window detector circuit for high frequency applications includes a differential amplifier that has two inputs which receive a differential voltage signal. A bias network, having a balancing node, connected between the two inputs. An output transistor, electrically biased by the balancing node, connected between power and ground. In operation, when the differential voltage signal is below a voltage threshold, the differential amplifier is turned off and current flows through the output transistor. When the differential voltage signal is at or exceed the voltage threshold, the differential amplifier turns on.

Abstract: An improved input buffer circuit and method configured for voltage detection is provided that can facilitate use of a mid-level voltage for testing purposes. An exemplary input buffer configured for voltage detection comprises a reference generator and a multi-state detector. The reference generator is configured to generate at least two reference voltages to be provided as input signals to the multi-state detector. The multi-state detector is suitably configured to receive an input reference signal, and through comparison of the input reference signal to the two reference voltages, provide output signals to three output terminals representing a high, low and mid-level state of operation. An exemplary input buffer circuit can comprise two differential pairs of transistors configured in a back-to-back arrangement and sharing a common node, thus resulting in lower current requirements.

Abstract: Data input receivers reproduce data signals, and methods detect data signals in data input receivers. The invention receives an input data signal and two reference signals, which may be complementary. A first voltage difference between the input data signal and the first reference signal is amplified, and a second voltage difference between the input data signal and the second reference signal is amplified. The amplified first voltage difference and the amplified second voltage difference are received on the same pair of output terminals, which are then compared to generate the reproduced data signal.

Abstract: A comparator circuit is described and contains a comparator, which is provided with an operating point. A montioring circuit suppresses undesired signal bouncing at the output. The bouncing is produced by interferences of the input signal. The monitoring circuit ensures that the circuit output is locked from being switched back to another logical level after switching until the input signal has reached a second threshold value that is higher than the operating point.

Abstract: A comparator circuit for positive and negative signals having zero consumption and suitable for devices with a single positive power supply includes a first and second comparator connected in parallel and receiving a common input signal and, respectively, a first positive threshold voltage and a second negative threshold voltage. The comparator circuit further includes a first logic circuit cascade-connected to the first and second comparators. The first and second comparators are respectively suitable to detect the crossing on the part of the input signal of the first and second threshold voltages. The second comparator is provided by n-channel and p-channel MOS transistors of the enhancement type. The comparator circuit also includes a second logic circuit cascade-connected to the first logic circuit, and a monostable circuit connected to the second logic circuit.

Abstract: The present invention provides a voltage detecting circuit comprising: at least a low voltage detecting circuit for detecting that a power voltage is lower than at least a predetermined reference voltage; at least a high voltage detecting circuit for detecting that the power voltage is higher than the at least a predetermined reference voltage; and a controller being connected to the at least a low voltage detecting circuit and the at least a high voltage detecting circuit for detecting that the power voltage is higher than the at least a predetermined reference voltage; and a controller being connected to the at least a low voltage detecting circuit and the at least a high voltage detecting circuit so that the controller receives an output signal from the at least a high voltage detecting circuit in order to place the at least a low voltage detecting circuit into selected one of operable and inoperable states in accordance with the output signal from the at least a high voltage detecting circuit.

Abstract: A power-up detection circuit to produce a power-up detection signal detects a reference voltage of a device. After a power-up detection has been produced, a DC current path to ground is established to conduct DC current to reset the power-up detection circuit to produce a subsequent power-up detection signal.

Abstract: A improved signal detector is provided. The signal detector includes a linear amplifier receiving the input signal and providing an amplified signal. A full-wave rectifier is coupled to the linear amplifier and provides a rectified signal. A low-pass filter is coupled to the full-wave rectifier receiving the rectified signal and providing a comparing signal. A high threshold reference and a low threshold reference respectively is applied to a first comparator and a second comparator, each receiving the comparing signal. The first comparator and the second comparator respectively provide a first compared signal and a second compared signal. A reference path providing the high threshold reference and the low threshold reference includes a linear amplifier, a full-wave rectifier and a low-pass filter providing the high threshold reference. A linear charge pump is connected at its input to the linear amplifier and connected at its output to a low-pass filter to provide the low threshold reference.

Abstract: The present invention concerns an improved charge pump. The charge pump efficiently charges a voltage signal while reducing its power consumption. The charge pump includes at least one diode configured to receive a voltage signal. Coupled to the diode(s) is at least one capacitive device that is capable of coupling charge onto the diode(s). For one embodiment, the capacitive device provides a constant capacitance to more efficiently charge the voltage signal. The charge pump also includes an oscillating circuit that is capable of providing each capacitive device with an oscillating signal that alternates between a first voltage level and a second voltage level at a predetermined frequency. The oscillating circuit includes an odd number of N inverters coupled in a ring wherein an output of the Nth inverter is coupled to the input of the first inverter.

Abstract: A loop control detection circuit (100) is provided for detecting feedback values in a current feedback control loop to determine if the control loop is in or out of control.

Abstract: The present invention concerns an improved charge pump. The charge pump efficiently charges a voltage signal while reducing its power consumption. The charge pump includes at least one diode configured to receive a voltage signal. Coupled to the diode(s) is at least one capacitive device that is capable of coupling charge onto the diode(s). For one embodiment, the capacitive device provides a constant capacitance to more efficiently charge the voltage signal. The charge pump also includes an oscillating circuit that is capable of providing each capacitive device with an oscillating signal that alternates between a first voltage level and a second voltage level at a predetermined frequency. The oscillating circuit includes an odd number of N inverters coupled in a ring wherein an output of the Nth inverter is coupled to the input of the first inverter.

Abstract: An arrangement for monitoring an alternating signal with respect to its state as mark-to-space ratio or direct-current component, in which the alternating signal is modified so that its mark-to-space ratio or direct-current component can be detected by simple comparison with reference signals. Various information is then transmitted over a line, and the operation of the stage that generates the alternating signal can also be monitored.

Abstract: In an interface circuit having a transmitting side circuit, a receiving side circuit and a transmission path connecting the transmitting side circuit and the receiving side circuit in a transmission system for transmitting a predetermined signal between the transmitting and receiving sides, the receiving side circuit has a receiver circuit having threshold control section for independently controlling a logical threshold value corresponding to rise of a received transmitting signal from low level to high level and a logical threshold value corresponding to fall of the received transmitting signal from high level to low level, and a control circuit for controlling the logical threshold values of the receiver circuit through the threshold control section in response to a voltage change in the transmitting signal.

Abstract: In controlling a discrimination level V.sub.1, V.sub.1 is controlled so that discrimination results based on discrimination levels V.sub.1 +.DELTA.V and V.sub.1 -.DELTA.V each become equal to the discrimination result based on the discrimination level V.sub.1. If the discrimination result based on V.sub.1 +.DELTA.V does not agree with the discrimination result based on V.sub.1, V.sub.1 is lowered, and if the discrimination result based on V.sub.1 -.DELTA.V does not agree with the discrimination result based on V.sub.1, V.sub.1 is raised. In controlling a discrimination phase .PHI..sub.1, .PHI..sub.1 is controlled so that discrimination results based on discrimination phases .PHI..sub.1 +.DELTA..PHI. and .PHI..sub.1 -.DELTA..PHI. each become equal to the discrimination result based on the discrimination phase .PHI..sub.1. If the discrimination result based on .PHI..sub.1 +.DELTA..PHI. does not agree with the discrimination result based on .PHI..sub.1, .PHI..sub.

Abstract: A method and apparatus for recovering timing information from a ternary signal includes transforming a ternary signal into a binary signal while retaining the necessary timing information. A two facet circuit initially receives a ternary signal, one that includes three levels of values. A first facet of this circuit transforms the ternary signal into two binary signals, each having one of the three levels represented by one value and both having the same level represented by the other value. The second facet of this circuit combines the two binary signals to produce a third binary signal that has one value representing one level and another value representing the two other levels.

Abstract: The present invention provides a method and apparatus for detecting voltage drops on an IC chip. The device operates by using a reference voltage to detect the voltage range of a local voltage. A multiple number of reference voltages are used (or predetermined) between the reference voltage and the ground voltage. The voltage drop detecting device includes a multiple number of inverters having to the local voltage as its input. The inverters each have a trigger voltage corresponding to one of the reference positions. When the local voltage is smaller than the trigger voltage of the inverter, a low to high voltage switching is present at the output. A multiple number of positive-edge triggering devices, coupled to the reference voltage as one of its inputs, are each coupled to one of the inverters. A corresponding inverter presents a low to high switching to make the reference voltage present at the corresponding output terminal. The voltage range of the local voltage is detected at the output terminals.

Abstract: A signal reception apparatus has an automatic level selection function. A comparing circuit compares a level of an input signal with a plurality of sensing levels and outputs a plurality of sensing signals in accordance with the compared result. An auto select level controller receives the plurality of sensing signals from the comparing circuit and selects one of the plurality of sensing levels in response to the plurality of sensing signals. The auto select level controller includes a plurality of flip flop stages. Each of the plurality of flip flop stages has a plurality of flip flops connected in series and is coupled to a corresponding one of the plurality of sensing signals from the comparing circuit. A circuit receives the output signals from the plurality of flip flop stages and selects one of the plurality of sensing levels in response to the inputted sensing signals.

Abstract: A comparator with hysteresis in bipolar technology having a voltage/current converter with a voltage input forming the comparator input connection, and a current output, a bistable current source with a current feeding connection coupled with the current output of the voltage/current converter and a current output connection forming the comparator output, the bistable current source being currentless in a first stable state and consuming current only in the second stable state, the firing current which must be fed to the current feeding connection to switch the bistable current source from the currentless state to the power-consuming state being different from the quenching current which must be fed to the current feeding connection to switch the bistable current source from the power-consuming state to the currentless state, to obtain a hysteresis of the comparator, and all transistors being formed as bipolar transistors.

Abstract: An electronic circuit suitable for sampling an incoming data bit stream in order to recover the information contained in the data stream contains an input section, a reference section, and a comparing section. The input section produces a ramp signal that switches between a first endpoint voltage and a second endpoint voltage in a periodic manner. The reference section furnishes a plurality of reference voltages between the two endpoint voltages. The comparing section compares the ramp signal to the reference voltages to produce corresponding sampling signals. Each sampling signal makes a first voltage transition as the ramp signal passes a corresponding reference voltage in going from the second endpoint voltage to the first endpoint voltage. Accordingly, the first transitions of the sampling signals occur in groups, each group being spread out in time during part of a period of the ramp signal. A data sampling portion of the circuit utilizes the sampling signals to sample the input data bit stream.

Abstract: A zero-crossing circuit and method, in which the sign of inputs to a comparator is reversed after each zero crossing of the input signal. This means that delay introduced by the comparator does not affect the duty cycle of the output signal, so precision synchronization remains possible.

Abstract: Integrated circuits which process analog signals and consist of a plurality of separate functional blocks are difficult to test because the terminals of, internally interconnected functional blocks cannot be simply fed out in view of the limited number of external terminals. In order to test the integrated circuit by testing individual functional blocks separately, it is proposed to connect inputs and outputs of functional blocks are connected to switches enabling connection of these functional blocks to external terminals. The switches are controlled by storage stages which are loaded via a test input which is connected to comparators. These comparators compare the input signal with various reference voltages, the voltage ranges between the reference signals being associated with the logic values "0" and "1" as well as with a clock signal value.

Abstract: A voltage level shifter is disclosed having an input and an output. The input receives a first signal capable of fluctuating between at least two voltages. The voltage level shifter produces a second signal, at the output, based on the voltage of the input signal and two or more user-defined reference voltages.

Abstract: A circuit (10) for enhancing logic transitions appearing on a line (34) has been provided. The circuit includes a first comparator (14) for sensing when a voltage on the line exceeds a first level and subsequently pulling the voltage on the line to a first predetermined voltage. The circuit also includes a second comparator (12) for sensing when the voltage on the line falls below a second level and subsequently pulling the voltage on the line to a second predetermined voltage.

Abstract: A glitch trigger circuit for measuring glitches that appear on power line signals includes two comparators and two independently controllable voltage trigger levels to allow proper trigger on glitches of unknown polarity. A high pass filter rejects the power line signal while passing the glitch signals to provide triggering on glitches with voltage amplitudes less than the voltage amplitude of the power line signal.

Abstract: An element generator for a dither matrix comprises a logic device which receives a row address and a column address and performs a logic operation thereon so as to produce a dither element corresponding to the row address and the column address, which is implemented at low cost and has an advantage in that the processing speed is increased. The dithering apparatus comprises a dither-matrix element generator, a comparator, an adder and a selector. The comparator compares the output of the dither-matrix element generator with lower-bit data of the original image data. The adder adds a predetermined number to upper-bit data of the original image data. The selector selects one between the upper-bit data and the adder output, in accordance with the output of the comparator, so as to produce the selected one as the dithered image data. Dithering is thereby performed via hardware, which leads to an increased processing speed.

Abstract: A non-linear transmission line terminator (10) is provided in which voltages appearing on a transmission line are sensed. If the voltage level sensed is equal to a predetermined voltage, the non-linear transmission line terminator (10) couples a reference voltage to the transmission line. If the sensed voltage is less than the predetermined voltage, the non-linear transmission line terminator (10) delivers current to the transmission line having a magnitude related non-linearly to the sensed voltage.

Abstract: A circuit style, which may be employed in fast, area-efficient, flexible programmable interconnect architectures, is disclosed. In one embodiment, a plurality of clocked dynamic logic circuits, each having a single network node, is connected to the intermediate nodes of a programmable interconnect architecture. During the precharge clock phase, the circuits precharge the intermediate nodes to a high logic level. During the evaluation clock phase, each circuit is initially in the stand-by state, in which it monitors the logic level on its network node. If a substantial deviation from the high level towards the low level is detected, the circuit switches to the discharge state, in which it enforces that level change by connecting its network node to the low level. This causes the potential on neighboring nodes, connected through conducting programmable switches, to change towards a low level, and their circuits in turn switch to the discharge state.

Abstract: An apparatus for activating a dual-mode logic device is provided. The apparatus monitors a parameter of an input signal of the logic device. If the parameter falls outside of predetermined parametric ranges, the apparatus activates the logic device. In the preferred embodiment, the apparatus resides on the same semiconductor chip as the logic device, and monitors the voltage level of the input signal. If the voltage level falls outside the voltage range which represents a logical HIGH and the voltage range which represents a logical LOW, the apparatus activates the logic device.