Abstract: This application relates to methods and apparatus for phase locked loops. A phase-and-frequency detector (101) receives a reference clock signal (CKref) and a feedback signal (SFB) and outputs a first adjustment signal (U) that is modulated between respective first and second signal levels to provide control pulses indicating that an increase in frequency required for phase and frequency lock, and a second adjustment signal (D) that is modulated between respective first and second signal levels to provide control pulses indicating that a decrease in frequency required for phase and frequency lock. First and second time-to-digital converters (201-1 and 201-2) receive the first and second adjustment signals respectively and output respective first and second digital signals indicative of the duration of said control pulses.

Abstract: A power-control device for generating and controlling a supply voltage is provided. The power-control device includes a variant delay chain with a delay length, a sampling circuit, a comparison circuit, and a power manager. The variant delay chain receives an initial signal and performs a delay operation on the initial signal according to the delay length to generate a delay signal. The sampling circuit receives the delay signal and performs a sampling operation on the delay signal to generate a sampled signal. The comparison circuit receives the sampled signal and compares the sampled signal with a reference signal to generate a comparison result signal. The power manager receives the comparison result signal and adjusts the supply voltage according to the comparison result signal.

Abstract: Systems and methods associated with phase frequency detection are disclosed. In one illustrative implementation, a phase frequency detection (PFD) circuit device may comprise first circuitry and second circuitry having a set input, a reset input, and an output, wherein the set input has a higher priority than the reset input, and additional circuitry arranged and operatively coupled to provide advantageous operation of the PFD circuit device. According to some implementations, for example, systems and methods with clock edge overriding reset features, extended detection range(s), and/or reduction of reverse charge after cycle slipping are provided.

Abstract: A software optimization system isolates an effect of a change in a control variable from effects of ongoing, unknown changes in other variables. The system discards effects due to noise so that effects of interest to a programmer are more easily visible. The software optimization system treats variations in one or more control variables and in the output of the system as signals. The system varies the control variable at a specific frequency unlikely to correlate with uncontrolled variations in external variables. The system uses digital signal processing (DSP) techniques to filter the output, isolating the frequency of the control variable variation. The system then compares the resulting filtered output to the input to determine the approximate effect of the variation in the control variable.

Abstract: A time-to-digital converter (TDC) with fine resolution of less than one inverter delay is described. In an exemplary design, the TDC includes first and second delay paths, a delay unit, and a phase computation unit. The first delay path receives a first input signal and a first reference signal and provides a first output. The second delay path receives a second input signal and a second reference signal and provides a second output. The delay unit delays the second input signal relative to the first input signal or delays the second reference signal relative to the first reference signal, e.g., by one half inverter delay. The phase computation unit receives the first and second outputs and provides a phase difference between the input signal and the reference signal. Calibration may be performed to obtain accurate timing for the first and second delay paths.

Abstract: The disclosure provides an effective means for fine-resolution determination of the frequency content of an RF signal using low speed digital circuits. The disclosure relates to a method and apparatus for decomposing a high frequency RF signal into several low frequency signals or data streams without loss of any information and without the use of extraneous circuit components such as local oscillators, mixers or offset phase-locked loops. Single or multiple phase oscillator outputs are fed directly to a single or multiple direct RF frequency-to-digital (DrfDC) circuits. The front end of the DrfDC circuit decomposes a high frequency signal into several low frequency signals without loss of any information. The low frequency signals are processed by the back-end of the DrfDC and converted into digital data streams. The digital data streams are then combined and averaged to represent the frequency of the input RF signal.

Abstract: A digital phase detector circuit and corresponding monitor and control logic is presented. The digital phase detector has two storage elements, where the data input of the first storage element receives a first clock signal and the data input of the second storage element receives a second clock signal. A time shifter shifts the second clock signal by a shift period, and transmits the shifted signal to the clock input of the storage elements. The signals applied to the data inputs are transmitted from the storage elements when the clock input receives the shifted second clock signal from the time shifter. A monitor and control module samples the data output from the storage elements after each shifted second clock signal is transmitted by the time shifter. The sampling of the output data provides the data used to determine the time relationship between the first and the second clock signals.

Abstract: Methods and apparatuses for retiming of multirate system for clock period minimization with a polynomial time without sub-optimality. In an embodiment, a normalized factor vector for the nodes of multirate graph is introduced, allowing the formulation of the multirate graph retiming constraints to a form similar to a single rate graph. In an aspect, the retiming constraints are formulated to allowed the usage of linear programming methodology instead of integer linear programming, thus significantly reducing the complexity of the solving algorithm. The present methodology also uses multirate constraints, avoiding unfolding to single rate equivalent, thus avoiding graph size increase. In a preferred embodiment, the parameters of the multirate system are normalized to the normalized factor vector, providing efficient algorithm in term of computational time and memory usage, without any sub-optimality.

Abstract: A computer-implemented method, device, and program product for detecting a phase shift between an I data clock and a Q data clock in processing an I data signal or a Q data signal used in quadrature modulation or quadrature demodulation. The method includes: receiving an input of the I data clock and the Q data clock; performing exclusive-ORing (XORing) on the I data clock and the Q data clock; latching a result of the performance of XORing on a phase sampling clock which is asynchronous with the I data clock and the Q data clock; incrementing a first number; incrementing a second number; comparing the incremented first number and the incremented second number and determining, based on a phase determination criterion, a phase shift between the I data clock and the Q data clock; and detecting a phase shift between the I data clock and the Q data clock.

Abstract: A time-to-digital converter (TDC) with fine resolution of less than one inverter delay is described. In an exemplary design, the TDC includes first and second delay paths, a delay unit, and a phase computation unit. The first delay path receives a first input signal and a first reference signal and provides a first output. The second delay path receives a second input signal and a second reference signal and provides a second output. The delay unit delays the second input signal relative to the first input signal or delays the second reference signal relative to the first reference signal, e.g., by one half inverter delay. The phase computation unit receives the first and second outputs and provides a phase difference between the input signal and the reference signal. Calibration may be performed to obtain accurate timing for the first and second delay paths.

Abstract: A time-to-digital converter (TDC) with fine resolution of less than one inverter delay is described. In an exemplary design, the TDC includes first and second delay paths, a delay unit, and a phase computation unit. The first delay path receives a first input signal and a first reference signal and provides a first output. The second delay path receives a second input signal and a second reference signal and provides a second output. The delay unit delays the second input signal relative to the first input signal or delays the second reference signal relative to the first reference signal, e.g., by one half inverter delay. The phase computation unit receives the first and second outputs and provides a phase difference between the input signal and the reference signal. Calibration may be performed to obtain accurate timing for the first and second delay paths.

Abstract: Methods and apparatuses for retiming of multirate system for clock period minimization with a polynomial time without sub-optimality. In an embodiment, a normalized factor vector for the nodes of multirate graph is introduced, allowing the formulation of the multirate graph retiming constraints to a form similar to a single rate graph. In an aspect, the retiming constraints are formulated to allowed the usage of linear programming methodology instead of integer linear programming, thus significantly reducing the complexity of the solving algorithm. The present methodology also uses multirate constraints, avoiding unfolding to single rate equivalent, thus avoiding graph size increase. In a preferred embodiment, the parameters of the multirate system are normalized to the normalized factor vector, providing efficient algorithm in term of computational time and memory usage, without any sub-optimality.

Abstract: Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a plurality of cycles, and during a given one of the cycles, generates a first intermediate signal or a second intermediate signal depending on which of the first and second input signals was received first during that given one of said cycles. The output circuit receives these intermediate signals, and outputs, during said one cycle, a first output signal or a second output signal depending on which one of intermediate signals was received by the output circuit during said one cycle. The reset circuit applies a reset signal to the input circuit under defined conditions to begin a new one of said plurality of cycles.

Abstract: A digital frequency detector and a digital phase locked loop (PLL) are provided. The digital frequency detector includes a first conversion unit which outputs a first frequency as first frequency information of a digital type using a first ring oscillator that operates in a high-level period of the first frequency, a second conversion unit which outputs a second frequency as second frequency information of a digital type using a second ring oscillator that operates in a high-level period of the second frequency, and an operation unit which outputs a digital frequency for the first frequency by calculating a ratio of the first frequency information to the second frequency information.

Abstract: In one embodiment, a phase error signal generated by a phase detector is equalized to compensate for the distortion in the phase error signal due to finite circuit speeds. The equalization may be based on suppressing the low frequency components of the phase error signal. For example, the amplitude of the phase error signal may be reduced when the amplitude of the phase error signal is not changing.

Abstract: A frequency detection circuit and a detection method thereof suitable for a clock data recovery (CDR) circuit are provided. The frequency detection circuit includes a phase detector, a first delayer, a frequency detector, and a logic circuit. The phase detector samples a data signal according to a first clock signal provided by the CDR circuit and provides a phase instruction signal according to the sampling. The first delayer delays the first clock signal to obtain a second clock signal. The frequency detector samples the data signal according to the second clock signal and provides a frequency instruction signal according to the sampling. The logic circuit generates a clock instruction signal according to the phase instruction signal and the frequency instruction signal. The CDR circuit adjusts the frequency of the first clock signal according to the status of the clock instruction signal.

Abstract: PFD includes UP and DOWN signal modules, and RESET signal module. UP and DOWN signal modules transmit UP and DOWN signals according to reference and fed-back clock signals. RESET module includes UP-RESET and DOWN-RESET signal modules. UP-RESET signal module resets UP signal module according to pre-trigger fed-back signal, UP and DOWN signals. Pre-trigger fed-back signal is generated according to original fed-back clock signal and calculation of logic gates and inverting delay module. DOWN-RESET signal module resets DOWN signal module according to pre-trigger reference signal, UP and DOWN signals. Pre-trigger reference signal is generated according to original reference clock signal and calculation of logic gates and inverting delay module.

Abstract: An electronic system (10). The system comprises circuitry (P1) for receiving a system voltage from a voltage supply. The system also comprises circuitry (141), responsive to the system voltage, for providing data processing functionality. The circuitry for providing data processing functionality comprises a critical path (CP1) and the critical path comprises a plurality of transistors. At least some transistors in the plurality of transistors have a corresponding predetermined voltage operating limit corresponding to a predicted lifespan. The system also comprises circuitry (221) for indicating a potential capability of operational speed of the critical path. The system also comprises circuitry (CB) for coupling the system voltage to the critical path. Lastly, the system also comprises circuitry (26) for adjusting the system voltage, as provided by the voltage supply, in response to the circuitry for indicating a potential capability.

Abstract: Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a plurality of cycles, and during a given one of the cycles, generates a first intermediate signal or a second intermediate signal depending on which of the first and second input signals was received first during that given one of said cycles. The output circuit receives these intermediate signals, and outputs, during said one cycle, a first output signal or a second output signal depending on which one of intermediate signals was received by the output circuit during said one cycle. The reset circuit applies a reset signal to the input circuit under defined conditions to begin a new one of said plurality of cycles.

Abstract: A method and apparatus for pre-clocking have been disclosed.

Abstract: A clock tuning device and method for executing overclocking operations on plural elements disposed on a motherboard. The clock tuning device includes a phase-locked loop for outputting a plurality of clock signals to the elements, and a control circuit for controlling the phase-locked loop to adjust the frequencies of the clock signals, so as to execute the overclocking operations on the elements, respectively. The method includes the steps of: increasing the frequency of a first clock signal until one of the elements can't work normally due to an utmost frequency of the first clock signal; resetting all the elements and operating the element corresponding to the first signal according to a safe frequency of the first clock signal; and repeating the above steps to perform overclocking operation on each of the other elements.

Abstract: Methods and systems for locking a phase locked loop (PLL) are disclosed herein. A first impulse signal may be generated utilizing an input reference signal. A second impulse signal may be generated utilizing an input divided signal. A programmable delay signal may be generated based on the generated first impulse signal and the generated second impulse signal. The generation of the first impulse signal and the generation of the second impulse signal may be controlled via the generated programmable delay signal. The generated first impulse signal and the generated second impulse signal may be delayed utilizing a programmable delay. The delayed first impulse signal and the delayed second impulse signal may be ANDed to generate the programmable delay signal, and the generated programmable delay signal may comprise a reset signal.

Abstract: A gated phase-frequency detector circuit includes a phase-frequency detector and a multiplexer circuit. The phase-frequency detector is arranged to provide UP and DOWN signals responsive to a reference clock signal and a feedback signal. Further, the phase-frequency detector includes a first flip-flop that provides the UP signal, a second flip-flop that provides the DOWN signal, and a clear logic circuit. One input of the multiplexer circuit is coupled to the output of the first flip-flop, another input of the multiplexer circuit is arranged to receive a logic high signal, and an output of the multiplexer circuit is coupled to the D input of the first flip-flop. The multiplexer circuit is arranged to multiplex the logic high signal and the UP signal responsive to a reference gate signal. If the reference gate signal corresponds to an active level, logic level of the UP signal does not change.

Abstract: A structure and associated method for reducing a static phase error in a phase-locked loop circuit. The phase-locked loop circuit comprises a voltage controlled oscillator and a phase frequency detector. The voltage controlled oscillator is adapted to provide a first clock signal comprising a first frequency. The phase frequency detector is adapted to compare the first clock signal comprising the first frequency to a reference clock signal comprising a reference frequency. The phase frequency detector comprises a programmable circuit adapted to vary a minimum pulse width of an increment pulse and a minimum pulse width of a decrement pulse. The programmable circuit is further adapted to reduce a static phase error of the phase locked-loop circuit.

Abstract: A clock signal generating device is described, having an oscillator and a PLL connected downstream thereof. The clock signal generating device is distinguished by the fact that a phase shifting device is provided between the oscillator and the PLL. This phase shifting device can temporally shift the edges of the signal output by the oscillator to a variable extent, and feeds the resultant signal to the PLL as an input signal. Such a clock signal generating device makes it possible to realize a spread spectrum oscillator which is constructed in a simple manner and can be made small.

Abstract: A phase-locked loop apparatus includes a ring oscillator including inverters, first and second transistors, a converter, mirror circuits. The first transistors control a current from a first voltage to the inverters. The second transistors control a current from the inverters. The converter converts the voltage output from the filter into a current. The first mirror circuit outputs a current in accordance with the current output from the converters. The second mirror circuit outputs a current according to the current output from the first mirror circuit to control the first transistors. The third mirror circuit outputs a current according to the current output from the second mirror circuit to control the second transistors. The converter, the first and second mirror circuits operate with a second voltage greater than the first voltage, and the ring oscillator and the third mirror circuit operate with the first voltage.

Abstract: A circuit for detecting abnormality of a subject clock signal, includes a frequency dividing circuit for frequency-dividing a monitoring clock signal to provide a frequency-divided monitoring clock signal; a shift register which stores the frequency-divided monitoring clock signal in synchronization with the subject clock signal; and a plurality of abnormality evaluation circuits. The abnormality evaluation circuits operate complementarily each other in accordance with an output signal of the shift register and detect abnormality of the subject clock signal for a period of time corresponding to the cycle of the monitoring clock signal.

Abstract: A phase lock loop system is provided that includes a phase frequency detector device to receive a reference clock signal and a feedback clock signal and to provide a first control signal and a second control signal. The phase lock loop system may include a width control circuit to alter a width of the first control signal and to produce an altered first control signal.

Abstract: A circuit for generating a signal that is proportional to the phase difference between a reference signal and a variable frequency signal. The circuit includes a reference generating circuit for generating N phase shifted reference signals from the reference signal. Each of the phase shifted reference signals has the same frequency and a different phase. The phase of the n.sup.th one of the phase shifted reference signals is equal to 360n/N degrees, where N>1 and n runs from 0 to N-1. A phase detection circuit generates a phase output signal proportional to the phase difference between the variable frequency signal and the phase shifted reference signal currently being outputted by the reference generating circuit. The phase output signal has value of I when the output signal corresponds to a phase difference of 360/N degrees.

Abstract: An asynchronous digital phase detector. The digital phase detector includes an asynchronous state machine which simulates an edge triggered J-K flip flop. Additionally, the digital phase detector includes a reset line. The asynchronous state machine is implemented with logic which provides for optimal phase detector sensitivity and minimal dead zone. The logic within the digital phase detector is implemented with pass-transistors. The channel widths of the pass-transistors are selectively widened or narrowed to further increase the sensitivity of the phase detector.

Abstract: A low-cost microstrip phase detector that is photo-etched onto a circuit board is disclosed. The phase detector is used to detect the phase difference between two high-power radio frequency (RF) signals. One RF signal enters a delay line causing the signal to experience a 180.degree. phase shift. The other RF signal is not phase shifted. Both RF signals are then input into a Wilkinson combiner circuit. The structure of the Wilkinson combiner is such that there is no voltage output from the combiner when the two input signals are exactly 180.degree. out of phase. When the original signals (before the delay line) are in-phase, there is no voltage output from the combiner. However, when the original signals are out-of-phase to begin with, they do not enter the Wilkinson combiner with a 180.degree. phase difference. Instead, the phase difference is greater than or less than 180.degree., depending on whether one input signal leads or lags the other input signal.

Abstract: A data discriminating circuit is provided on the receiver side of a digital signal transmission system, and performs data discrimination with a proper phase relation settled between data and a clock signal. In the discrimination circuit, a data discriminating section discriminates input data in synchronism with a clock signal and outputs resultant data as discriminated data, a phase-relation judging section judges a phase relation between the input data and the discriminated data, a clock phase controller produces a phase control signal to control and initially-determined phase of the clock signal, based on an output of the phase-relation judging section, and a clock phase judging section determines a phase of the clock signal and alters the initially-determined phase of the clock signal in accordance with the phase control signal from the clock phase controller.

Abstract: A sequential phase-frequency detector circuit using precharged logic and a minimum number of transistors is suitable for use in a delay locked loop because of insensitivity to a stuck delay line output signal. The detector receives standard REFERENCE and LOCAL input signals and provides UP and DOWN output signals for control of a charge pump. In one embodiment, the detector includes a pulse generator for isolating the reset of the UP output signal from a stuck delay line output. This feature permits the UP output to be turned ON while the LOCAL input is stuck at a high level. The circuit exhibits improved gain at phase differences of less than 20 pico-seconds, resulting in reduced phase jitter. The isolating feature minimizes frequency acquisition time in applications in which the frequency of the REFERENCE signal is sometimes substantially reduced, such as during an Energy-Star.TM. power-conserving or Slow modes, which typically causes the delay line output to become stuck.

Abstract: A delay element (10) generates a delay pulse (OUT) the length of which is not dependent on an available system clock. The delay element uses oscillators (12a, 12b, 12c) and edge detectors (16a, 16b, 16c) to generate a delay based on the beat frequency of the oscillators. The delay element is suitable for fabrication as part of a CMOS integrated circuit, and requires less layout area than alternative methods.

Abstract: Within the differential detection demodulator, the received signal is first quantized by a limiter amplifier 10 and then subjected to frequency conversion by a frequency converter 50 including: an exclusive OR element 51; a running average generator 52 consisting of a shift register 53 and an adder 54; and a comparator 55. In response to the output of the frequency converter 50, the phase comparator 60 outputs a relative phase signal representing the phase shift of the received signal after frequency conversion relative to the phase reference signal. The phase comparator 60 includes: an exclusive OR element 61; an absolute phase shift measurement means 62 consisting of an adder 63 and D flip-flop arrays 64 and 65; and a D flip-flop 66 serving as a phase shift polarity decision means.

Abstract: A clock control circuit is provided to control the frequency of a microprocessor clock signal and includes a clock management unit which controls the frequency of a timing signal applied to a clock generator and distribution unit, which correspondingly supplies an internal clock signal to a CPU core of the microprocessor. A thermal sensor is integrated with the semiconductor die which forms the microprocessor circuit. An output signal from the thermal sensor is provided to a primary temperature indicator unit and to an auxiliary temperature indicator unit. The primary temperature indicator unit is configured to assert a primary indicator signal when the temperature of the semiconductor die has increased above a first threshold level referred to as the primary threshold level, and the auxiliary temperature indicator unit is configured to assert an auxiliary indicator signal when the temperature of the semiconductor die exceeds yet a second threshold level referred to as the auxiliary threshold level.