Abstract: A glitch filter is provided. The glitch filter receives an input signal and sets a voltage level of an intermediary input node in accordance with a state of the input signal. The glitch filter charges or discharges a switched capacitance based on the voltage level of the intermediary input node and charges or discharges a filter capacitance based on a charge of the switched capacitance. The glitch filter sets a state of an output signal based on the charge of the filter capacitance. The glitch filter includes a reset stage that at least partially filters a burst of glitches in the input signal from the output signal by controlling the charge of the switched capacitance based on the state of the input signal and the state of the output signal.

Abstract: A leakage compensation circuit includes a buffer amplifier, a link coupling element, and a leakage compensation element. The buffer amplifier has an input coupled to a sense node, and an output. The link coupling element has an input coupled to the output of the buffer amplifier, and an output, wherein the link coupling element is unidirectional in a direction from the input to the output thereof. The leakage compensation element has a first current terminal coupled to the sense node, a control terminal coupled to the output of the link coupling element, and a second current terminal coupled to a reference voltage terminal.

Abstract: A driver circuit is provided. The driver circuit includes a differential driver, a first feedback passive circuit and a second feedback passive circuit. The differential driver includes a first half circuit and a second half circuit. The first half circuit has a first input point and a first output point. The second half circuit has a second input point and a second output point. The first feedback passive circuit is coupled to the second input point and the first output point. The second feedback passive circuit is coupled to the first input point and the second output point.

Abstract: This disclosure describes techniques for transferring data from an analog-to-digital converter (ADC) to a host device. The techniques may determine whether an ADC is operating in a quiet conversion time period, and selectively deactivate a digital data output of the ADC when the ADC is operating in the quiet conversion time period. This may allow an ADC to transfer data during both the conversion and acquisition phases of the ADC (rather than just during the acquisition phase), thereby increasing the data throughput of the ADC for a given transfer clock speed. The techniques may further allow data to be transferred during the conversion phase of an ADC without requiring a host device to be aware of the quiet conversion time period requirements of the ADC. In this way, the data throughput of an ADC data transfer may be increased with relatively little additional complexity added to a host device.

Abstract: This document discusses, among other things, a charge regulator configured to optimize charging of an energy storage device by measuring an internal voltage drop of the energy storage device using an open circuit voltage (OCV) across the terminals of the energy storage device during charging and a voltage across the terminals of the energy storage device during charging (CCV).

Abstract: The sample-and-hold device comprises a holding capacitor and operates according to a track phase during which the voltage on the terminals of the capacitor tracks the input signal and according to a hold phase during which the capacitor is isolated from the input signal, it comprises: a differential pair comprising a first transistor Q1 and a second transistor Q2 connected as common emitters, the collector of the transistor Q2 being connected to the holding capacitor, the input signal being applied to the base of the transistor Q1; a third transistor Q3, of which the base is connected to the collector of the transistor Q2 and the emitter is connected to the base of the transistor Q2, the signal present on the emitter of the transistor Q3 forming the output signal of the sample-and-hold device; a current source I connected to the collector of the transistor Q2; during the track phase, the differential pair Q1, Q2 being supplied by a current 2I, the transistor Q2 being charged by the current source and by the h

Abstract: A sample and hold circuit and a method for sampling a signal are disclosed. The sample and hold circuit includes first and second switches, first, second, and third capacitors, and an amplifier. The amplifier receives a signal to be sampled on a first input. The first capacitor is characterized by a first capacitance and has a first terminal connected to an output of the amplifier by the first switch. The second capacitor is characterized by a second capacitance and has a second terminal connected to the output of the amplifier by the second switch. The third capacitor connects the first and second terminals. The amplifier is configured to form a capacitive transimpedance amplifier having the third capacitor as a feedback circuit when the first switch is in a non-conducting state and the second switch is in a conducting state.

Abstract: A zero-crossing detector with effective offset cancellation includes a set of series connected capacitors and an amplifier having an input terminal. An offset capacitor is operatively connected between the amplifier and the set of series connected capacitors. A switch is operatively connected to the input terminal, and an offset sampling capacitor is operatively connected to the switch. The switch connects the offset sampling capacitor to the input terminal of the amplifier during a charge transfer phase.

Abstract: A sampling circuit and a sampling method are provided, where the sampling circuit includes a first delay chain, a second delay chain, and a half-speed binary-phase detector. The first delay chain is used to delay an input signal according to an up signal and a down signal, so as to generate a first delay signal; and the second delay chain is used to delay the first delay signal according to a preset delay value, so as to generate a second delay signal. The half-speed binary-phase detector is used to sample a data signal according to edge trigger of the first delay signal and that of the second delay signal, and generate an output signal, an up signal, and a down signal according to a sampling result of the data signal.

Abstract: A sample and hold circuit and a method for sampling a signal are disclosed. The sample and hold circuit includes first and second switches, first, second, and third capacitors, and an amplifier. The amplifier receives a signal to be sampled on a first input. The first capacitor is characterized by a first capacitance and has a first terminal connected to an output of the amplifier by the first switch. The second capacitor is characterized by a second capacitance and has a second terminal connected to the output of the amplifier by the second switch. The third capacitor connects the first and second terminals. The amplifier is configured to form a capacitive transimpedance amplifier having the third capacitor as a feedback circuit when the first switch is in a non-conducting state and the second switch is in a conducting state.

Abstract: A compensation circuit for eliminating harmonic content resulting from a phase imbalance in a differential sampling circuit. The compensation circuit includes a pair of field effect transistors operating in saturation mode, each field effect transistor coupled in parallel with the differential switch of the sampling circuit, which operates in linear mode. The saturation region transistors across the differential switch allow the harmonic content to flow through the compensation circuit instead of the sampling capacitors of the sampling circuit.

Abstract: A sampling circuit includes a continuous section which is a circuit for transmitting a continuous signal; a digital section for transmitting a signal which is sampled and quantized; and a sampling and holding section for transmitting a signal which is sampled but not quantized between the continuous section and the digital section. The sampling and holding section includes capacitors for accumulating charge generated by an input signal and plural switches for accumulating the charge in the capacitors. The plural switches receive plural clock signals having different operation timings and perform an ON/OFF operation in response to the supplied clock signals.

Abstract: A sampling circuit comprising: an input node; a first signal path comprising a first sampling capacitor and a first signal path switch in a signal path between the input node and a first plate of the first sampling capacitor; a second signal path comprising a second sampling capacitor and a second signal path switch in a signal path between the input node and a first plate of the second sampling capacitor, and a signal processing circuit for forming a difference between a signal sampled onto the first sampling capacitor and a signal sampled onto the second sampling capacitor.

Abstract: A semiconductor circuit which can have stable input output characteristics is provided. Specifically, a semiconductor circuit in which problems caused by the leakage current of a switching element are suppressed is provided. A field-effect transistor in which a wide band gap semiconductor, such as an oxide semiconductor, is used in a semiconductor layer where a channel is formed is used for a switching element included in a switched capacitor circuit. Such a transistor has a small leakage current in an off state. When the transistor is used as a switching element, a semiconductor circuit which has stable input output characteristics and in which problems caused by the leakage current are suppressed can be fabricated.

Abstract: A track-and-hold circuit comprises at least first and second amplifier stages, and switched capacitor circuitry coupled between the first and second amplifier stages. In a track mode of operation of the track-and-hold circuit, the switched capacitor circuitry is configured to decouple inputs of the second amplifier stage from respective outputs of the first amplifier stage and to couple the inputs of the second amplifier stage to a common mode voltage via respective first and second capacitors. In a hold mode of operation of the track-and-hold circuit, the switched capacitor circuitry is configured to couple the inputs of the second amplifier stage to the respective outputs of the first amplifier stage via the respective first and second capacitors. Multiple instances of the track-and-hold circuit may be implemented in parallel in a time-interleaved analog-to-digital converter.

Abstract: An offset canceling circuit stores charge corresponding to a voltage difference between a reset voltage received from a unit pixel and a reference voltage, thereby canceling an offset of the unit pixel.

Abstract: This relates to sampling a feedback signal representative of an output of a power converter. The sampling is performed using a buffer sampling circuit having three sample and hold stages coupled in series to sense and store the feedback signal. The first stage is coupled to sample and hold the feedback signal on a capacitor. If the output diode is conducting, the sampled signal is transferred to the second stage. If the output diode is conducting, the first stage will sample the feedback signal and the sampled signal will be transferred to be sampled and held by the second stage. When the output diode stops conducting, the sampled voltage held by the second stage is transferred to the third stage. The third stage stores the sampled voltage on a capacitor. As such, the controller may sample the feedback signal near the end of the output diode conduction time.

Abstract: A sample and hold circuit is provided. The circuit includes a plurality of switches, a first capacitor, an operational amplifier having a first input selectively coupled to the first capacitor and an output, a second capacitor and a third capacitor both selectively coupled to the first capacitor and both selectively coupled between the first input of the operational amplifier and the output of the operational amplifier, wherein the plurality of switches are configured to receive a plurality of control signals such that the first capacitor is configured to sample an input signal in a sample phase and to transfer a charge to one of the second capacitor and the third capacitor in a hold phase, and the second capacitor and third capacitor are configured to alternate between holding the transferred charge and resetting in any back-to-back hold phases.

Abstract: A sampling circuit of the power converter according to the present invention comprises an amplifier circuit receiving a reflected voltage for generating a first signal. A first switch and a first capacitor are utilized to generate a second signal in response to the reflected voltage. A sample-signal circuit generates a sample signal in response to the disable of a switching signal. The switching signal is generated in accordance with a feedback signal for regulating an output of the power converter. The feedback signal is generated in accordance with the second signal. The sample signal is utilized to control the first switch for sampling the reflected voltage. The sample signal is disabled once the first signal is lower than the second signal. The sampling circuit precisely samples the reflected voltage of the transformer of the power converter for regulating the output of the power converter.

Abstract: A sample and hold circuit is provided. The circuit includes a first switch configured to receive an input, a second switch coupled to a second end of the first switch, a first capacitor coupled to the second end of the first switch, a third switch coupled to a second end of the first capacitor, a fourth switch coupled between the second end of the first capacitor and ground, an op-amp having a first input coupled to the second end of the third switch and a second input connected to ground and an output coupled to the second end of the second switch, a fifth switch coupled to a second end of the third switch, a second capacitor coupled between the output of the op-amp and a second end of the fifth switch, and a sixth switch coupled between the second end of the second capacitor and ground.

Abstract: A low pass filter circuit includes an amplifier having a single-ended output. A first line and a second line are arranged to receive a differential signal. A first switch selectively connects the first line to a first input of the amplifier in a first cycle of operation having a first observation window. A second switch selectively connects the second line to a second input of the amplifier in a second cycle of operation having a second observation window that is at least partially coincident with the first observation window. A signal measuring stage that is supplied with a modulated input signal generates the differential signal. The signal measuring state has an input switch to reverse a polarity of the differential signal applied to the first and second lines of the low pass filter circuit.

Abstract: Circuits and methods for sampling differential input signals having wide input swings including voltages below ground potential, and capable of operating on a single positive supply voltage are disclosed. In an embodiment, the circuit includes a first input switch circuit and a second input switch circuit, a sample and hold circuitry and an operational amplifier. Each of the first and second input switch circuits includes serially connected PMOS switch and NMOS switch for receiving a differential input signal. The sample and hold circuitry includes a first sampling capacitor, a second sampling capacitor and a plurality of switches. The switches are configured to provide the differential input signal to the sampling capacitors for the sampling in a sample phase, and are configured to provide the sampled differential input signal at an output of the operational amplifier in a hold phase.

Abstract: A high-speed BiCMOS double sampling track-and-hold amplifier circuit, comprising an input buffer, two front-end switches, two sampling capacitors, two intermediate buffers, two feedback buffers, two back-end switches and an output buffer. The present invention forms a hold circuit featuring BiCMOS double sampling through the aforementioned components so as to reduce complexities in designing the sampling circuit and the output buffer within the BiCMOS track-and-hold amplifier circuit by means of double sampling, thereby increasing the effective sampling rate to two times. Additionally, the high-speed BiCMOS double sampling track-and-hold amplifier circuit according to the present invention further employs the linearization technology to enhance the linearity of the input buffer in the BiCMOS double sampling track-and-hold amplifier circuit in order to improve the dynamic response of the integral BiCMOS double sampling track-and-hold amplifier circuit.

Abstract: A comparator based circuit with effective offset cancellation includes first and second amplifiers and an offset capacitor operatively connected to the first and second amplifiers. An offset voltage source generates an offset voltage. A first switch connects the offset voltage source to ground during a first time period. The first amplifier generates an output voltage in response to the first switch connecting the offset voltage source to ground during the first time period. A second switch connects the offset capacitor to ground during a second time period. The first switch disconnects the offset voltage source from ground during a third time period, and the second switch disconnects the offset capacitor from ground during the third time period.

Abstract: A zero-crossing detector with effective offset cancellation includes a set of series connected capacitors and an amplifier having an input terminal. An offset capacitor is operatively connected between the amplifier and the set of series connected capacitors. A switch is operatively connected to the input terminal, and an offset sampling capacitor is operatively connected to the switch. The switch connects the offset sampling capacitor to the input terminal of the amplifier during a charge transfer phase.

Abstract: A sample-and-hold (S/H) circuit is provided. The S/H circuit generally comprises a sampling switch, a sampling capacitor, and a correction network. The sampling switch that receives an analog input signal is actuated and deactuated by a timing signal. The sampling capacitor is coupled to the sampling switch at a sampling node so as to receive the analog input signal when the sampling switch is actuated and to store a voltage of the analog input signal when the sampling switch is deactuated. The correction network has at least one row of varactor cells such that each varactor cell is coupled to the sampling node and wherein each varactor cell in the row receives a reference voltage. Additionally, each varactor cell receives at least one of a plurality of control signals.

Abstract: A capacitance interface circuit is provided. An external inductive capacitor is divided into a variable portion and an invariable portion. The capacitance of an internal adjustable capacitor is designed to be equal or close to the fixed capacitance of the external inductive capacitor. The internal adjustable capacitor is used for storing charges having a polarity opposite to that of the invariable portion of the external inductive capacitor in order to neutralize the effect of the invariable portion of the external inductive capacitor. Thus, a charge converter composed of a fully-differential amplifier and feedback capacitors needs only work on the variable portion of the external inductive capacitor, and accordingly the accuracy in subsequent data processing is increased.

Abstract: A capacitor interface circuit is provided. A capacitor under test (CUT) is divided into a variable portion and an invariable portion, and the capacitance of an offset capacitor is designed to equal to or close to the fixed capacitance of the CUT. The offset capacitor is used to store the charges opposite to the invariable portion of the CUT for neutralizing the effect of the invariable portion of the CUT. Thereupon, the charge converter composed by the fully-differential amplifier and the feedback capacitors only responses for the variable portion of the CUT so as to increase the accuracy of the follow-up data processing.

Abstract: To provide a common-mode feedback circuit that feeds back signal corresponding to common-mode components of output terminal voltage of first and second amplifiers to input terminals of the first and second amplifiers via first and second passive elements connected to a common terminal, respectively.

Abstract: A correlated double sampling (CDS) circuit for sampling first and second pixel signals, which are respectively transmitted via first and second data lines, in a pixel array. The CDS circuit includes first and second sampling circuits, an amplifier circuit and a control circuit. The control circuit controls the first sampling circuit to sample a reset level and a data level of the first pixel signal in a first sampling period, and controls the second sampling circuit to sample a reset level and a data level of the second pixel signal in a second sampling period. The control circuit controls the amplifier circuit to output the reset level and the data level of the first pixel signal in a first output period, and output the reset level and the data level of the second pixel signal in a second output period.

Abstract: In pipeline analog-to-digital converters (ADCs) the third harmonic can degrade the performance of the ADC, and conventional circuits that attempt to cancel this third harmonic are oftentimes sensitive to process variation, temperature variation, and common mode variations. Here a correction circuit is provided that includes a compensator that adjusts control voltages for MOS capacitors to generally ensures that the difference between the gate-source voltages and threshold voltages of MOS capacitors is generally maintained across variations of process, temperature, and common mode.

Abstract: A sampling and holding circuit includes an amplifier (A) that amplifies a signal, a holding capacitor (Ch) that stores the signal, and a switch (S) connected between an output terminal of the amplifier and the holding capacitor. In a state in which the switch is on, the amplifier amplifies the signal with a first signal bandwidth, and subsequently, in a state in which the switch is on, the amplifier amplifies the signal with a second signal bandwidth, which is narrower than the first signal bandwidth, and subsequently the switch is turned off while the amplifier still amplifies the signal with the second signal bandwidth.

Abstract: To provide a common-mode feedback circuit that feeds back signal corresponding to common-mode components of output terminal voltage of first and second amplifiers to input terminals of the first and second amplifiers via first and second passive elements connected to a common terminal, respectively.

Abstract: A sample hold circuit and a method for sampling and holding a signal are provided. The sample hold circuit includes a sample unit, a direct current (DC) voltage elimination unit, and a hold unit. When the sample hold circuit is in a first state, the sample unit samples an input signal, and the DC voltage elimination unit lowers a predetermined percentage of the DC voltage in the input signal sampled by the sample unit. When the sample hold circuit is in a second state, the DC voltage elimination unit eliminates the residual percentage of the DC voltage, and the hold unit outputs the alternating current (AC) signal in the input signal sampled by the sample unit.

Abstract: The invention relates to a transconductance amplifier, providing current variations di=k·dv when it receives voltage variations dv. The amplifier comprises a first MOS transistor (MN4) whose drain provides differential currents (I?di, I+di). It comprises an output stage having a second transistor (MP5) of a type opposite to the first, whose source is linked to the drain of the first, whose gate is biased at a constant potential (Vref), and whose drain receives the current variations which are provided by the first transistor and which must be applied to a sampling capacitor.

Abstract: This disclosure describes a capacitive interface circuit for a low power system. The capacitive interface circuit is configured to achieve very low noise sensing of capacitance-based transducers, such as a micro-electro-mechanical system (MEMS)-based sensor, with high resolution and low power. The capacitive interface circuit uses a differential amplifier and correlated triple sampling (CTS) to substantially eliminate, or at least reduce, kT/C noise, as well as amplifier offset and flicker (1/f) noise, from the output of the amplifier. The capacitive interface circuit may further include an output stage that reduces glitching, i.e., clock transients, in the output signal by allowing transients in the amplifier output to settle. In this manner, the circuit can be used in a low power system to produce a stable, low-noise output.

Abstract: A sample-and-hold circuit (100) is provided that that includes a sample-and-hold switch (125), an integrator circuit (180) designed to generate an output voltage (VOUT) signal, and a bias voltage (VBIAS) source (185). The sample-and-hold switch (125) incldues a first switch (130), a second switch (140), and a third switch (150). The first switch (130) has a first gate (132), a first source (134) and a first drain (134), the second switch (140) has a second gate (142), a second source (144) electrically coupled to a bulk region (147), and a second drain (146), and the third switch (150) has a third gate (152), a third drain (154), and a third source (156) coupled to the first source (136). The integrator circuit (180) includes an output operational amplifier (170) having an inverting input (V?) (172) coupled to the second drain (146) and a non-inverting input (V+).

Abstract: Methods and systems for a DC offset correction loop for a mobile digital cellular television environment are disclosed. Aspects of one method may include removing at least a portion of a DC offset from output of an amplifier. The DC offset may be removed from a single stage amplifier, or from each stage of a N stage amplifier, where N may be an integer. The DC offset may be removed by using second differential signals generated from first differential signals, where the second differential signals may be communicated to inputs of the amplifier. The first differential signals may by a first circuit that integrates outputs of the amplifier. The first circuit may perform the integration using a variable corner frequency that may be adjusted by changing a resistance of at least one variable resistor in the first circuit.

Abstract: A peak detect-and-hold circuit and method thereof using ramp sampling technique includes utilizing two sampling signals of different slopes to sample an input voltage for respective tracking voltages; comparing the held tracking voltage sampled with the sampling signal of a smaller slope and the input voltage to determine whether the input voltage is rising or falling, and if the input voltage starts falling, the held tracking voltage sampled with the sampling signal of a larger slope is taken as the peak. The peak detect-and-hold circuit using ramp sampling technique controls respective tracking voltages by comparing the input voltage with the sampling signals rather than the feedback tracking voltage. Also, it uses the input voltage directly rather than an operational transconductance amplifier to charge holding capacitors for the tracking voltages. Therefore, the errors of peak detecting and holding, namely the pedestal voltage, overshoot voltage and voltage droop are reduced.

Abstract: In embodiments of the present invention a device, circuit, and method are described for sampling input signal voltages, which may include voltages below a negative supply voltage for the device or circuit, without requiring static current from the input. Various embodiments of the invention obviate the requirement of an external negative supply voltage or attenuation resistors to allow sampling between a positive and negative voltage range. These embodiments result in a lower power sampling solution as well as simplifying any driver circuitry required by the sampler. The embodiments of the invention may be applied to sampling processes within analog-to-digital converters and may also be applicable to various other types of circuits in which a sampling input having input voltages that are lower than its negative supply voltage.

Abstract: Methods and apparatus are disclosed to track and hold a voltage. An example track and hold circuit comprises a first electronic switch, a second electronic switch, and a current mode logic amplifier.

Abstract: A dual mode, single ended to fully differential converter structure is incorporated into a fully differential sample and hold structure which can be coupled with an ADC as a front end for mixed mode applications. The structure incorporates additional switches which allow negative and positive charges to be sampled on both negative and positive sides of the structure. By inverting the sampled charge on one side, single ended to fully differential conversion is obtained. The structure can be implemented in a compact, generic block which performs single ended to fully differential conversions as well as sample and hold functions, without compromising speed and accuracy in either mode.

Abstract: A sample-and-hold (S/H) circuit is provided. The S/H circuit generally comprises a sampling switch, a sampling capacitor, and a correction network. The sampling switch that receives an analog input signal is actuated and deactuated by a timing signal. The sampling capacitor is coupled to the sampling switch at a sampling node so as to receive the analog input signal when the sampling switch is actuated and to store a voltage of the analog input signal when the sampling switch is deactuated. The correction network has at least one row of varactor cells such that each varactor cell is coupled to the sampling node and wherein each varactor cell in the row receives a reference voltage. Additionally, each varactor cell receives at least one of a plurality of control signals.

Abstract: Provided is a comparator circuit that is capable of operating at high speed and canceling an offset voltage with high precision. The comparator circuit includes a second amplifier circuit for amplifying an output of an amplifier circuit and feeding back the amplified output to an input of the amplifier circuit. When the comparator circuit samples the input voltage, the second amplifier circuit conducts feedback and increases a gain to cancel the offset. Also, when the gain of the amplifier circuit is made lower than the gain of the second amplifier circuit, and the comparator circuit compares the input voltage, the comparing operation can be conducted at high speed by separating the amplifier circuit from the feedback of the second amplifier circuit.

Abstract: A sample-data analog circuit includes a level-crossing detector. The level-crossing detector controls sampling switches to provide a precise sample of the output voltage when the level-crossing detector senses the predetermined level crossing of the input signal. A multiple segment ramp waveform generator is used in the sample-data analog circuits. The ramp waveform generator includes an amplifier, a variable current source, and a voltage detection circuit coupled to the current source to control the change in the amplitude of the current. The ramp generator produces constant slope within each segment regardless of the load condition. The sample-data analog circuit also utilizes variable bandwidths and thresholds.

Abstract: Switches with passive bootstrap that can achieve good sampling performance are described. In one design, a sampling circuit with passive bootstrap includes first and second filters and a switch. The first filter filters an input signal and provides a filtered input signal. The second filter filters a clock signal and provides a filtered clock signal. The switch receives a control signal formed based on the filtered input signal and the filtered clock signal and either passes or blocks the input signal based on the control signal. The first filter may be a lowpass filter having a first corner frequency that is higher than the bandwidth of the input signal. The second filter may be a highpass filter having a second corner frequency that is lower than the fundamental frequency of the clock signal. The first and second filters may both be implemented with one resistor and one capacitor.

Abstract: A correlated double sampling circuit and method for providing the same are disclosed. The circuit may include an amplifier, a plurality of capacitors, and a switch matrix. The amplifier provides a reset voltage replica and a signal voltage replica. The switch matrix controls a plurality of switches to perform correlated double sampling over at least three phases. The first phase for sampling the reset voltage replica on a first and second capacitors. The second phase for sampling the reset voltage replica and the kTC noise on a third capacitor. The first phase producing a thermal kTC noise from the first and second capacitors. The third phase for subtracting a charge representing the signal voltage replica, the kTC noise and the reset voltage replica, combined, from the charge sampled in the second phase to provide an output voltage. The method for providing low noise correlated double sampling includes controlling the plurality of switches to provide the at least three phases.

Abstract: A sample-and-hold amplification circuit comprises an amplifier, a first sample-and-hold unit, and a second sample-and-hold unit. The amplifier has an input terminal and an output terminal. The first sample-and-hold unit is coupled to the input terminal and the output terminal. The second sample-and-hold unit is coupled to the input terminal and the output terminal. When the first sample-and-hold unit is arranged to perform a sampling operation, the second sample-and-hold unit performs a holding operation, and when the first sample-and-hold unit is arranged to perform the holding operation, the second sample-and-hold unit performs the sampling operation.

Abstract: A detection system in which a single sensor is employed to detect an extensive range of a parameter. The output signal from the sensor is fed to the input of the electrical circuit, having a feedback loop, wherein the electrical circuit has a non-linear transfer characteristic. The non-linear transfer characteristic is achieved by changing the behavior of the feedback loop of the electrical circuit at a predetermined level of input signal. The output of the circuit has a proportional relationship with the input until the input signal reaches this predetermined value, whereupon the behaviors of the feedback loop changes and the relationship of the output to the input of the circuit changes. While the input signal is above the predetermined value, the output of the circuit has a linear but disproportionate relationship with the input at a gradient different to that when the input signal is below the predetermined value.

Abstract: A sample-and-hold apparatus and an operating method thereof are provided. The sample-and-hold apparatus includes a sampling amplifier, a transistor, a first switch, a second switch, a sampling capacitor, and a drain-charge unit. A first input terminal of the sampling amplifier receives an input signal. A first-terminal of the transistor is coupled to a first voltage. The first switch is coupled between an output terminal of the sampling amplifier and a gate of the transistor. The first and second terminals of the second switch are coupled to a second terminal of the transistor and a second input terminal of the sampling amplifier, respectively. The first and second terminals of the sampling capacitor are coupled to the gate of the transistor and a reference voltage. The drain-charge unit for draining/providing charges has first and second terminals coupled to the second terminal of the second switch and a second voltage, respectively.