Sample And Hold Patents (Class 327/94)
  • Patent number: 11785805
    Abstract: A display device includes: a plurality of pixels on a substrate, each of the plurality of pixels including a light emitting element and a pixel circuit configured to drive the light emitting element, wherein the pixel circuit of each of the plurality of pixels comprises: a first-first transistor configured to control a driving current flowing through the light emitting element based on a voltage of a first node; a first-second transistor connected in series with the first-first transistor and configured to control the driving current based on a voltage of a second node; a second transistor configured to selectively supply a data voltage to a third node which is a first electrode of the first-first transistor; a third-first transistor connected between the first node and a fourth node which is a second electrode of the first-second transistor; and a third-second transistor connected between the second node and the fourth node.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: October 10, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Keun Woo Kim, Tae Wook Kang
  • Patent number: 11689200
    Abstract: A sampling switch circuit, including an input node, which receives an input voltage signal to be sampled, a sampling transistor having gate, source and drain terminals, the source terminal connected to the input node, a capacitor, a current source configured to cause a defined current to flow therethrough and switching circuitry configured to alternate between a precharge configuration and an output configuration depending upon a clock signal. In the precharge configuration, the switching circuitry connects the capacitor into a current path between said current source and a first voltage reference node to form a potential difference across the capacitor which is dependent on the defined current. In the output configuration, the switching circuitry connects the capacitor between a second voltage reference node and the gate terminal of the sampling transistor so that a voltage level applied at the gate terminal of the sampling transistor is dependent on the defined current.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: June 27, 2023
    Assignee: SOCIONEXT INC.
    Inventors: Vlad Cretu, Masahiro Kudo
  • Patent number: 11682961
    Abstract: An example of a power supply system includes a switching voltage regulator comprising at least one switch configured to conduct an input current to generate an output voltage responsive to a switching signal and based on an input voltage. The system also includes a current regulator configured to generate a current sample voltage based on an amplitude of the input current relative to a reference current defining a maximum average amplitude setpoint of the input current to set a switching time defining a switching period of the at least one switch. The system also includes a switch controller configured to provide the switching signal to control the at least one switch based on an amplitude of the output voltage relative to a reference voltage and based on the switching time.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: June 20, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ivan Shumkov, Erich-Johann Bayer, Ruediger Ganz
  • Patent number: 11336815
    Abstract: A focusing control device that moves a position of a focus lens included in an imaging lens along an optical axis direction. The device comprises a processor configured to execute a process.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: May 17, 2022
    Assignee: FUJIFILM Corporation
    Inventors: Koichi Tanaka, Kenkichi Hayashi, Akihiro Uchida, Seiichi Izawa, Shinichiro Fujiki
  • Patent number: 11328678
    Abstract: A pixel driving circuit includes a driving transistor, a first switch, a second switch, a third switch, a fourth switch, a first capacitor, a second capacitor, an initial-voltage-signal terminal, a data-voltage-signal terminal, and a driving-voltage-signal terminal. The driving transistor includes a gate terminal, a source terminal, and a drain terminal. The first switch is disposed between the gate terminal and the drain terminal. The gate terminal is connected with the initial-voltage-signal terminal via the second switch. The source terminal is connected with the driving-voltage-signal terminal and the data-voltage-signal terminal via the third switch and the fourth switch, respectively. The first capacitor is connected between the gate terminal and a ground terminal. The second capacitor is connected between the gate terminal and the source terminal. A pixel driving method and a display panel are also provided.
    Type: Grant
    Filed: September 27, 2020
    Date of Patent: May 10, 2022
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Xiaolong Chen, Yi-Chien Wen, Ming-Jong Jou
  • Patent number: 11303837
    Abstract: A readout circuit, an image sensor and an electronic device are provided, which could effectively reduce an area and power consumption of the image sensor. The readout circuit includes a plurality of capacitors, a switch circuit and an output circuit; where the plurality of capacitors are connected to the output circuit through the switch circuit; the plurality of capacitors are configured to store output signals of a plurality of pixel circuits, respectively; and the output circuit is configured to output signals stored by the plurality of capacitors through the switch circuit one-by-one.
    Type: Grant
    Filed: December 14, 2019
    Date of Patent: April 12, 2022
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventor: Liang Li
  • Patent number: 11270194
    Abstract: Artificial neural networks (ANNs) are a distributed computing model in which computation is accomplished with many simple processing units, called neurons, with data embodied by the connections between neurons, called synapses and by the strength of these connections, the synaptic weights. An attractive implementation of ANNs uses the conductance of non-volatile memory (NVM) elements to record the synaptic weight, with the important multiply—accumulate step performed in place, at the data. In this application, the non-idealities in the response of the NVM such as nonlinearity, saturation, stochasticity and asymmetry in response to programming pulses lead to reduced network performance compared to an ideal network implementation. A method is shown that improves performance by distributing the synaptic weight across multiple conductances of varying significance, implementing carry operations between less-significant signed analog conductance-pairs to more-significant analog conductance-pairs.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: March 8, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Geoffrey W Burr
  • Patent number: 11271660
    Abstract: There is described a system for lossless sampling and denoising amplification of a signal, comprising: a first phase modulator configured for receiving a wave signal and modulating a phase of the wave signal while satisfying a Talbot condition to obtain a sampled signal; and a second phase modulator configured for receiving the sampled signal, compensating for a given phase induced in the sampled signal by the first phase modulator while satisfying the Talbot condition to obtain a denoised and amplified signal, and outputting the denoised and amplified signal.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: March 8, 2022
    Assignee: Institut national de la recherche scientifique
    Inventors: Benjamin Crockett, Jose Azana, Luis Romero Cortes
  • Patent number: 11264111
    Abstract: An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch coupled to provide an input signal to be sampled, and a second switch coupled to the first switch and to a first capacitor. The S/H circuit further includes a third switch coupled to the second switch and to a second capacitor, and a fourth switch to selectively couple to ground a node between the first and second switches.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: March 1, 2022
    Assignee: Silicon Laboratories Inc.
    Inventor: Mohamed M. Elsayed
  • Patent number: 11252353
    Abstract: A low-noise amplifier is disclosed. The amplifier includes a signal amplifier having an amplifier signal output, a first filter capacitor, a buffer amplifier having a buffer amplifier input and a buffer amplifier output; and a switching network. The first filter capacitor has first and second terminals. The second terminal is connected to a power rail. The amplifier signal output is connected to the buffer amplifier input by a first direct current path and the buffer amplifier output to the first terminal of the first filter capacitor by a second direct current path during a first time period. The amplifier signal output is connected directly to the first terminal of the first filter capacitor by a third direct current path during a second time period, and the amplifier signal output to the first terminal of the first filter capacitor through a resistor during a third time period.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: February 15, 2022
    Assignee: BAE Systems Imaging Solutions Inc.
    Inventors: Hung T. Do, Chenguang Gong, Alberto M. Magnani
  • Patent number: 11190203
    Abstract: A receiver having analog-to-digital converters (ADC) is disclosed. The ADCs may be reconfigured based on the data rate of the receiver. For example, more portions of each time-interleaved ADC may be enabled to support a higher data rate of the receiver and less portions of the ADCs may be used to support a lower data rate of the receiver.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: November 30, 2021
    Assignee: eTopus Technology Inc.
    Inventor: Danfeng Xu
  • Patent number: 11169286
    Abstract: A set of N standard bin count distributions may be generated by irradiating a test radiation detector system with an X-ray beam attenuated by a respective one of N different K-edge filters for each of the at least one X-ray source energy setting. Energy bins of detectors of a target radiation detector system may be calibrated by generating measured bin count distributions for each calibration setting in which a respective one of the N different K-edge filters attenuates a source X-ray beam. Calibration parameters of the detectors of the target radiation detector system may be adjusted to match each of the measured bin count distributions to a corresponding standard bin count distribution. In addition, energy resolution of the radiation detectors can be measured and calibrated by fitting a portion of the measured X-ray spectrum near a K-edge to a fitting function.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: November 9, 2021
    Assignee: REDLEN TECHNOLOGIES, INC.
    Inventors: Elmaddin Guliyev, Georgios Prekas, Michael Rozler, Krzysztof Iniewski, Jean Marcoux, Conny Hansson
  • Patent number: 11132013
    Abstract: Provided is a device connected to a clock and data signal lines, comprising: a voltage input unit configured to be inputted with a clock signal as an input signal from the clock signal line and to generate first reference voltage corresponding to a high level of the clock signal; a reference voltage generation unit configured to be inputted with predetermined input voltage and to generate second reference voltage; a voltage regulation unit for generating regulation voltage by using the second reference voltage to convert a level of the first reference voltage; a drive unit for stepping down the regulation voltage to generate output voltage; a control unit; and an output unit connected with the control unit, the drive unit, and the data signal line, for outputting the output voltage to the data signal line in response to input of a high level of a control signal from the control unit.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: September 28, 2021
    Assignee: Asahi Kasei Microdevices Corporation
    Inventor: Toshio Kaiho
  • Patent number: 11095303
    Abstract: A single-ended to differential circuit is presented. The circuit may be a single-ended to differential integrator or a single-ended to differential amplifier. The circuit determines a first output and a second output voltage based on an input voltage, first and second reference voltages. The circuit has a first, a second and a third input memory element. The circuit in a first phase, samples a voltage indicative of the input voltage on the first input memory element. The circuit in the first phase, samples a voltage indicative of the first reference voltage on the second input memory element. The circuit in the first phase, samples a voltage indicative of the second reference voltage on the third input memory element. The circuit, in a second phase, determines the first and second output voltage based on the sampled voltages on the first, second, and third input memory elements.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: August 17, 2021
    Assignee: Dialog Semiconductor B.V.
    Inventor: Maikel Wagemans
  • Patent number: 11063602
    Abstract: A device having a capacitive sampling structure that allows for removal of sampling noise can be implemented in a variety of applications. Noise cancellation can be achieved by storing on an auto-zero capacitor a scaled replica of kT/C noise by a mechanism of correlated sampling. In an example embodiment, a set of switches can be arranged such that, in switching, scaled thermal noise, generated in an acquisition phase in which a voltage signal is input to an input capacitor structure, is captured on an output capacitor structure and, in a conversion phase, the captured thermal noise is cancelled or compensated from an output of the output capacitor structure.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: July 13, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventors: Rares Andrei Bodnar, Pasquale Delizia
  • Patent number: 11019289
    Abstract: An imaging device includes: a pixel including a photoelectric converter that generates signal charge by photoelectric conversion, and a charge accumulation region that accumulates the signal charge, the pixel being configured to output a signal corresponding to a voltage of the charge accumulation region; a signal line electrically connected to the pixel, the signal being transmitted through the signal line; a first switch that is electrically connected to the signal line and that has input-output characteristics in which an output is linear with respect to an input up to a clipping voltage and the output is clipped at the clipping voltage with respect to the input exceeding the clipping voltage; and a second switch that is electrically connected to the signal line and that has input-output characteristics in which an output is linear with respect to an input.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: May 25, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Makoto Shouho, Masaaki Yanagida
  • Patent number: 10951062
    Abstract: A rectifier circuit rectifies the current that flows through a reception coil. A smoothing capacitor is coupled to the output of the rectifier circuit. A power supply circuit stabilizes the rectified voltage VRECT that occurs across the smoothing capacitor, and supplies the rectified voltage thus stabilized to a load. A dump circuit sinks the first dump current IDUMP from the output of the power supply circuit. A current detection circuit detects the current IOUT that flows through the power supply circuit, and generates a current detection signal S11 that indicates the amount of the current.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: March 16, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Daisuke Uchimoto
  • Patent number: 10897263
    Abstract: A multipath bootstrapped sampling circuit includes a sampling capacitor, a sampling transistor interposed between the sampling capacitor and the analog input signal voltage, two bootstrap capacitors, and a bootstrap switching network periodically transitioning between a holding phase and a tracking phase. The bootstrap switching network includes a primary bootstrap path that drives only one load: the gate terminal of the sampling transistor. One or more auxiliary bootstrap paths drive other transistors in the bootstrap switching network. This absolutely minimizes the parasitic capacitance due to fan-out on the primary bootstrap path. Additionally, the provision of two (or more) bootstrap capacitors allows bulk terminals of transistors on the primary bootstrap path to be connected to an auxiliary bootstrap path, further reducing parasitic capacitance on the primary bootstrap path.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: January 19, 2021
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Daniele Mastantuono, Sunny Sharma, Lars Sundström
  • Patent number: 10892722
    Abstract: Differential sampling circuits may be adversely affected by changes in common mode voltage. Changes in the common mode voltage may alter the on resistance of transistor switches which it turn may mean that small signal changes are not correctly observed against a bigger common mode signal. The present disclosure relates to a way of improving the ability to resolve small differential signal changes by varying the supply or drive voltage to a component to compensate for common mode voltage changes.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: January 12, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventors: Jonathan Ephraim David Hurwitz, George Redfield Spalding, Jr., Seyed Amir Ali Danesh
  • Patent number: 10819360
    Abstract: A ?? modulator includes an input circuit having a sampling capacitor, an integration circuit, a quantizer and a D/A converter having a DAC capacitor. The input circuit takes in an analog input voltage in the sampling capacitor in a sampling period, and transfers a charge to the integration circuit in a holding period. The D/A converter takes in an analog potential, to which selection switches are connected in the sampling period based on a digital output of the quantizer, in the DAC capacitor, and subtracts a charge from the integration circuit in the holding period. At this time, since the input circuit and the D/A converter are set so that the holding periods do not overlap with each other, an error caused by the lowering of a feedback factor is suppressed.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: October 27, 2020
    Assignee: DENSO CORPORATION
    Inventors: Kunihiko Nakamura, Tomohiro Nezuka
  • Patent number: 10771719
    Abstract: The present technology relates to an imaging element that can reduce noise. The imaging element includes: a photoelectric conversion element; a first amplification element that amplifies a signal from the photoelectric conversion element; a second amplification element that amplifies an output from the first amplification element; an offset element provided between the first amplification element and the second amplification element; a first reset element that resets the first amplification element; and a second reset element that resets the second amplification element. The offset element is a capacitor. A charge is accumulated in the offset element via a feedback loop of an output from the second amplification element, and an offset bias is generated. The present technology can be applied to an imaging element.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: September 8, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Toshiyuki Nishihara, Tomohiro Takahashi, Masao Matsumura, Tsutomu Imoto
  • Patent number: 10734090
    Abstract: Systems and methods for a track and hold amplifier with extended dynamic range may include a track amplifier comprising a first PMOS transistor coupled to a first NMOS transistor, a second PMOS transistor coupled to a second NMOS transistor, a capacitor at gates of each NMOS and PMOS transistor, and a plurality of switches. The track and hold amplifier is operable to, during a tracking mode of the track and hold amplifier, couple a differential input signal to each NMOS and PMOS transistor via a first switch coupled to a first capacitor coupled to the gate of the first PMOS transistor and a second capacitor coupled to the gate of the first NMOS transistor, and via a second switch coupled to a third capacitor coupled to the gate of the second PMOS and a fourth capacitor coupled to the gate of the second NMOS transistor.
    Type: Grant
    Filed: June 30, 2019
    Date of Patent: August 4, 2020
    Assignee: Luxtera LLC.
    Inventor: Oleksiy Zabroda
  • Patent number: 10726900
    Abstract: A semiconductor memory device includes: a first bit line; a second bit line connected to the first bit line via a first switch; a charge transfer section including: a first holding section connected to the second bit line, the first holding section being configured to hold a readout voltage from a memory section that stores data, and a second holding section connected to the first bit line, the second holding section being configured to hold a voltage generated due to transfer of charges between the first holding section and the second holding section, the charge transfer section being configured to transfer charges between the first holding section and the second holding section via the first bit line; and a comparison section configured to compare a voltage held in the second holding section with a reference voltage.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: July 28, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Seishi Sano
  • Patent number: 10715356
    Abstract: The present disclosure is directed to systems, apparatuses, and methods for performing continuous or periodic link training. Existing link training protocols generally perform link training only once during startup or initialization of a link and, as a result, are limited in their applications. After link training is performed and Open Systems Interconnect (OSI) data link layer and other high-layer data is transmitted across the link, no further link training is performed using these existing link training protocols. However, parameters of the link may change over time after link training is performed, such as temperature of the link and voltage levels of signals transmitted over the link by the transmitter of the transmitter-receiver pair.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: July 14, 2020
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Magesh Valliappan, Adam Healey
  • Patent number: 10700673
    Abstract: Comparison circuit and delay cancellation method are provided. The circuit includes a control circuit, capacitors and a transconductance amplifier circuit, wherein the control unit is configured to receive an input signal and control the comparison circuit to be in different working stages; the capacitors are configured to store a DC offset voltage signal at an automatic zero calibration stage; store the input signal when the output signal is inverted at a measurement stage; and store an equivalent delay voltage signal at a delay sampling stage; the transconductance amplifier circuit is configured to store the DC offset voltage signal to the capacitors at the automatic zero calibration stage; compare voltage signals on positive and negative input terminals and generate an output signal at the measurement stage; and store the equivalent delay voltage signal to the capacitors at the delay sampling stage. An inherent delay of the comparison circuit may be cancelled.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: June 30, 2020
    Assignee: Wuxi Chipown Microelectronics Co., Ltd.
    Inventors: Leiyi Wang, Yutong Zou, Lixin Zhang
  • Patent number: 10660197
    Abstract: A differential pair group equalization system includes a board providing a differential trace pair group with a plurality of differential trace pairs, each of a transmitter device and a receiver device are coupled to the board and the differential trace pairs in the differential trace pair group. At least one of the transmitter device and the receiver device operates to identify a first differential trace pair in the differential trace pair group, and adjust second differential trace pair equalization parameters for a second differential trace pair in the differential trace pair group. If it is determined that first differential trace pair signal transmission capabilities for the first differential trace pair have improved in response to the adjustment of the second differential trace pair equalization parameters for the second differential trace pair the second differential trace pair equalization parameters are set for the second differential trace pair.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: May 19, 2020
    Assignee: Dell Products L.P.
    Inventors: Wade Andrew Butcher, Bhyrav M. Mutnury
  • Patent number: 10560555
    Abstract: The present disclosure is directed to systems, apparatuses, and methods for performing continuous or periodic link training. Existing link training protocols generally perform link training only once during startup or initialization of a link and, as a result, are limited in their applications. After link training is performed and Open Systems Interconnect (OSI) data link layer and other high-layer data is transmitted across the link, no further link training is performed using these existing link training protocols. However, parameters of the link may change over time after link training is performed, such as temperature of the link and voltage levels of signals transmitted over the link by the transmitter of the transmitter-receiver pair.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: February 11, 2020
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventor: Adam Healey
  • Patent number: 10515709
    Abstract: A sample-and-hold circuit of the disclosure includes: a differential pair that includes a first MOS transistor and a second MOS transistor, in which respective source terminals of the first MOS transistor and the second MOS transistor are interconnected to a specified node, and an input signal is input to a gate terminal of the first MOS transistor; a capacitor that is coupled to a gate terminal of the second MOS transistor, and samples and holds the input signal; a switch transistor that has a source terminal coupled to the capacitor and the gate terminal of the second MOS transistor, and causes the capacitor to sample and hold the input signal upon application of a predetermined ON voltage; and an ON-voltage control transistor that couples a gate terminal of the switch transistor to the specified node when causing the input signal to be sampled and held.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: December 24, 2019
    Assignee: SONY CORPORATION
    Inventors: Masaru Chibashi, Ken Kikuchi, Takaaki Sugiyama
  • Patent number: 10511296
    Abstract: The present invention relates to a system and a method for pulse width modulation and demodulation of a continuous input signal, which system is configured to receive a continuous input to an analog modulator, which system comprises a demodulator generating a continuous output signal. It is the object of the pending patent application to use an analog modulator for transmitting the signal from the input stage over to an output stage. A further object of the pending patent application is to preserve the signal integrity in regard to precision and to minimize both non-linearities and distortion side effects.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: December 17, 2019
    Assignee: PR Electronics A/S
    Inventors: Stig Alnøe Lindemann, Dan Vinge Madsen
  • Patent number: 10438677
    Abstract: A sample-and-hold circuit is broken down into multiple parallel modules, and an output switch, where each module includes a switch and a capacitor. Each of the switches in the modules and the output switch are controlled by different phases of a clock signal. The sample-and-hold circuit receives an input signal and operates in sample and hold modes to generate a sampled output signal.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: October 8, 2019
    Assignee: NXP B.V.
    Inventors: Sushil Kumar Gupta, Hitesh Kumar Garg
  • Patent number: 10361684
    Abstract: A pulse-width-to-voltage (“PWV”) converter, comprises: a switch, a capacitor, a current source, and a current sink. The switch is operable by a signal. The current source, the current sink, and the switch are serially connected across a high voltage potential and a low voltage potential. An output node is coupled to a serial connection between the current source and the current sink. An end of the capacitor is coupled to the output node for converting a current into a control voltage indicative of a duty cycle of the signal.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: July 23, 2019
    Assignee: Invecas, Inc.
    Inventors: Venkata N. S. N. Rao, Majid Jalali Far, Prasad Chalasani, Aram Martirosyan
  • Patent number: 10236765
    Abstract: A switched-capacitor circuit is described herein. In accordance with one exemplary embodiment the switched-capacitor circuit includes a first input node and a second input node and an input switch unit. The input switch is connected to the first input node and the second input node and has a first output node and a second output node. A first capacitor is coupled to the first output node of the input switch unit, and a second capacitor is coupled to the second output node of the input switch unit. The input switch unit includes a plurality of switches configured to con-nect and disconnect one of the first and second input nodes and one of the first capacitor and the second capacitor. The input switch unit further includes a first charge pump coupled to the first input node and a second charge pump coupled to the second input node.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: March 19, 2019
    Assignee: Infineon Technologies AG
    Inventor: Clemens Kain
  • Patent number: 10186328
    Abstract: A current sampling and holding circuit is disclosed. The current sampling and holding circuit includes: a canceling circuit, connected in series between a VDD terminal and a current sensor, being conducted according to a first enable signal, and configured to output a current to cancel a direct-current component in the current sensor; and a mirroring circuit, connected in parallel between the VDD terminal and a ground voltage with the canceling circuit and the current sensor connected in series, and being conducted according to a second enable signal inverse to the first enable signal, and configured to perform current transfer according to a current difference between a mirror current of a shunt current and an output current of the current sensor. According to the present application, the setup speed of the current sampling and holding circuit is improved, and the noise output by the current sampling and holding circuit is reduced.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: January 22, 2019
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventor: Mengwen Zhang
  • Patent number: 10185339
    Abstract: A voltage regulator that provides feedforward cancellation of power supply noise is disclosed. The voltage regulator includes a process tracking circuit that receives a supply voltage and generates a proportional voltage. A tracking capacitor is coupled to the process tracking circuit and generates an injection voltage based on the proportional voltage. An Ahuja compensated regulator generates a regulated voltage. The injection voltage is provided on a feedback path of the Ahuja compensated regulator.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: January 22, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shuaeb Fazeel, Eeshan Miglani, Visvesvaraya Pentakota, Shagun Dusad
  • Patent number: 10078395
    Abstract: Disclosed herein is an electronic device including a display layer generating display noise based on scanning thereof and a sensing layer including a plurality of sense lines. The display noise is capacitively coupled from the display layer to each of the plurality of sense lines of the sensing layer. A differential charge converter circuit has first and second differential inputs respectively coupled to corresponding ones of the plurality of sense lines, and first and second reference inputs. The first and second reference inputs of the differential charge converter circuit are coupled to voltage references during a reset period, and are decoupled from the voltage references during a scan period.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: September 18, 2018
    Assignee: STMicroelectronics Asia Pacific Pte Ltd
    Inventors: Hugo Gicquel, Leonard Liviu Dinu
  • Patent number: 9998077
    Abstract: An apparatus includes an amplifier having a first input and a second input. A first feedback resistor is coupled to the first input and has a first body terminal coupled to a first bias terminal. A second feedback resistor is coupled to the second input and has a second body terminal coupled to a second bias terminal.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: June 12, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Arash Mehrabi, Zongyu Dong, Vijayakumar Dhanasekaran, Dongyang Tang, Chien-Chung Yang
  • Patent number: 9923568
    Abstract: An analog-to-digital converter (ADC) that uses voltage-based signal processing and time-based signal processing to convert an analog input signal to a digital output signal is disclosed. In some embodiments, the ADC has a voltage-based signal processing element configured to receive an input signal and to generate a first digital signal having a plurality of most significant bits and a residue voltage. A residue offset circuit is configured to provide a residue offset voltage to the residue voltage. A voltage-to-time conversion element is configured to convert a sum of the residue voltage and the residue offset voltage to a time domain representation, and a time-based signal processing element is configured to convert the time domain representation to a second digital signal having a plurality of least significant bits.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: March 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Martin Kinyua
  • Patent number: 9893738
    Abstract: An analog-to-digital converter includes a sample hold circuit configured to receive an analog input signal based on an operating mode, the operating mode being one of at least two modes including a sample mode and a hold mode. The sample hold circuit includes a first transistor including a control terminal and a first terminal, the first transistor configured to receive a control signal via the control terminal and receive the analog input signal via the first terminal. The analog-to-digital converter further includes a bootstrap switch operationally connected to the control terminal and the first terminal of the first transistor, the bootstrap switch configured to form a first current path from a power source based on the analog input signal and a boosted voltage of the control terminal of the first transistor in the sample mode, the control terminal bing along the first current path in the sample mode.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: February 13, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-hoon Lee, Seung-hyun Oh, Jong-woo Lee
  • Patent number: 9881551
    Abstract: A drive circuit for a light emitting element which can correct a threshold voltage of a drive transistor between two reference voltages without a reset power supply. The drive circuit includes a light emitting element, a drive transistor for controlling an amount of current, a first switching element that is arranged between the light emitting element and the drive transistor, a second switching element that is arranged between the drive transistor and the second reference voltage, a third switching element that is arranged between a gate, and one of a source and a drain of the drive transistor, a fourth switching element that is connected to the other of the source and the drain of the drive transistor, and controls input of signal voltage, and a first capacitor connected to the gate of the drive transistor.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: January 30, 2018
    Assignee: Japan Display Inc.
    Inventors: Toshio Miyazawa, Mitsuhide Miyamoto
  • Patent number: 9798347
    Abstract: A tracking current sense system is described that includes a current source and a current control device. The current source alternatively and substantially replicates a first current flowing through a first switch and a second current flowing through a second switch. The current control device configures the current source to alternate between replicating the first current and the second current.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: October 24, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Adriano Sambucco, Karl Norling
  • Patent number: 9768794
    Abstract: An analog-to-digital converter includes a switched capacitor circuit, an analog-to-digital conversion circuit, and a constant current circuit. The switched capacitor circuit includes first and second input terminals for a differential input, and is configured to sample an analog voltage of the differential input. The analog-to-digital conversion circuit is connected to output terminals of the switched capacitor circuit, and configured to convert the sampled analog voltage into a digital signal and output the digital signal. The constant current circuit is connected to at least one of the first and second input terminals.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: September 19, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yusuke Wada
  • Patent number: 9741449
    Abstract: Aspects of various embodiments of the present disclosure are directed to applications utilizing voltage sampling. In certain embodiments, a sample and hold circuit is configured to sample voltages that exceed a tolerance voltage of components. The circuit includes a first and a second capacitors. In a first mode, a voltage difference between an input node and a first reference voltage is sampled using the first capacitor. Also in the first mode, a voltage stored by the second capacitor is referenced to a second reference voltage and provided to a first output node. In a second mode, a voltage difference between an input node and a first reference voltage is sampled using the second capacitor. Also in the second mode, a voltage stored by the first capacitor is referenced to the second reference voltage and provided to a second output node.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: August 22, 2017
    Assignee: NXP USA, Inc.
    Inventors: Pedro Barbosa Zanetta, Marcos Mauricio Pelicia
  • Patent number: 9664713
    Abstract: A tracking current sense system is described that includes a first current tracking system, a second current tracking system, and a pre-biasing device. The first current tracking system is configured to replicate a first current flowing through a first switch and the second current tracking system is configured to replicate a second current flowing through a second switch. The pre-biasing device is configured to pre-bias the second current tracking system based on first information detected at the first current tracking system that is indicative of the first current and also, pre-bias the first current tracking system based on second information detected at the second current tracking system that is indicative of the second current.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: May 30, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Adriano Sambucco, Karl Norling
  • Patent number: 9666271
    Abstract: To provide a semiconductor device which can write and read a desired potential. The semiconductor device includes a first transistor (Tr), a second Tr, and a capacitor. In the semiconductor device, operation of writing data is performed by a first step and a second step. In the first step, a low voltage is applied to a bit line and a first wiring to turn on the first Tr and the second Tr. In the second step, a first voltage is applied to the first wiring, and application of the low voltage to the bit line is stopped. Operation of reading the data is performed by a third step and a fourth step. In the third step, a high voltage is applied to the first wiring. In the fourth step, application of the high voltage to the first wiring is stopped, and a low voltage is applied to a capacitor line.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: May 30, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tatsuya Onuki
  • Patent number: 9590604
    Abstract: An apparatus includes a current-to-voltage converter configured to convert first and second currents into first and second input voltages and provide the first and second input voltages to first and second nodes, respectively, and a current difference determination circuit configured to determine a difference between the first and second currents based on a difference between the first and second input voltages. A method includes converting first and second currents into first and second input voltages to output the first and second input voltages to first and second nodes, respectively, and determining a difference between the first and second currents based on a difference between the first and second input voltages.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: March 7, 2017
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Xiaoang Li, Wai Lau, Yuan Lu
  • Patent number: 9583213
    Abstract: A positive/negative sampling and holding (S/H) circuit is disclosed herein. The positive/negative S/H circuit includes an operational amplifier, a first capacitor, a second capacitor being parallel with the first capacitor and forming an integration circuit with the operational amplifier, and several discharge switches correspondingly connecting discharge paths of the first and the second capacitors to control the first and the second capacitors to output a first sampling signal and a second sampling signal respectively, and herein, the first and the second sampling signals has the same magnitude but opposite voltage polarities.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: February 28, 2017
    Assignee: EGALAX_EMPIA TECHNOLOGY INC.
    Inventors: Chin-Fu Chang, Guang-Huei Lin
  • Patent number: 9525404
    Abstract: The input circuit includes a first switch control circuit that controls a first switch and a second switch. The first switch control circuit turns off the first switch and the second switch in a first period during which a first input signal and a second input signal are DC signals. The first switch control circuit turns on the first switch and the second switch in a second period during which the first input signal and the second input signal are AC signals.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: December 20, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryota Terauchi, Shinsuke Fujii
  • Patent number: 9525409
    Abstract: A signal gate is provided where the gate can be low impedance to allow a signal to pass or be high impedance to block it. The signal gate has two output nodes arranged such that during the blocking mode spurious signals passing through the gate by way of parasitic components are presented as common mode signals at the output nodes.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: December 20, 2016
    Assignee: Analog Devices Global
    Inventors: Christopher Peter Hurrell, Alan Bannon, Michael Coln
  • Patent number: 9524796
    Abstract: Disclosed herein is a shift register circuit that is formed on an insulating substrate with thin film transistors having channels of the same conductivity type and includes shift stages, each of the shift stages including: a first thin film transistor; a second thin film transistor; a 3(1)-th thin film transistor; a 3(2)-th thin film transistor; a 4(1)-th thin film transistor; a 4(2)-th thin film transistor; a fifth thin film transistor; and a sixth thin film transistor.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: December 20, 2016
    Assignee: Sony Corporation
    Inventor: Seiichiro Jinta
  • Patent number: 9411987
    Abstract: Certain aspects of the present disclosure provide various sampling networks for switched-capacitor integrators, which may be used in switched-capacitor analog-to-digital converters (ADCs). Rather than having both an input sampling capacitor and a reference sampling capacitor, certain aspects of the present disclosure use a shared sampling capacitor for the reference voltage and the input voltage, thereby reducing ADC input-referred noise, decreasing op amp area and power, and avoiding anti-aliasing filter insertion loss. Furthermore, by sampling the reference voltage during the sampling phase and sampling the input voltage during the integration phase using the shared sampling capacitor, a high-bandwidth reference buffer need not be used for the reference voltage.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: August 9, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Dinesh Jagannath Alladi, Yuhua Guo