Abstract: An arrangement for generating a digital, downconverted complex baseband signal from a bandpass signal comprises a signal source for providing first and second clock signals at first and second clocking rates, respectively. The first clocking rate is at four times the expected center frequency of the bandpass signal, and the second clocking rate is at an exact subharmonic frequency of the bandpass frequency. The bandpass signal is sampled by a composite sampling event of two sampling pulses which occur once during each period of the second clocking signals and which are time-spaced from each other by the inverse of the first clocking rate. The complex baseband samples are ready as an A/D converter output, with no requirement for DSP processing to complete the downconversion to zero-IF.

Abstract: Digital frequency demodulation is accomplished by monitoring similar transitions in an FM radio signal to determine frequency. Time intervals between similar transitions in the FM signal are established by selecting anticipated transition times and accumulating error values relative to actual transition times. Accumulated error values provide a basis for further selecting anticipated transition times in such manner that a reported sequence of anticipated transition times provides a basis for inferring signal frequency. In one illustrated embodiment, the chosen transition times are positive transitions in the FM signal and the anticipated times of transition are taken from a set of two time periods, an early transition and a late transition relative to a valid transition window. In one embodiment of the invention, accumulated error is stored in an integrator device while in another embodiment accumulated error is stored in the phase of a bi-frequency oscillator.

Abstract: The digital FM demodulation apparatus includes a sampling unit, a frequency specifying unit, and a demodulated value specifying unit. The sampling unit samples an FM modulated wave at predetermined intervals. The frequency specifying unit specifies a frequency of the FM modulated wave at the time of sampling based on a plurality of sampled values. The demodulated value specifying unit specifies a demodulated value corresponding to the frequency to provide the demodulated value.

Abstract: Symbols (18) of a burst (12) are sub-divided into symbol sections (20). Each symbol section (20) is sampled and converted into polar coordinates. A buffer bank (38) selectably delays the samples and replays a preamble (14). A demod bank (40) includes a coherent demod (58) and several differential demods (60). Each differential demod (60) processes its own stream of symbol sections (20). The differential demods (60) feed a preamble detector (66) and a symbol synchronization circuit (62). The symbol synchronization circuit (62) identifies the symbol section (20) which yields the smallest magnitude of frequency errors. This symbol section (20) is processed by the coherent demod (58) to acquire carrier phase and recover data. The coherent demod (58) is implemented in the phase domain so that only oscillation signal phase data need be generated in phase locked loops.

Abstract: In a digital frequency demodulator, data representing the input signal to be demodulated is prestored in a look-up table and signal processing is digitally performed to generate a read address required for reading out the data stored in the look-up table using a phase shift method of operation. Phase-shifting is performed by determining the slope of a frequency-modulated signal containing a signal which does not cross the zero axis. Thus, the precision of the frequency demodulation is enhanced, and the frequency demodulation data stored in the look-up table is minimized to reduce the size of a ROM used for the look-up table.

Abstract: A demodulator (414) for improving bit error rate performance where alternating bit patterns produce the worst occurrences of bit errors. The demodulator (414) consists of a zero threshold comparator circuit (502), a first threshold detector circuit (508), and a second threshold detector circuit (504). The zero threshold comparator circuit (502) receives a frequency information signal and slices it into a plurality of bits (522). The first threshold detector circuit (508) compares the frequency information signal to a predetermined threshold, which is selected to optimize bit error rate performance. The second detector threshold circuit (504) is used to ensure that an alternating bit pattern has occurred.

Abstract: Digital frequency demodulation is accomplished by monitoring similar transitions in an FM radio signal to determine frequency. Time intervals between similar transitions in the FM signal are established by selecting anticipated transition times and accumulating error values relative to actual transition times. Accumulated error values provide a basis for further selecting anticipated transition times in such manner that a reported sequence of anticipated transition times provides a basis for inferring signal frequency. In one illustrated embodiment, the chosen transition times are positive transitions in the FM signal and the anticipated times of transition are taken from a set of two time periods, an early transition and a late transition relative to a valid transition window.

Abstract: Method and apparatus for recovering a message signal from a carrier signal. More specifically, method and apparatus for demodulating a frequency modulated signal using measured time intervals between zero-crossings of a received carrier signal. The method and apparatus employing averaging techniques to provide a more accurate signal representing the message signal. The method and apparatus employing mapping techniques to provide a more accurate signal representing the message signal.

Abstract: A subscriber unit for wireless communication with a base station in a wireless subscriber communication system includes a FIR chip, a DIF (digital intermediate frequency) chip, a single processor chip and a radio. The processor chip transcodes a digital voice input signal to provide digital input symbols; demodulates an output signal received from the base station to provide digital output symbols; and synthesizes a digital voice output signal from the digital output symbols. The FIR chip FIR filters the digital input symbols and generates timing signals for timing the transcoding and synthesizing operations in the processor chip. The DIF chip digitally synthesizes a digital intermediate frequency signal by direct digital synthesis (DDS) and modulates the digital intermediate frequency signal with the filtered input symbols to provide a modulated intermediate frequency input signal. The radio further processes the modulated input signal for transmission to the base station.

Abstract: A method and an apparatus for demodulation with adaptive phase control in quasi-coherent detection, capable of compensating detection phase error due to the initial phase error and the frequency error at high speed and high quality, without a complicated circuit configuration and a significant delay. In the apparatus, a frequency error in the modulated complex input signals is estimated by using a phase variation during one symbol due to the frequency error according to the modulated complex input signals and the demodulated complex signals for present and immediately previous symbols; an initial phase error in the modulated complex input signals is estimated according to the modulated complex input signals, the demodulated complex signals, and the estimated frequency error; and the demodulated complex signals are obtained by applying optimum phase compensation determined according to the estimated frequency error and the estimated initial phase error, to the modulated complex input signals.

Abstract: A digital demodulator provides efficient demodulation of frequency modulated, pulse-width modulated, and other temporally modulated signals. Without employing an analog-to-digital converter, modulating signal information is extracted from a modulated signal as numerical information. For frequency demodulation, a high gain stage is applied to an incoming FM signal to produce a corresponding sequence of square waves. The period between zero-crossings of the square waves is accurately measured to within one clock pulse using a high-speed clock and at least one counter to produce a demodulated signal.

Abstract: An FM or PM signal is demodulated so that the cycle time of the modulated input signal is measured using a time-to-digital converter comprising a counter that uses a moderate clock frequency as a reference clock, a digital delay line interpolator and a control circuitry. The counter is used for rough digitization and the delay line for interpolating the moment of zero-crossing inside a clock cycle. Total delay of the delay line, i.e., the range of time intervals the interpolator is able to measure, is actively kept equal to the cycle time of the reference clock. When the number of delay elements in the delay line is a power of two, the result of the delay line interpolator may be used directly as the least significant bits of the measurement.

Abstract: A digital demodulator provides efficient demodulation of frequency modulated, pulse-width modulated, and other temporally modulated signals. Without employing an analog-to-digital converter, modulating signal information is extracted from a modulated signal as numerical information. For frequency demodulation, a high gain stage is applied to an incoming FM signal to produce a corresponding sequence of square waves. The period between zero-crossings of the square waves is accurately measured to within one clock pulse using a high-speed clock and at least one counter. Period information is then provided to a signal processor that serves to convert the sequence of period measurement values into a demodulated signal with a high signal-to-noise ratio.

Abstract: An FM demodulating apparatus suitable for use in a VTR or the like has a suppressing circuit for suppressing the upper and lower sideband components of an FM modulated video signal, an FM demodulation circuit for demodulating the output from the suppressing circuit and a recovering circuit connected to the output of the FM demodulation circuit for recovering the sideband components suppressed by the suppressing circuit, to thereby provide a favorable demodulation.

Abstract: Upon transmission, when the digital transmission mode is set, an analog audio signal is A/D converted, the digital audio signal is coded, a first carrier is modulated by the coded signal and multiplied by a first multiplier, and the multiplied signal is sent to an orthogonal modulating and D/A converting circuit. When the analog transmission mode is set, a second carrier is modulated by the digital audio signal and multiplied by a second multiplier, and the multiplied signal is sent to the orthogonal modulating and D/A converting circuit. A signal of a frequency which is equal in both of the digital transmission mode and the analog transmission mode is given to the orthogonal modulating and D/A converting circuit. Upon reception, when the digital transmission mode is set, an output of an A/D converting and orthogonal demodulating circuit is frequency divided by a first frequency divider and demodulated and decoded.

Abstract: A frequency detection system is based on a digital phase locked loop, the detection system being especially suitable for use in noisy environments like supervisory audio tone (SAT) detection in AMPS and TACS mobile telephone systems. In addition to the digital phase locked loop (4), the frequency detection system according to the invention incorporates a detector circuit (5), which comprises a detection timer (6) and two phase detectors VI1 (7) and VI2 (8). The timer (6) forms a detection sequence of desired length, at the end of which the output signal (SATVAL) of the detector circuit is updated. The first phase detector VII (7) has a phase window in which it counts those falling edges of the synchronized input signal (SSAT) that coincide with the window. The second phase detector VI2 (8) also has a phase window of its own in which it counts those falling edges of the synchronized input signal (SSAT) that coincide with its window.

Abstract: A digital demodulator provides efficient demodulation of frequency modulated, pulse-width modulated, and other temporally modulated signals. Without employing an analog-to-digital converter, modulating signal information is extracted from a modulated signal as numerical information. For frequency demodulation, a high gain stage is applied to an incoming FM signal to produce a corresponding sequence of square waves. The period between zero-crossings of the square waves is accurately measured to within one clock pulse using a high-speed clock and at least one counter. Period information is then provided to a numerical processor, wherein it is at least scaled and low-pass filtered to produce a high-quality demodulated signal with a high signal-to-noise ratio.

Abstract: An analog angle modulated signal is converted into a digital signal within an A/D converter using a sampling clock having a frequency an integer times higher than the carrier of the angle modulated signal. The digital signal is delayed by one sampling slot within each of four delay circuits connected in series to the A/D converter. The output of the A/D converter and that of the fourth delay circuit are multiplied by -1/2 within respective digital weighting circuits, and the multiplied outputs as well as the output of the second delay circuit are added together to generate an I component level signal. The output of the first delay circuit is multiplied by -1 within another weighting circuit and this multiplied output as well as the output of the third delay circuit are added together to generate a Q component level signal.

Abstract: For an integratable FM demodulator which has an optimal noise behavior and does not require any balancing, the demodulator includes a marker pulse generator (2) having an integrator (22) which is succeeded by a comparator (23), while at the start of each positive and/or negative edge of the limited FM signal, a marker pulse is started and one of a first and second reference signals is applied to the integrator input until a predetermined edge of the reference clock signal appears, and the first and a second reference signals are subsequently applied alternately to the integrator input in dependence upon a reference clock signal applied to the marker pulse generator, the two reference signals being applied to the integrator input during the desired period of time of the marker pulse, each time during equal overall time intervals, and a comparison voltage occurring at the integrator output at the end of the desired period of time, which comparison voltage is detected by the comparator (23), whereupon the starte

Abstract: A digital demodulator for demodulating baseband signals in a radio receiver. The demodulator includes a digital signal processing module for forming a mathematical series adapted for generating demodulation functions. The selection of coefficients for this series is controlled to provide specific demodulation functions as required for the demodulation of different kinds of signals such as amplitude modulated or angle modulated signals using one computational block or element. When demodulating amplitude modulated signals, the coefficients used in the mathematical series provide an approximation to the square root function. When demodulating phase or frequency modulated signals, the coefficients used provide an approximation to the arctangent function.

Abstract: A single substantially non-programmable fully integrated circuit for a digital frequency modulated discriminator is provided whereby frequency variations of a digitized frequency modulated information signal are linearly converted to amplitude variations. Matched pairs of data words from the digitized information signal are used to obtain a phase octant, one of eight equal sectors of the 360 degree spectrum. Further manipulations of the pairs of data words provide a coarse phase measurement, being some integral multiple of .pi./2, and a fine phase correction factor less than or equal to .pi./4 radians. The coarse phase measurement is combined with the fine phase correction factor. The sum is differentiated and demodulated, yielding the original information signal.

Abstract: An integrated circuit FM detector which compensates for variations in semiconductor manufacturing process and temperature employs a pair of serially connected switched capacitor-operational amplifier combinations. The first combination is a frequency to voltage converter which uses a switched capacitor input circuit which is clocked at the frequency of the input signal, an operational amplifier and a feedback resistor. The second combination is a compensation circuit which uses an input resistor, a feedback switched capacitor circuit and an operational amplifier. The feedback switched capacitor circuit is clocked at a fixed rate. Reversal of the roles of the resistor and the switched capacitor in the first and second combinations compensates for both temperature and manufacturing process variations.

Abstract: A sampled data FM demodulator samples the FM signal at intervals of (2n.pi.+.pi./2) radians relative to the FM carrier. Pairs of samples S.sub.n and S.sub.n+1 are square and multiplied together to generate sample values S.sub.n.sup.2, S.sub.n+1.sup.2 and S.sub.n S.sub.n+1. These sample values are lowpass filtered in a filter having a cutoff frequency which substantially attentuates at least the second harmonic of the FM carrier. The low pass filtered samples are then combined according to the relation S.sub.n S.sub.n+1 /.sqroot.S.sub.n.sup.2 S.sub.n+1.sup.2 to generate demodulated output samples.

Abstract: A frequency demodulator which comprises a digital FM demodulating circuit for demodulating an inputted FM signal and outputting a digital demodulated signal, a discriminator for discriminating whether or not the value of the digital demodulated signal from the digital FM demodulating circuit deviates from an upper limit value or a lower limit value set for a normal demodulating range, and a circuit operable on the basis of a result of the discrimination performed by the discriminator for replacing the value of the demodulated signal deviating from the upper limit value or the lower limit value with a compensation value set to a value approximating the upper limit value in the case where the inputted FM signal which has been demodulated is of a type having upper and lower side-bands suppressed and emphasized, respectively, or with a compensation value set to a value approximating the lower limit value in the case where the inputted FM signal which has been demodulated is of a type having upper and lower side-b

Abstract: A telemetry receiver for demodulating subcarrier frequencies is disclosed. The flexibility of the receiver permits it to decode signals from a wide variety of transmitters. In the preferred embodiment, a biomedical digital telemetry subcarrier demodulator employs microprocessor control of a variable bandpass filter and cycle counter. The bandpass of the filter is set by the microprocessor to pass frequencies at and around the center frequency of the desired subcarrier frequency. The counter is preset for the desired number of cycles. In operation, the desired subcarrier frequency is passed by the filter, through a signal shaper, and to the counter. Upon receiving the first cycle, the counter activates a timer, which measure the period of the predetermined number of cycles. The desired signal is the percentage deviation of the subcarrier period from the average subcarrier period.

Abstract: A digital subharmonic sampling converter, for use in an analog IF signal demodulator and the like, includes: an analog-to-digital converter (ADC) means receiving the IF analog signal for conversion to a digital data stream by sampling at a sampling rate frequency substantially equal to 4/(2n+1) times the IF signal frequency, where n is an integer greater than zero. A digital mixer means is used to convert the sampled data to baseband. The interleaved sequential in-phase I data words and quadrature-phase Q data words are then sorted into a pair of concurrent I and Q data word streams.

Abstract: The demodulation circuit includes a Schmitt trigger circuit, first and second monostable multivibrators, a quartz oscillator, first and second low-pass filters, and a comparator. The Schmitt trigger circuit converts a modulated signal modulated by data into a pulse signal. The first monostable multivibrator converts an output from the Schmitt trigger circuit into a PPM signal. The quartz oscillator oscillates at the same frequency as the center frequency of the modulated signal. The second monostable multivibrator is formed on the same chip as the first monostable multivibrator and responsive to an output signal from the quartz oscillator. The second monostable multivibrator generates a signal comprising a pulse train having the same pulse width as that of the PPM signal output form the first monostable multivibrator and a constant pulse separation. The first low-pass filter receives an output from the first monostable multivibrator.

Abstract: In a demodulating circuit, for example, for demodulating an amplitude- or frequency-modulated signal, analog-to-digital converted values are obtained at a plurality of sampling points in each cycle of the modulated signal, such converted values are integrated to provide a calculated integration value for the respective cycle, and the calculated integration value is compared with a maximal integration value derived in the same manner so as to obtain the demodulated output.

Abstract: A complex digital sampling converter, for use with an IF demodulator, includes: an analog-to-digital converter (ADC) receiving the IF analog signal for conversion to a digital data stream by sampling at a sampling rate frequency substantially equal to four times the IF signal frequency; a digital mixer for converting the sampled data to baseband; a sorter for separating the interleaved sequential in-phase I data words and quadrature-phase Q data words into a pair of concurrent I and Q data word streams; and at least one of a circuit for removing the effects of any DC offset in the analog IF signal applied to the ADC, and a circuit for correcting misalignment errors in the concurrent I and Q streams.

Abstract: A multichannel processor for signals modulated onto a common IF frequency includes first and second analog-to-digital converters (ADC) for first and second channels, respectively. Each ADC receives a 4XIF frequency clock for producing digital samples, which are applied to a pair of gates for alternately coupling the digital signal to two signal paths. Each signal path alternately negates and does not negate the signals passing therethrough, thereby generating baseband I and Q signals for that channel. Since each channel has a separate ADC, there may be amplitude and temporal error between the channels. One of the channels is selected as a reference, and uses a pair of interpolators to produce samples representing the I and Q signal values at a common time between clock pulses. The other channels include controllable interpolators which are adjusted so that their I, Q common times correspond to that of the reference channel.

Abstract: Electronic apparatus for receiving amplitude or frequency modulated facsimile signals detects the instantaneous value ( i.e., the amplitude or frequency) of the modulation by a circuit including means detecting the modulation value in each cycle of the signal and producing a gating signal corresponding in duration to the detected modulation value, a generator of clock pulses higher in frequency than the signal, and a modulator responsive to the clock pulse and gating signal to pass a number of clock pulses commensurate with the modulation value to a counter which generates a marking signal commensurate in amplitude to the modulation value for application to a facsimile recorder.