Abstract: A gain-controlled amplifier capable of dealing with the system for performing the receiving operation continuously, and capable of correcting a change of a DC offset owing to an operation condition such as temperature; a receiver circuit using the gain-controlled amplifier; and a radio communication device installing the receiver circuit. In a gain-controlled amplifier composed of three GCA stages (11)–(13) connected by cascade connection, the center value of an output DC of each GCA stage (11)–(13) is kept to be constant by a common feedback circuit (16)–(18) provided correspondingly to each of the GCA stages (11)–(13), and a DC feedback quantity is made to be changed according to a gain control voltage VG by means of a DC feedback circuit (19) provided between an output side of a last stage of the GCA stages and an input side of a first stage of the GCA stages.

Abstract: A power amplifier configuration including power amplifier circuitry and power control circuitry and having improved Power Added Efficiency (PAE) is provided. The power amplifier circuitry includes one or more input amplifier stages in series with a final amplifier stage. The power control circuitry provides a variable supply voltage to the input amplifier stages based on an adjustable power control signal. The final amplifier stage is powered by a fixed supply voltage. In operation, as output power of the power amplifier is reduced from its highest power level, the variable supply voltage is reduced. Accordingly, RF power of an amplified signal provided to the final amplifier stage from the input amplifier stages decreases, and the final amplifier stage transitions from saturation to linear operation, thereby increasing the gain of the final amplifier stage. Thus, a desired output level can be maintained while operating at lower current levels.

Abstract: Disclosed is a direct conversion type transmitter or transceiver circuit suitable for a mobile communication device which corresponds to broad signal output level variable width to be required by W-CDMA, which does not necessitate any high-performance low noise VCO and RF filter, capable of reducing a number of components and the cost. In the input portion of an orthogonal modulator composed of a divider, mixers, and a common load, there are provided variable attenuators. If an input signal level of the orthogonal modulator within the transmitter circuit lowers, this variable attenuator circuit is operated so as to lower the bias of the orthogonal modulator to reduce the amount of occurrence of carrier leak, and to prevent the signal during low output level and carrier leak ratio from being deteriorated.

Abstract: A circuit for providing a base operating voltage for a bipolar transistor includes a UBE multiplier providing, in response to a working-point control current, a working voltage fed to a circuit for reducing the working voltage in order to generate a base operating voltage smaller than a base-emitter voltage drop of a bipolar power transistor. With this, the bipolar power transistor may be maintained in the class C operation in a flexible and robust manner, so that an amplifier with high efficiency is obtained.

Abstract: Systems, devices, and methods are provided for actively biasing a multi-stage amplifier. A method for differentially actively biasing a multi-stage amplifier comprises the steps of: actively biasing, with a single active bias circuit, an amplifier comprising a plurality of amplification stages; and differentially applying the bias provided by the single active bias circuit by biasing at least one amplification stage at a different bias level than another of the plurality of amplification stages. An active bias circuit for a multi-stage amplifier comprises: a single active bias circuit that is configured to actively bias a plurality of amplification stages via at least two gates; and a differential device configured to cause the active biasing provided to one gate to be different from the bias provided to another gate.

Abstract: A system for communicating information includes a variable gain amplifier (VGA) responsive to an input signal and a gain control signal for controlling a gain of the VGA. The system also includes a power amplifier responsive to the VGA. An output power level of the power amplifier is compared to a predetermined reference value to generate the gain control signal. The gain control signal is offset by a gain offset value. To change the output power level of the power amplifier from a first output power level to a second output power level, a first predetermined reference value and a first gain offset value associated with the first output power level are changed substantially concurrently to a second predetermined reference value and a second gain offset value, respectively, associated with the second output power level.

Abstract: A power amplifier includes an input network, output stages, coupled in parallel and configured to output power optimally in corresponding power-ranges, the output stages coupled to the input network, an output impedance matching network, coupled to the output stages and not containing a switching element, and a bias-control network, coupled between the output impedance matching network, the input network, and the output stages. In some amplifiers the output impedance matching network does not contain a switching element corresponding to the output stage configured to output power in the highest range. In other amplifiers the bias-control network is configured to isolate output stages by providing a hard shut-off to transistors of the isolated output stages.

Abstract: A differential circuit and an amplifier circuit for reducing an amplitude difference deviation, performing a full-range drive, and consuming less power are disclosed. The circuit includes a first pair of p-type transistors and a second pair of n-type transistors. A first current source and a first switch are connected in parallel between the sources of the first pair of transistors, which are tied together, and a power supply VDD. A second current source and a second switch are connected in parallel between the sources of the second pair of transistors, which are tied together, and a power supply VSS. The circuit further includes connection changeover means that performs the changeover of first and second pairs between a differential pair that receives differential input voltages and a current mirror pair that is the load of the differential pair. When one of the two pairs is the differential pair, the other is the current mirror pair.

Abstract: A system is provided for adjusting an output power of a multi-stage power amplifier by controlling a supply voltage provided to one or more output amplifier stages of the power amplifier using a switching DC—DC converter. In general, the system includes a power amplifier including an input amplifier stage and one or more output amplifier stages coupled in series with the input amplifier stage. The one or more output amplifier stages receive a variable supply voltage from switching DC—DC conversion circuitry. The switching DC—DC conversion circuitry provides the variable supply voltage based on an adjustable power control signal. By controlling the variable supply voltage provided to the one or more output stages, the switching DC—DC conversion circuitry controls an output power of the power amplifier based on the adjustable power control signal.

Abstract: An amplifier includes a plurality of power amplifier elements connected in cascaded multiple stages, a first bias power supply, a second bias power supply, a switching circuit configured to switch a first output supplied from the first bias power supply in response to a modulation pulse so as to transmit the first output to the plurality of power amplifier elements, a pulse differentiating circuit configured to differentiate the modulation pulse by a given time constant, and an adder circuit configured to add the differentiated modulation pulse and a second output of the second bias power supply so as to transmit the differentiated modulation pulse added to the second output as an input bias voltage to at least one of the plurality of power amplifier elements except for a final stage in the cascaded multiple stages.

Abstract: Providing a high frequency power amplifier circuit and a radio communication system which can control output power by a power voltage, produce sufficient output power in high regions of demanded output power and improve power efficiency in low regions of demanded output power. In a high frequency power amplifier circuit (RF power module) which comprises two or more cascaded FETs for amplification and controls output power by controlling power voltages of the FETs for amplification to gate terminals of which bias voltages of a predetermined level are applied, different transistors for power voltage control are provided for a last-stage FET for amplification and preceding-stage FETs for amplification. The transistors for power voltage control generate and apply the power voltage so that the preceding-stage FETs for amplification saturate when a demanded output level is relatively low.

Abstract: The input stage of the fully differential amplifier output stage is configured in a differential pair configuration with a tail current. The tail current is divided between two legs of the input stage and is higher in the leg that has the higher of the two input voltage levels (in or inb). The devices in each leg of the fully differential amplifier output stage may be cascoded to avoid electrical voltage overstress. The top device in each leg of the differential input stage may be coupled in a diode configuration and is utilized to mirror the current into another NMOS current mirror as well as to a PMOS output device. The gate of the PMOS output devices are connected in a cross-coupled configuration. The NMOS current mirrors are utilized to mirror the current into the NMOS output devices in a non-cross-coupled configuration.

Abstract: The present invention provides a high frequency power amplifier of an open-loop type, which outputs a signal having a level corresponding to an output level required under control of a power supply voltage for each output power FET, based on a control signal for the output level. The high frequency power amplifier is provided with a bias voltage generating circuit which generates a gate bias voltage of each output power FET according to an output voltage of a power control circuit for controlling the power supply voltage for the output power FET, based on the control signal for the output level.

Abstract: A system is provided for substantially reducing variation in AM to PM distortion of a power amplifier caused by variations in RF drive power and temperature. The system includes power control circuitry and power amplifier circuitry. The power amplifier circuitry includes an input amplifier stage and at least one additional amplifier stage coupled in series with the input amplifier stage. The power control circuitry provides a first supply voltage to the input amplifier stage based on a control signal such that the first supply voltage has a predetermined DC offset with respect to the control signal. The first supply voltage is provided such that the predetermined DC offset substantially reduces variations in the AM to PM distortion of the power amplifier due to variations in radio frequency (RF) drive power.

Abstract: A multi-stage variable gain amplifier is disclosed that utilizes overlapping gain curves to compensate for log-linear errors. Each gain stage is configured to approximate a log-linear response with a sinusoidal error term such that a portion of the curve has positive errors and a portion of the curve has negative errors. In operation, the control signal inputs for the gain stages are driven such that the gain curves overlap and positive errors in each stage are offset by negative errors in the adjacent stage. The resulting combined gain is a more log-linear response.

Abstract: The present invention provides a power amplifier module featuring that: its output power characteristic smoothly changes as the input control voltage changes; and its control sensitivity is stable over a wide dynamic range. By same means, idling current for gain setting is supplied to a single amplifier element or all of multiple stages of amplifier elements of the power amplifier module. By making this idling current behave so as to exponentially change, relative to input control voltage, the invention enables output power control proportional to the input control voltage.

Abstract: Wideband low noise amplification is achieved using a serial chain of relatively narrowband LNAs. Each of the narrowband LNAs amplifies a different portion of the overall bandwidth of the wideband amplification system. In at least one embodiment, a buffer amplifier is provided at the end of the chain of LNAs to provide impedance matching over the extended bandwidth.

Abstract: A recording system, such as a magnetic or optical recording system, sets input attenuation level setting and variable gain amplifier (VGA) operating region during zero gain start (ZGS) by sharing the ZGS adjustment between attenuator settings and VGS gain setting. Further adjustment is made to attenuator settings and VGS gain setting for each subsequent servo or read sector event. The input attenuation level setting and variable gain amplifier (VGA) operating region are set so as to minimize effects of gain error due to incorrect attenuator setting, and subsequently operate the VGA near the center of its range where the non-linear effects are minimal.

Abstract: The present invention provides a high frequency power amplification circuit capable of preventing an output power and current consumption from being largely changed even when a load fluctuates in a wireless communication system for detecting an output level necessary for feedback control by a current detecting method. In a high frequency power amplification circuit as a component of a wireless communication system which detects an output level necessary for feedback control by a current detecting method, a capacitive element is interposed between the drain terminal of a power amplification transistor in the final stage and the gate terminal of a transistor constructing a current mirror circuit in a circuit for detecting an output level, and a change in an output power accompanying load fluctuation is reflected in a detection current of the output level detecting circuit.

Abstract: A power supply voltage required on the basis of information of setting transmission power to be output is supplied, thereby minimizing power consumption. A transmission circuit comprises a driver amplifier 3 whose gain is controlled by a first control voltage Vc1 for setting transmission power and a power amplifier 4 connected to the post-stage of the power amplifier 3. A power supply circuit 5 to which the first control voltage Vc1 is input and whose output voltage is controlled by the first control voltage Vc1 is provided. A voltage required for the power amplifier 4 when outputting the transmission power set by the first control voltage Vc1 is supplied from the power supply circuit 5.

Abstract: There are provided an electronic component for high frequency power amplification provided with a high-sensitivity output power detection circuit which is immune to the influence of changes in the use environment thereof, free of an output mismatch, small in size, and low in insertion loss and a wireless communication system using the electronic component.

Abstract: A multistage high frequency power amplifier circuit device has a plurality of semiconductor amplification elements connected in a cascade. The circuit device is provided with a bias control circuit used to control the bias voltage or bias current of the output semiconductor amplification element in each stage so as to reduce the variation of the output power with respect to the power control signal voltage in an area around the threshold voltage of the semiconductor amplification elements. This realizes a high frequency power amplifier circuit device provided with excellent controllability of the output power and high efficiency at the time of low power output realized with use of such a control voltage as a power control signal.

Abstract: An FET band amplifier for reducing a residual noise during gain control. An FET band amplifier 5 included in an AM receiver comprises amplifiers 11 to 15 e.g. at five stages, a BPF 16 inserted halfway in their connection, and an AGC circuit 8. The BPF 16 allows the passage of a component of a band wider than the amplification band of the whole of the FET band amplifier and reduces a 1/f noise by removing a low-band component of a signal output from the amplifier 13 at the third stage and thermal noise by removing the high-band component. This process enables a reduction in a residual noise during gain control included in a signal output from the amplifier 15 at the final stage.

Abstract: A high-power amplification circuit includes a first transistor which amplifies an input signal, a bias circuit which includes a second transistor which is an emitter follower, and supplies a bias current to a base of the first transistor, a constant-voltage power supply connected to the base of the second transistor through a first resistor, a control voltage terminal input one of a first control and a second control voltage, a third transistor including a base connected to the control voltage terminal through a second resistor, a third resistor connected between the base of the second transistor and the collector of the third transistor, and a fourth transistor connected between the base of the second transistor and the third resistor, the fourth transistor being diode-connected.

Abstract: An operational amplifier comprises multiple stages. A differential input stage that includes an adaptive high voltage differential pair generates up and down output currents in response to up and down input voltages. The differential input stage includes adaptive common input high voltage (HV) bias. An intermediate stage converts the up and down output currents into a first output voltage signal. The intermediate stage includes a folded cascode arrangement. The intermediate stage is biased by fixed voltage bias signals. The intermediate stage also includes unaffected slew rate stability compensation and a combined split stability compensation. An output stage includes a class AB source follower driver that generates a second output voltage signal in response to the first output voltage signal. The output stage is biased with an adaptive push-pull source follower output HV bias. The output stage includes feed-forward slew rate enhancement.

Abstract: Analog-valued floating-gate transistors are used as trimmable circuit components for modifying and/or controlling the gain, phase, offset, frequency response, current consumption, and/or transfer function of signal pathways in parallel and/or serial processing circuits in radio frequency, analog, or mixed-signal integrated circuits.

Abstract: A circuit and method for bridging an analog signal between two integrated circuits operating at different supply voltages. The circuit is a two stage fixed gain amplifier. The first stage is a transconductance amplifier and the second stage is an operational amplifier. The first stage converts an input signal from a voltage into a current. The second stage converts the current signal to an output voltage signal.

Abstract: A method is disclosed to operate a dual mode multi-timeslot RF transmitter, as is an RF transmitter that include a control unit that operates in accordance with the method. The method includes, prior to a first timeslot, setting a plurality of control signals for the RF transmitter in accordance with a first modulation format used during the first timeslot; and during a guard period between the first timeslot and a next, temporally adjacent timeslot, setting the plurality of control signals for the RF transmitter in accordance with a second modulation format used during the second timeslot, where the first modulation format differs from the second modulation format.

Abstract: A multi-stage amplifier is coupled with a power detector. The multi-stage amplifier includes a plurality of amplifier stages in series, with a signal path extending through them. The power detector is coupled to an interior node of the amplifier along the signal path, and is operable to sample a first signal being transmitted on the signal path. The power detector outputs a second signal reflective of a power of the first signal. In one embodiment, the interior node is in a matching network of the amplifier disposed between a first amplifier stage and a final amplifier stage of the amplifier. The second signal may be used in a feedback network to adjust an amount of amplification of the first signal by the amplifier.

Abstract: A multi-stage amplifier is coupled with a power detector. The multi-stage amplifier includes a plurality of amplifier stages in series, with a signal path extending through them. The power detector is coupled to an interior node of the amplifier along the signal path, and is operable to sample a first signal being transmitted on the signal path. The power detector outputs a second signal reflective of a power of the first signal. In one embodiment, the interior node is in a matching network of the amplifier disposed between a first amplifier stage and a final amplifier stage of the amplifier. The second signal may be used in a feedback network to adjust an amount of amplification of the first signal by the amplifier.

Abstract: The present invention relates to a lineariser for use with an amplifier and to a method of linearising an amplifier. The lineariser comprises an input to receive an input signal and an output for outputting an adjusted signal. A gain variations adjustment means are provided for adjusting amplitude dependent gain variations of the signal. A phase variations adjustment means are provided for adjusting amplitude dependent phase variations of the signal. Said gain and phase variations adjustment means are adapted to be individually adjustable elements on the signal path between said input and output. A variable gain amplifier is provided on the signal path between the gain variations adjustment means and phase variations adjustment means. The adjusted signal is then input to said amplifier.

Abstract: A multistage differential amplifier with commonly controlled input and output common mode voltages. A shared common mode control signal jointly controls both input and output common mode voltages with a DC gain and bandwidth substantially equivalent to the differential signal gain and bandwidth.

Abstract: The present invention provides a power amplifier module used in a cellular phone or the like. In the power amplifier module, a bias control circuit converts a bias voltage to a current by MOS transistors, whereby a voltage drop is reduced and the value of the bias voltage is lowered. Bias control signals outputted from the bias control circuit are inputted to a high-frequency amplifying unit through low-pass filters. The low-pass filter comprises an inductance, and a condenser. Each of the condensers attenuates an envelope frequency. Each of the inductances suppresses a change in impedance at a carrier frequency of a modulation signal.

Abstract: Disclosed herein is an integratable power amplifier having a variable bias voltage, in which a first bias controller detects the amplitude of an RF signal and outputs a DC signal varying with the detected amplitude based on the non-linearity of a rectification transistor. A second bias controller generates a bias voltage that optimizes amplification efficiency by adjusting the voltage of the DC signal received from the first bias controller through a source follower transistor being a complementary device. An amplifier transistor is activated by a driving voltage, amplifies the input signal according to the bias voltage received from the second bias controller, and outputs the amplified signal.

Abstract: An arrangement for saving energy in a radio device transmitter and a radio device. The steady currents of the transmitter amplifiers are made dependent on the transmitting power for reducing the losses of the amplifiers. The VGA (400) comprises at least one main differential pair (Q41–Q42; Q43–Q44) for controlling the gain and a bias differential pair (Q47–Q48) for controlling said steady currents. These pairs are steered by the one and the same voltage (?V), in which case the output current (Ib1; Ib2) of the bias differential pair changes in the same way as the output current (io1; io2) of the main differential pair when the gain is readjusted. The output current of the bias differential pair is used as a bias current of the transmitter amplifiers, i.e. as a current that determines the steady currents of the amplifiers.

Abstract: The present invention provides a power amplifier module featuring that: its output power characteristic smoothly changes as the input control voltage changes; and its control sensitivity is stable over a wide dynamic range. By same means, idling current for gain setting is supplied to a single amplifier element or all of multiple stages of amplifier elements of the power amplifier module. By making this idling current behave so as to exponentially change, relative to input control voltage, the invention enables output power control proportional to the input control voltage.

Abstract: A high-frequency power amplification electronic part is disclosed which comprises a power amplifier circuit and a bias control circuit, the power amplifier circuit having a plurality of amplifier stages for amplifying an input high-frequency signal, the bias control circuit acting to bias the power amplifier circuit. The power amplifier circuit controls output power in accordance with input power that is varied while a gain of the power amplifier circuit is being fixed by either a bias current or a bias voltage supplied from the bias control circuit.

Abstract: An apparatus and method is disclosed for improving the gain precision and bandwidth of fixed-gain amplifiers, while providing high bandwidth and performance necessary in many applications. Fixed-gain amplifiers, having relatively precise gain, are connected together in a specific architecture to further increase the gain precision and bandwidth over any of the amplifiers operating independently. Due to the configuration of the amplifiers, the absolute gain error of individual amplifiers is substantially canceled such the gain error of the total circuit is greatly reduced. The disclose architecture is useful in many high speed, high bandwidth applications where very precise gain is needed, while avoiding the reduction in bandwidth caused by amplifiers using feedback to achieve gain stability.

Abstract: The present invention relates to a high-frequency power amplifier having differential inputs, and more specifically to a high-frequency power amplifier having differential inputs, in which a structure of an output port of a communication system for 2.4 GHz ISM frequency band can be simplified by designing and producing the high-frequency power amplifier having differential inputs for 2.4 GHz ISM frequency band using a silicon germanium (SiGe) microwave monolithic integrated circuit (MMIC), thereby decreasing the number of components of a transmission unit and reducing a price of the communication system.

Abstract: A variable gain amplifier of low amplitude distortion, and low noise, having a large variable range, is provided. A variable gain differential amplifier that controls a gain by use of bias current is used as each of unit amplifiers (VGAs) making up the variable gain amplifier. A large variable gain range is obtained by series-connecting a plurality of the variable gain differential amplifiers. An attenuator is installed on the input side of the unit amplifier (VGA) at least in the initial stage. By doing so, it becomes possible to prevent amplitude distortion from occurring to the respective VGAs. An attenuator utilizing voltage division by capacitors, generating no noise, is used for lowering noise. Further, the variable gain amplifier is provided with a fixed gain amplifier installed in the final stage as necessary in order to obtain a total gain as desired.

Abstract: An FET band amplifier for reducing a residual noise during gain control. An FET band amplifier 5 included in an AM receiver comprises amplifiers 11 to 15 e.g. at five stages, a BPF 16 inserted halfway in their connection, and an AGC circuit 8. The BPF 16 allows the passage of a component of a band wider than the amplification band of the whole of the FET band amplifier and reduces a 1/f noise by removing a low-band component of a signal output from the amplifier 13 at the third stage and thermal noise by removing the high-band component. This process enables a reduction in a residual noise during gain control included in a signal output from the amplifier 15 at the final stage.

Abstract: A method and apparatus is provided for detecting the output power of an RF power amplifier for purposes of controlling the output power. A circuit for generating an output power control signal includes a power detector to detect the output power of an RF power amplifier. A variable gain amplifier is coupled to the power detector for amplifying the output of the power detector. The value of the generated control signal is a function of the gain of the variable gain amplifier.

Abstract: A gain-control method and device that enable high-speed gain switching of cascaded programmable gain amplifiers (PGA) without a high-resolution A/D converter is provided. In one example, the gain-control method for cascaded PGAs detects all the input levels of the PGAs, calculates the optimum gains of the PGAs each on the basis of the detection results, and sets the obtained optimum gains of each of the PGAs at one time, whereby high-speed gain switching becomes possible. The gain-control device for cascaded PGAs that implements this gain-control method includes peak hold circuits that retain the input levels of each of the PGAs, a switch group that sequentially switches outputs of the peak hold circuits, an A/D converter that sequentially detects the outputs from the switch group, and a control and operation device that calculates the optimum gains of the PGAs from the detection results by the A/D converter to set the calculated optimum gains simultaneously to each of the PGAs.

Abstract: The present invention provides a high frequency power amplifier of a multi-stage configuration in which a plurality of transistors for power amplification are cascaded, with reduced distortion of a signal in a region where an output power level is low and improved power efficiency. In a high frequency power amplifier electric part in which a plurality of transistors for power amplification are cascaded, a transistor for output level detection is provided whose gate terminal receives a gate input of a transistor for power amplification in the final stage via a resistive element of which resistance value is 100 ? or less. Current detected by the transistor is converted to voltage. The voltage is compared with output control voltage by an error amplifier. Voltage according to the potential difference is applied to the gate terminals of the transistors for power amplification in the amplification stages to thereby pass idle current.

Abstract: Prior art architectures of power amplifiers employ a substantial die area, and utilize multiple integrated circuit technologies with a net higher manufacturing cost and large associated packaging area. A new scheme is presented wherein several sense and control signals are used to provide fine and gross control over the key figures of merit associated with integrated semiconductor power amplifiers. How and where these sense and control signals are used is crucial to achieving the most manufacturable and most economic integrated amplifier. In accordance with a first embodiment of the invention, a Dual Feedback-Low power regulation circuit for a three-stage power amplifier integrated circuit is provided. In accordance with a second embodiment of the invention, a current source feedback circuit having low RF output signal power regulation for a three-stage power amplifier integrated circuit is provided.

Abstract: A phase signal is modulated in quadrature modulation by a quadrature modulator, and the frequency of this modulated phase signal is converted into carrier frequency by a frequency converter. An amplitude signal extracted from the modulating signal is delayed by a delay circuit, and an output gain signal designating the output average power gain is supplied to the output signal of the delay circuit. Synchronization of this frequency modulated phase signal and the amplitude signal delayed and added to the output gain signal allows to obtain an RF signal with little out of band undesired component even if the modulating signal contains amplitude variation. Therefore, the RF signal with little out of band undesired component is output even if the modulating signal contains amplitude variation.

Abstract: The number of components of a high frequency power amplifier is reduced. A bias resistance ratio is adjusted in accordance with a change in the threshold voltage Vth of a transistor. A high frequency power amplifier has a plurality of amplifying systems. Each of these systems has an input terminal to which a signal to be amplified is supplied, an output terminal, a bias terminal, a plurality of amplifying stages which are sequentially cascaded between the input and output terminals, and a bias circuit connected to the bias terminal and each of the amplifying stages to apply a bias potential to the amplifying stage. The amplifying stage includes a control terminal for receiving an input signal and the bias potential supplied to the stage and a first terminal for transmitting an output signal of the stage.

Abstract: By extracting a portion of RF signals from an input side of a multistage RF amplifier with a detector, and converting extracted signals into envelope signals, low-frequency second-harmonic distortion components are efficiently extracted. Then, the extracted low-frequency second-harmonic distortion components are amplified with a low-frequency amplifier, and phase adjusted with a phase shifter, after which they are injected into a gate or base bias of the final stage of the multistage RF amplifier. As a result, the low-frequency second-harmonic distortion components are converted into third-harmonic distortion due to the non-linearity of transistors, and the third-harmonic distortion thus obtained cancels out the third-harmonic distortion originally present in the multistage RF amplifier.

Abstract: A biasing circuit for biasing a device (e.g., a GaAs field effect transistor) used for amplifying a radio frequency (RF) signal, the biasing circuit including an active element in series with a resistor, the active element providing a relatively low impedance over a bandwidth comparable to an amplitude modulation bandwidth of the RF signal, such that a DC bias voltage applied at the active element has a fixed DC voltage at the resistor input, i.e., without any memory effect, thereby allowing for improved predistortion compensation of non-linear voltage of the RF signal.

Abstract: The present invention provides a high frequency amplifier using a power supply voltage regulate circuit for the purpose of compensating for variations in power supply voltage. The high frequency amplifier comprises three-stage power amplifiers which amplify an input signal and output the amplified signal, a bias circuit which supplies bias voltages for controlling these power amplifiers, a regulate circuit which compensates for variations in noise or gain with respect to the variations in the power supply voltage for driving the power amplifiers, etc. The regulate circuit holds constant an output voltage Vddc with respect to variations in power supply voltage Vdd and outputs the constant-held output voltage Vddc as a power supply voltage for the power amplifiers.