Abstract: There is provided a CMOS integrated circuit capable of avoiding deterioration of NF characteristic and achieving a high degree of linearity in the case in which an LNA circuit is formed on an SOI substrate and an LAN circuit is formed in a bulk CMOS process. The CMOS integrated circuit includes a field effect transistor having a gate electrode connected to a signal input terminal, a drain electrode connected to a power terminal, and a source electrode connected to a ground terminal, wherein the field effect transistor is formed on the SOI substrate and a connection between a body potential and a potential lower than a source potential are formed by a resistor element. The deterioration of NF characteristic can be avoided and a high degree of linearity can be achieved by using this CMOS integrated circuit.

Abstract: Disclosed are a sense amplifier and a memory circuit that incorporates it. The amplifier comprises cross-coupled inverters, each with a pull-down transistor and a pull-up transistor connected in series. One inverter has a voltage-controlled switch controlling the electrical connection between drain nodes of the transistors. During a read operation, the pull-up transistor drain node is pre-charged high and the pull-down transistor drain node receives an input signal. The switch is tripped, thereby making the electrical connection only when the voltage at the pull-down transistor drain node is less than the switch's trip voltage. In this case, the sense node discharges to the same level as the input signal. Otherwise, the switch prevents the electrical connection and the sense node remains high. The trip voltage depends on a reference voltage, which can be variable, thereby allowing the sensitivity of the sense amplifier to be selectively adjusted. Also disclosed are associated methods.

Abstract: An amplifier system comprises a cascode common-source (CS) amplifier including a plurality of transistors connected in a common-source configuration. A stress reducing circuit is connected to at least one of the plurality of transistors to equalize a voltage drop across the plurality of transistors. The stress reducing circuit includes a first transistor including a control terminal, a first terminal and a second terminal. The second terminal of the first transistor is connected to a first terminal of a first one of the plurality of transistors. A capacitance has a first terminal connected to the control terminal of the first transistor and a second terminal connected to a control terminal of a second one of the plurality of transistors.

Abstract: A positive and negative voltage input operational amplifier includes a positive operational amplifier and a negative operational amplifier. Each of the positive operational amplifier and the negative operational amplifier has a reduced layout area and a lowered static current, so that the power consumption is effectively reduced.

Abstract: System and method for compensating for changes in an output impedance of a power amplifier uses an impedance compensating circuit with an impedance inverter coupled to the power amplifier. The impedance inverter of the impedance compensating circuit is configured such that an output impedance of the impedance inverter is proportional to the inverse of the output impedance of the power amplifier to compensate for changes in the output impedance of the power amplifier.

Abstract: To suppress the occurrence of distortion. There are included an initial-stage amplifier circuit PREA that receives an input signal IN, a first source-grounded transistor Tr1 that receives an output signal of the initial-stage amplifier circuit PREA at the gate, a second gate-grounded transistor Tr2 the source of which is coupled to the drain of the first transistor Tr1, which sends out an output signal OUT from the drain and at the same time, to the drain of which, a power source is supplied, and a first impedance circuit Z1 interposed between a power source end of the initial-stage amplifier circuit PREA and the source of the second transistor Tr2. The first impedance circuit Z1 is a circuit configured so as to cause a direct current to pass and at the same time, to have an impedance equal to or higher than a predetermined impedance in a predetermined frequency band.

Abstract: An embodiment of a compound semiconductor device includes: a substrate; a compound semiconductor stacked structure formed over the substrate; and an amorphous insulating film formed between the substrate and the compound semiconductor stacked structure.

Abstract: An embodiment of a compound semiconductor device includes: a substrate; an electron channel layer and an electron supply layer formed over the substrate; a gate electrode, a source electrode and a drain electrode formed on or above the electron supply layer; and a p-type semiconductor layer formed between the electron supply layer and the gate electrode. The p-type semiconductor layer contains, as a p-type impurity, an element same as that being contained in at least either of the electron channel layer and the electron supply layer.

Abstract: According to one embodiment, a high-frequency amplifier is provided with a field effect transistor for performing amplification, and a stabilizing circuit. The field effect transistor has a source which is configured to be grounded. The stabilizing circuit is connected to a gate of the field effect transistor. The stabilizing circuit has impedance which changes so as to increase as the voltage of a drain of the field effect transistor increases.

Abstract: Provided are an amplification circuit capable of amplifying an input signal having a changing duty ratio with high efficiency, and a transmission device and a communication device using the amplification circuit. The amplification circuit includes: a transistor circuit (10) having a pulse wave first signal having a changing duty ratio input, and a second signal obtained by amplifying the pulse wave first signal output; and a matching circuit (20) having the second signal input and a third signal having a fundamental frequency of the pulse wave first signal output. An impedance of the matching circuit (20) as seen from the transistor circuit side changes in accordance with the duty ratio of the pulse wave first signal. The transmission device and the communication device each use the amplification circuit.

Abstract: A transimpedance method and apparatus are provided. In one implementation an apparatus includes a common-gate amplifier for receiving a first current from a first circuit node and outputting a second current to a second circuit node, and a load circuit coupled to the second circuit node, the load circuit comprising a diode-connected MOS (metal-oxide semiconductor field effect transistor), wherein a gate terminal of the MOS is coupled to a drain terminal of the MOS via a resistor. In one embodiment, a current-mode input is injected to the first circuit node and the apparatus further comprises a biasing circuit for outputting a substantially constant current to the first circuit node.

Abstract: Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths.

Abstract: Disclosed is a Class-AB/B amplifier comprising a first output stage including a first plurality of amplification devices and a second output stage including a second plurality of amplification devices. According to one embodiment, the first output stage operates when the Class-AB/B amplifier is in a quiescent state and the second output stage operates when the Class-AB/B amplifier is in an active state. The Class-AB/B amplifier also comprises a level shifting circuit that adjusts a control voltage of the second output stage, where the level shifting circuit is adapted to activate the second output stage when the Class-AB/B amplifier enters the active state. Embodiments of the Class-AB/B amplifier may include a level shifting circuit that implements either a fixed or signal-dependent level shift, and a quiescent control circuit that substantially eliminates any systematic offset arising from the active feedback circuit inside the replica bias circuit.

Abstract: There is provided a complementary metal oxide semiconductor (CMOS) power amplifier including: a load unit connected between an operating voltage supply terminal and an output terminal; an amplifying unit formed as a cascode structure between the load unit and a ground, amplifying a power of an input signal input through an input terminal and outputting the amplified signal through an output terminal; and a threshold voltage control unit varying a threshold voltage of the amplifying unit according to a magnitude of the input signal input through the input terminal.

Abstract: One embodiment of the present invention relates to a power amplifier comprising a plurality of amplifying elements connected in a serial-parallel matrix configuration, containing parallel columns having amplifying elements connected in series. The parallel columns are connected to a common output path coupled to a supply voltage source configured to provide an equal supply voltage to each of the columns. One or more input signals (e.g., RF input signals) are connected to the power amplifier by way of input terminals on a first row of amplifying elements. The remaining amplifying elements have control terminals that are connected to independent control signals, which allow each amplifying element to be operated independent of the other amplifying elements in the matrix. This selective operation of amplifying elements allows for improved efficiency over a wide range of power amplifier output powers.

Abstract: An amplifier circuit includes an amplifier and a noise suppression block. The amplifier is arranged for receiving an input signal at an input port and generating an output signal at an output port according to the input signal. The noise suppression block is coupled between the input port and the output port of the amplifier, and arranged for receiving the input signal and the output signal and applying noise suppression to the output signal generated from the amplifier according to the received input signal and the received output signal.

Abstract: A pre-driver for an amplifier comprising a load network in which the following elements are connected in the following order: a resistor-an inductor-a capacitor. Also described are a power amplifier comprising such a pre-driver, a method of fabricating a pre-driver for an amplifier, and a method of performing power amplification.

Abstract: A radio frequency (RF) power transistor circuit includes a power transistor and a decoupling circuit. The power transistor has a control electrode coupled to an input terminal for receiving an RF input signal, a first current electrode for providing an RF output signal at an output terminal, and a second current electrode coupled to a power supply voltage terminal. The decoupling circuit includes a first inductive element, a first resistor, and a first capacitor coupled together in series between the control electrode of the first power transistor and the power supply voltage terminal. The first decoupling circuit is for dampening a resonance at a frequency lower than an RF frequency.

Abstract: Illustrative embodiments of a power amplifier are disclosed which include a plurality of amplifier cells, each having an input and an output. The plurality of amplifier cells are formed on a semiconductor substrate such that the outputs of the plurality of amplifier cells are electrically coupled in series. Each of the plurality of amplifier cells may comprise a first transistor that is electrically insulated from the semiconductor substrate and a first feedback resistor configured to dynamically bias the first transistor.

Abstract: An error amplifier and a LED circuit comprising the same are provided. The LED circuit comprises an inductor, a group of LEDs and a power MOS connected to the inductor, an error amplifier and a pulse width modulator controlling the gate of the power MOS according to an error amplifier output. The error amplifier comprises a differential input stage, an output stage having a first NMOS, a first PMOS, a second NMOS, a second PMOS and a control switch module. During a first operation mode, the control switch module connects the first NMOS and PMOS and connects the second NMOS and PMOS, and during a second operation mode, control switch module disables the second NMOS and PMOS.

Abstract: A high frequency amplifier circuit includes a first transistor that has a first terminal, a second terminal and a control terminal, the first terminal being grounded, a second transistor that has a first terminal, a second terminal and a control terminal, the control terminal of the second transistor being coupled to the second terminal of the first transistor, the first terminal of the second transistor being coupled to only the second terminal of the first transistor with respect to high frequency wave, the second terminal of the second transistor being coupled to a direct-current power supply, and a first resistor of which first terminal is coupled to a node between the second terminal of the first transistor and the control terminal of the second transistor, and of which second terminal is coupled to the first terminal of the second transistor.

Abstract: A CMOS power amplifier includes: a first MOS transistor connected between a first power terminal and a first output stage and having a gate connected to an input stage; a second MOS transistor connected between the first output stage and a ground and having a gate connected to the input stage; a switching circuit unit connecting or separating a feedback line between the input stage and the first output stage to select a linear amplifying operation or a non-linear amplifying operation; and a resistor formed at the feedback line between the input stage and the first output stage to determine a linear amplification gain when the feedback line is turned on.

Abstract: Signaling systems, preamplifiers, memory devices and methods are disclosed, such as a signaling system that includes a transmitter configured to receive a first digital signal. The transmitter provides a transmitted signal corresponding to the digital signal to a signal path. A receiver system coupled to the signal line includes a preamplifier coupled to receive the transmitted signal from the signal path. The preamplifier includes a common-gate amplifying transistor that is configured to provide an amplified signal. The receiver system also includes a receiver coupled to receive the amplified signal from the preamplifier. The receiver is configured to provide a second digital signal corresponding to the amplified signal received by the receiver. Such a signaling system may be used in a memory device or in any other electronic circuit.

Abstract: There is presented a high bandwidth circuit for high-speed transceivers. The circuit may comprise an amplifier combining capacitor splitting, inductance tree structures, and various bandwidth extension techniques such as shunt peaking, series peaking, and T-coil peaking to support data rates of 45 Gbs/s and above while reducing data jitter. The inductance elements of the inductance tree structures may also comprise high impedance transmission lines, simplifying implementation. Additionally, the readily identifiable metal structures of inductors and t-coils, the equal partitioning of the load capacitors, and the symmetrical inductance tree structures may simplify transceiver implementation for, but not limited to, a clock data recovery circuit.

Abstract: Disclosed herein is a transformer including: a primary coil formed of a first conductor having a predetermined length and including a first end and second end for receiving a signal, wherein the first conductor is formed as a first loop; and a secondary coil that is coupled to the primary coil in an electromagnetic coupling, and is formed of a second conductor having a predetermined length and including a first end and a second end for outputting a signal, wherein the second conductor is formed as a second loop, wherein the primary coil and the secondary coil are stacked while crossing each other. Accordingly, power transformer efficiency may be increased.

Abstract: A semiconductor power amplifier of an embodiment includes: a plurality of unit FETs disposed in parallel in a direction of a substantially straight line connecting source electrodes of the unit FETs; a first via hole which connects the two source electrodes positioned between adjacent ones of the unit FETs in common and an RF ground electrode; and a second via hole which connects the source electrode on a side having no adjacent unit FET and the RF ground electrode. Each unit FET includes: a gate electrode which connects gate finger electrodes and leads out the gate finger electrodes; a drain electrode which connects drain finger electrodes disposed facing the gate finger electrodes and leads out the drain finger electrodes ; and two source electrodes which connects source finger electrodes disposed facing the gate finger electrodes and lead out the source finger electrodes to opposing sides in a widthwise direction thereof.

Abstract: An amplifier for providing improved third-order intermodulation (IM3) cancelation. The amplifier may comprise a main branch for amplifying input signals and an auxiliary branch for generating IM3 signals that are equal to corresponding IM3 components resulting from amplifying input signals via the main branch, with both of the main and the auxiliary branches being configured as differential circuits. The differential implementation may result in the auxiliary branch generating IM3 distortion signals with minimal or no non-IM3 signals. Each of the main and the auxiliary branches may comprise at least two transistor elements. Separate bias current sources may be applied to each of the main and the auxiliary branches. Operation of the auxiliary branch may be controlled by adjusting one or both of the bias current sources. Outputs of the main and the auxiliary branches may be cross-coupled, to invert a sign of IM3 distortion signals generated via the auxiliary branch.

Abstract: An amplifier including an amplifier transistor, and a switch transistor, wherein the amplifier is configured to be switched on and off by controlling bias voltages of the transistors.

Abstract: A multiple transistor differential amplifier is implemented on a segment of a single graphene nanoribbon. Differential amplifier field effect transistors are formed on the graphene nanoribbon from a first group of electrical conductors in contact with the graphene nanoribbon and a second group of electrical conductors insulated from, but exerting electric fields on, the graphene nanoribbon thereby forming the gates of the field effect transistors. A transistor in one portion of the graphene nanoribbon and a transistor in another portion of the graphene nanoribbon are responsive to respective incoming electrical signals. A current source, also formed on the graphene nanoribbon, is connected with the differential amplifier, and the current source and the differential amplifier operating together generate an outgoing signal responsive to the incoming electrical signal. In an example application, the resulting circuit can be used to interface with electrical signals of nanoscale sensors and actuators.

Abstract: There is provided a multi-mode power amplifier operable in a low power mode having a preset power range and in a high power mode having a power range higher than the power range of the low power mode. The multi-mode power amplifier includes: a high power amplifying unit including at least one cascode amplifier to amplify an input signal to a high power level having a preset power range; a low power amplifying unit sharing a common source node of the at least one cascode amplifier to amplify the input signal to a low power level having a power range lower than the high power level; and a coupling unit coupling a transfer path of a signal output from the high power amplifying unit and a transfer path of a signal output from the low power amplifying unit to each other.

Abstract: A semiconductor device for transmitting-signal amplification which has a fine resolution, a high dynamic range, a small occupied area, and low power consumption, is realized. An input signal amplitude is reduced every one half by a ladder network, and a transconductance amplifier stage is arranged corresponding to each node of the ladder network. An output of the transconductance amplifier stage is coupled to an output signal line in common. According to a control word WC<21:0>, the transconductance amplifier stage is enabled selectively, and the output current which appears in the output signal line is added.

Abstract: A configurable low noise amplifier circuit which is configurable between a first topology in which the low noise amplifier circuit includes a degeneration inductance stage whereby the low noise amplifier circuit operates as an inductively degenerated low noise amplifier, and a second topology in which the low noise amplifier circuit includes a common-gate low noise amplifier stage whereby the low noise amplifier circuit operates as a common-gate low noise amplifier. The second topology includes one or more internal input impedance matching components and the first topology does not include the one or more internal input impedance matching components.

Abstract: An amplifier (22) containing an arrangement of capacitive elements (26, 28) in place of a source degeneration inductor arrangement to set the real part of the amplifier's input impedance.

Abstract: A power amplifier according to the embodiments includes: a silicon substrate; an input terminal configured to receive an input of a RF signal; a power dividing unit configured to divide the RF signal into a first signal and a second signal; a phase modulating unit configured to modulate a phase of the second signal; an N well formed in the silicon substrate; a P well formed in the N well and configured to receive an input of the second signal of a modulated phase; a gate insulating film formed on the P well; a gate electrode formed on the gate insulating film and configured to receive an input of the first signal; source and drain electrodes formed on both sides of the gate electrode in the silicon substrate; and an output terminal configured to output a RF signal obtained from the drain electrode.

Abstract: A high electron mobility transistor (HEMT) includes a substrate, a heterojunction on the substrate including a first layer having a Group III-nitride semiconductor material interfaced to a second layer having a doped Group III-nitride semiconductor material. A gate electrode is on a surface of the heterojunction, and a source and a drain are on opposite sides of said gate electrode. A patterned field shaping (FS) layer formed from a wide band-gap semiconductor material is over the heterojunction on at least a portion between the gate electrode and the drain.

Abstract: Amplifiers with improved efficiency and output power are described. In an exemplary design, an apparatus includes an amplifier having at least three transistors and at least two capacitors. The at least three transistors are coupled in a stack and receive and amplify an input signal and provide an output signal. The at least two capacitors include at least one capacitor coupled between the drain and source of an associated transistor for each of at least two transistors in the stack, e.g., at least one capacitor for each transistor in the stack except for the bottommost transistor in the stack. The at least two capacitors recycle energy from gate-to-source parasitic capacitors of the at least two transistors to the output signal, which improves efficiency and output power of the amplifier.

Abstract: An amplifier having an operating frequency includes: an input port and an output port; three gain elements, each having an input terminal and an output terminal; an input matching network; and an output matching network. The input matching network includes: a first microstrip line which is connected to the input port and is an inductor at the operating frequency; a second microstrip line extending between the input terminals of the three gain elements; and a first split shunt capacitor connecting the first microstrip line to the second microstrip line. The output matching network includes: a third microstrip line which is connected to the output port and is an inductor at the operating frequency; a fourth microstrip line extending between the output terminals of the three gain elements; and a second split shunt capacitor connecting the third microstrip line to the fourth microstrip line.

Abstract: According to an embodiment, a power amplifier includes: an MMIC substrate; a high frequency probe pad disposed on the MMIC substrate; and a metal plate disposed on the MMIC substrate so as to adjoin to the high frequency probe pad, and connected to an MMIC external circuit via a bonding wire.

Abstract: Provided is a power amplifier including: a depletion mode high electron mobility transistor (D-mode HEMT) configured to amplify a signal inputted to a gate terminal and output the amplified signal through a drain terminal; an input matching circuit configured to serially ground the gate terminal; and a DC bias circuit connected between the drain terminal and a ground. Through the foregoing configuration, the HEMT may be biased only by a single DC bias circuit without any biasing means to provide a negative voltage. Also, superior matching characteristic may be provided in various operation frequency bands through a shunt inductor and a choke inductor.

Abstract: An operational amplifier includes an input stage, an output stage, an output enable switch, an internal capacitor, a coupling effect reduction circuit. The input stage provides an intermediate signal according to an input signal. The output stage, including an output node, provides a driving signal according to the intermediate signal. The output enable switch is turned on during an output enable period, having a start time point, to drive a load with the driving signal. The internal capacitor is coupled between the input stage and the output stage. The coupling effect reduction circuit, coupled between the internal capacitor and the output node or between the internal capacitor and the input stage, is turned off during an operational period starting from the start time point, to prevent coupling charge generated when the output enable switch is turned on from affecting operational voltage levels of the input stage.

Abstract: An embodiment of an LNA includes a voltage input, a voltage output, an input transistor connected as a source follower with a current source at the drain and source nodes of the input transistor, an input resistor connected between the source follower source node and signal ground, a gain boosting transistor with the gate connected to the input transistor drain node, wherein the source node is connected to ground and the drain node is connected through a load resistor to the input transistor source node. Such an LNA provides substantial improvement in power efficiency by adapting an output stage of the LNA to reuse the supply current of the input transistors to the LNA through a load resistor.

Abstract: A power amplifier includes an input terminal, an input matching circuit connected to the input terminal, an amplifying transistor having a gate connected to the input matching circuit, an output matching circuit connected to the drain of the amplifying transistor, an output terminal connected to the output matching circuit, and an inverting differentiator circuit for either inverting and then differentiating, or differentiating and then inverting, a signal from the input terminal. The output of the inverting differentiator circuit is connected to the gate.

Abstract: A method and apparatus is provided for use in power amplifiers for reducing the peak voltage that transistors are subjected to. A power amplifier is provided with first and second switching devices and an inductor connected between the switching devices. The switching devices are driven such that the switching devices are turned on and off during the same time intervals.

Abstract: An amplifier circuit for actuating a light diode is provided. The amplifier circuit may have a small output impedance of approximately 3 Ohms, a large bandwidth having a lower threshold frequency of 200 kHz and an upper threshold frequency of 5 MHz, for example, and an amplitude of the output current of several 100 mA, for example. The amplifier circuit may have an entry stage for actuating a driver circuit that actuates the light diode by means of a direct current supply.

Abstract: A power amplifier, which includes n+1 amplifying units coupled in parallel, where n is an integer greater than or equal to 0, third input ends VR(i) of the n+1 amplifying units are coupled to a power input VL, output ends D(i) of the n+1 amplifying units are coupled to a power input VH, and an output power of the power amplifier is in an increasing function relationship with a capacitance value obtained through accumulation of energy returning capacitors xC of the n+1 amplifying units. The power amplifier changes circuit impedance in a manner of controlling the parallel capacitance value by a switching digital signal, thereby controlling a magnitude of a returned power value and forming different output powers.

Abstract: A plurality of inductors are connected in series between a load resistor and a first transistor, and a plurality of second transistors provided in parallel are connected to the plurality of inductors.

Abstract: A gate electrode is formed so as to embed an electrode material in a recess for an electrode, which has been formed in a structure of stacked compound semiconductors, through a gate insulation film, and also a field plate electrode that comes in Schottky contact with the structure of the stacked compound semiconductors is formed by embedding an electrode material in a recess for an electrode, which has been formed in the structure of the stacked compound semiconductors so that the field plate electrode directly comes in contact with the structure of the stacked compound semiconductors at least on the bottom face of the recess for the electrode.

Abstract: According to an embodiment, a class-AB power amplifier includes an amplifying element whose power supply voltage is expressed as Vdc and whose maximum current is expressed as Imax, a conduction angle ?o of the amplifying element being more than ?(rad) and less than 2·?r(rad), and load impedance of a fundamental wave being expressed as Z1=R1+j·X1 and load impedance of a 2nd harmonic being expressed as Z2=R2+j·X2 which are observed from a dependent current source of an equivalent circuit of the amplifying element, wherein a relationship between variables X1 and R1 is set to ?R1<=X1<=R1, variable R1 is set to R1=Vdc/Imax·?·{1?cos(?o/2)}/{?o/2?sin(?o)/2}, and variable X2/X1 is set to X2/X1=?{?o/2?sin(?o)/2}/{sin(?o/2)?sin(1.5·?o)/3}, or each of the variables is set thereto so as to become equal substantially.

Abstract: There is embodied a high-reliability high-voltage resistance compound semiconductor device capable of improving the speed of device operation, being high in avalanche resistance, being resistant to surges, eliminating the need to connect any external diodes when applied to, for example, an inverter circuit, and achieving stable operation even if holes are produced, in addition to alleviating the concentration of electric fields on a gate electrode and thereby realizing a further improvement in voltage resistance. A gate electrode is formed so as to fill an electrode recess formed in a structure of stacked compound semiconductors with an electrode material through a gate insulation film, and a field plate recess formed in the structure of stacked compound semiconductors is filled with a p-type semiconductor, thereby forming a field plate the p-type semiconductor layer of which has contact with the structure of stacked compound semiconductors.

Abstract: An amplifier circuit includes: a first transformer in which a first inductor and a second inductor are magnetically coupled; a first field-effect transistor in which a gate is connected to a first input node via the first inductor, a drain is connected to a drain bias potential node via the second inductor, and a source is connected to a reference potential node; and a first output node connected to the drain of the first field-effect transistor.