Abstract: A level shift regulator circuit comprises a level shift transistor (Mls) and an output transistor (Mreg) being arranged in series to the level shift transistor (Mls) in an output path (OP). The circuit comprises a feedback path (FP) being arranged between an input node (IN) of the output path (OP) and a gate connection of the output transistor (Mreg). A current splitter (CS) is provided to split a current of a current source (IS0) coupled to the input node (IN) to reduce the loop gain. A current mirror (CM) is arranged in series to the current splitter (CS) to reduce the signal current provided by the current splitter (CS) to the gate connection of the output transistor (Mreg) to further reduce the gain and to improve stability of the circuit. A first and second filter (F1, F2) may optionally be provided to improve the phase response.

Abstract: Apparatus and methods for a delay circuit are provided. In an example, a delay circuit can include a resistor configured to receive a compensation current, a capacitor configured to receive a charge current based on the compensation current, a first compensation circuit configured to provide a control signal, and a charge-current coupling circuit. The first compensation circuit can include an inverter circuit configured to track an inverter threshold voltage across process, voltage and temperature variations, wherein an output of the inverter circuit is directly coupled to an input of the inverter circuit, and an amplifier configured to receive the output of the inverter circuit an provide the control signal. The charge-current coupling circuit can be configured to receive the control signal and to provide the compensation current and the charge current.

Abstract: Aspects and examples described herein provide a radio-frequency switching circuit, switching device, and related methods. In one example, a radio-frequency switching device includes an input path configured to receive a radio-frequency signal, a plurality of output paths each configured to provide the radio-frequency signal, and a plurality of radio-frequency sub-networks each coupled to the input path and configured to direct the radio-frequency signal, each of the plurality of sub-networks including at least a first radio-frequency circuit having a first series of directly biased transistors, a second radio-frequency circuit having a second series of directly biased transistors, and a direct current blocking network interposed between the first radio-frequency circuit and the second radio-frequency circuit, each output path of the plurality corresponding to at least one of the plurality of radio-frequency sub-networks.

Abstract: A driver circuit includes a first termination resistor and a distributed amplifier comprising a plurality of pairs of input transistors and comprising inductors coupled between each pair of input transistors. The driver circuit also includes a distributed current-mode level shifter coupled to the first termination resistor. The distributed current-mode level shifter includes a first plurality of inductors coupled in series between the first termination resistor and the distributed amplifier and a first plurality of capacitive devices. Each capacitive device is coupled to a power supply node and to a node interconnecting two of the series-coupled inductors.

Abstract: A power amplifier includes a transistor operating in a range of frequencies from a lower operating frequency to a higher operating frequency to provide a relatively linear gain between the lower operating frequency and the higher operating frequency, an input transmission line circuit coupled to a gate terminal of the transistor, and an output transmission line circuit coupled to a drain terminal of the transistor. The input transmission line includes an inductor-capacitor (LC) circuit that resonates at a first resonant frequency equaled to or higher than the higher operating frequency. The output transmission line includes an inductor-capacitor-inductor (LCL) circuit and a capacitor-inductor-capacitor (CLC) circuit. The LCL circuit resonates at a second resonant frequency equaled to or lower than the lower operating frequency. The CLC circuit resonates at a third resonant frequency equaled to or higher than the higher operating frequency.

Abstract: Circuits, methods and devices are disclosed, related to fast turn-on of radio-frequency amplifiers. In some embodiments, a method for amplifying a radio-frequency signal includes providing an amplification path implemented to amplify an radio-frequency signal, where the amplification path includes a switch and an amplifier. In some embodiments, each of the switch and the amplifier are configured to be ON or OFF to thereby enable or disable the amplification path, respectively. In some embodiments, the method includes providing a compensation circuit coupled to the amplifier, where the compensation circuit is configured to compensate for a slow transition of the amplifier between its ON and OFF states resulting from a signal applied to the switch.

Abstract: A transistor stack can include a combination of floating and body tied devices. Improved performance of the RF amplifier can be obtained by using a single body tied device as the input transistor of the stack, or as the output transistor of the stack, while other transistors of the stack are floating transistors. Transient response of the RF amplifier can be improved by using all body tied devices in the stack.

Abstract: The present disclosure provides a trans-impedance amplifier, comprising: an inverting amplifier circuit, having an input end and an output end. The input end is coupled to an optical diode and is used for accessing an input voltage signal, and the output end is used for outputting an amplified voltage signal. The inverting amplifier circuit comprises at least three sequentially-connected amplifier units. Each of the amplifier units comprises two mutually-coupled N-type transistors, wherein one N-type transistor is used for receiving an input voltage, and the other N-type transistor is used for receiving a DC voltage signal. A common connection end of the two N-type transistors is used for outputting an amplified voltage signal, and the N-type transistor used for receiving the DC voltage signal adopts a native NFET. The trans-impedance amplifier further comprises a feedback resistor coupled to the input end and the output end of the inverting amplifier circuit.

Abstract: A novel microphone incorporates a phantom-powered JFET circuit for audio application. In one embodiment of the invention, a novel phantom-powered JFET preamplifier gain circuit can minimize undesirable sound distortions and reduce the cost of producing a conventional preamplifier gain circuit. Moreover, in one embodiment of the invention, one or more novel rounded-edge magnets may be placed close to a ribbon of a ribbon microphone, wherein the one or more novel rounded-edge magnets reduce or minimize reflected sound wave interferences with the vibration of the ribbon during an operation of the ribbon microphone. Furthermore, in one embodiment of the invention, a novel backwave chamber operatively connected to a backside of the ribbon can minimize acoustic pressure, anomalies in frequency responses, and undesirable phase cancellation and doubling effects.

Abstract: Power amplifier circuitry includes an amplifier stage, a non-linear compensation network, and non-linear compensation control circuitry. The amplifier stage includes an input and an output, and is configured to receive an input signal at the input and provide an amplified output signal at the output. The non-linear compensation network is coupled between the input and the output of the amplifier stage. The non-linear compensation control circuitry is coupled to the non-linear compensation network and one or more of the input and the output of the amplifier stage. The non-linear compensation control circuitry is configured to adjust a capacitance of the non-linear compensation network to cancel a parasitic capacitance associated with the amplifier stage and thus reduce AM-PM distortion.

Abstract: A differential amplifier comprises a first differential circuitry structure including a first part comprising at least one branch of transistors and a second part comprising at least one branch of transistors, and a second circuitry structure. The second circuitry structure has a first non-linear device and a second non-linear device. The non-linear devices each comprise a transistor having a control node connected to a differential output terminals of the differential amplifier. A common center node of the non-linear devices is connected to a control node of one of the transistors of each branch of the first part having a differential output terminal. Amplifier applications, communication devices and network nodes are also disclosed.

Abstract: Embodiments of the disclosure relate to calibrating a power amplifier. The power amplifier calibration circuit is configured to provide a plurality of bias signal combinations each including a respective first bias signal and a respective second bias signal to the power amplifier. Power amplifier performance parameters for each of the bias signal combinations can be measured and provided to a control circuit in the power amplifier calibration circuit. The control circuit is configured to rank the measured power amplifier performance parameters based on predefined ranking criteria and determines a selected bias signal combination that can optimize the power amplifier performance parameters of the power amplifier. As such, it is possible to calibrate the power amplifier to operate at a balanced performance level, thus helping to improve radio frequency (RF) coverage and performance of the remote unit in a wireless distribution system (WDS).

Abstract: A system may include a radio frequency (RF) amplifier device that includes an input impedance matching network and first and second baseband decoupling circuits, which may remove intermodulation distortion products from signal energy input to the RF amplifier device at baseband frequencies. The input impedance matching network may act as a band-pass or low-pass filter. A gate bias voltage may be applied to the gate of a transistor in the RF amplifier device through one of the baseband decoupling circuits or, alternatively, at an input node of the RF amplifier device.

Abstract: A power amplifier includes a main amplifier, an auxiliary amplifier, and a control circuit. The main amplifier is configured to amplify input power, and the auxiliary amplifier is configured to amplify the input power when the input power exceeds a certain level. The control circuit, which is provided between a source of the main amplifier and a ground, is configured to control a source potential of the main amplifier so as to increase the source potential when the input power reaches at least a certain value.

Abstract: This disclosure relates generally to continuous time linear equalization. In an example of a continuous time linear equalizer, a variable gain circuit includes transistors having gate nodes respectively as a first and a second input node. A first transimpedance circuit is connected between the first input node and a first output node. A second transimpedance circuit is connected between the second input node and a second output node. A source node of each of the first transistor and the second transistor are commonly connected to one another. In the same or another equalizer, output nodes of a first frequency peaking circuit are connected to input nodes of a second frequency peaking circuit. In such a same or another equalizer, an RC feedback circuit has tap-off nodes and summing nodes respectively connected at the output nodes of the first frequency peaking circuit.

Abstract: Provided is a power amplification module that supports a plurality of communication systems. The power amplification module includes: two power amplifiers that can be selectively connected in parallel with each other; a switch that, in accordance with one communication system selected from among the plurality of communication systems, selects one power amplifier that is to operate by itself from among the two power amplifiers or selects the two power amplifiers and connects the two power amplifiers in parallel with each other; and a phase correction circuit that, when the two power amplifiers are both selected, corrects a phase difference by being selectively connected between the outputs of the two selected power amplifiers such that a phase difference is not generated between the output signals of the two selected power amplifiers.

Abstract: A multiple-stage amplifier includes a driver stage die and a final stage die. The final stage die includes a III-V semiconductor substrate (e.g., a GaN substrate) and a first transistor. The driver stage die includes another type of semiconductor substrate (e.g., a silicon substrate), a second transistor, and one or more secondary circuits that are electrically coupled to a control terminal of the first transistor. A connection (e.g., a wirebond array or other DC-coupled connection) is electrically coupled between an RF signal output terminal of the driver stage die and an RF signal input terminal of the final stage die. The secondary circuit(s) of the driver stage die include a final stage bias circuit and/or a final stage harmonic control circuit, which are electrically connected to the final stage die through various connections.

Abstract: A power amplifier circuit comprising a transistor for receiving a signal to be amplified at an input and for outputting an amplified signal at an output; a modulated power supply connected to the transistor output; and a resistive element connected at the transistor output such that a low impedance is maintained at the transistor output across a range of operational frequencies.

Abstract: The present disclosure provides a trans-impedance amplifier, comprising: an equivalent secondary amplifier module, having an input end and an output end, wherein the input end is coupled to an optical diode and used for accessing an input voltage signal, and the output end is used for outputting a secondarily amplified first voltage signal; an inverting amplifier unit, coupled to the output end of the equivalent secondary amplifier module and used for accessing the first voltage signal and outputting an inverting amplified voltage signal, the inverting amplifier unit comprising a third N-type transistor and a fourth N-type transistor coupled to the third N-type transistor; and a feedback resistor, coupled to the input end of the equivalent secondary amplifier module and an output end of the inverting amplifier unit. The feedback resistor of the trans-impedance amplifier can be not restricted by original conditions, may increase resistance, reduce input noise and improve sensitivity.

Abstract: A radio frequency (RF) power transistor circuit includes a power transistor and a decoupling circuit. The power transistor has a control electrode coupled to an input terminal for receiving an RF input signal, a first current electrode for providing an RF output signal at an output terminal, and a second current electrode coupled to a voltage reference. The decoupling circuit includes a first inductive element, a first resistor, and a first capacitor coupled together in series between the first current electrode of the power transistor and the voltage reference. The decoupling circuit is for dampening a resonance at a frequency lower than an RF frequency.

Abstract: Embodiments of the disclosure relate to calibrating a power amplifier. The power amplifier calibration circuit is configured to provide a plurality of bias signal combinations each including a respective first bias signal and a respective second bias signal to the power amplifier. Power amplifier performance parameters for each of the bias signal combinations can be measured and provided to a control circuit in the power amplifier calibration circuit. The control circuit is configured to rank the measured power amplifier performance parameters based on predefined ranking criteria and determines a selected bias signal combination that can optimize the power amplifier performance parameters of the power amplifier. As such, it is possible to calibrate the power amplifier to operate at a balanced performance level, thus helping to improve radio frequency (RF) coverage and performance of the remote unit in a wireless distribution system (WDS).

Abstract: A power integrated circuit and a method of forming includes forming a first body region of a first conductivity type in a first deep well of a second conductivity type. The power integrated circuit includes a first deep diffusion region formed under the first body region and in electrical contact with the first body region where the first deep diffusion region is formed by performing first and second ion implantations of dopants of the first conductivity type and using second implant energy greater than the first implant energy.

Abstract: According to one embodiment, there is provided a semiconductor integrated circuit including an output transistor, an error amplifier, and a control circuit. The output transistor is connected between a first node on an input terminal side and a second node on an output terminal side. The error amplifier has a non-inverting input terminal, an inverting input terminal, and an output terminal. The non-inverting input terminal is connected to a third node between the second node and a standard potential. The inverting input terminal is connected to a reference voltage. The output terminal is connected to the gate of the output transistor. The control circuit makes responsiveness of the error amplifier at startup slower than responsiveness of the error amplifier at steady operation.

Abstract: [Problem to be Solved] To provide an RF tag antenna capable of improving readability and a method of manufacturing the same, and an RF tag.

Abstract: The present disclosure relates systems and methods for providing a three-dimensional device architecture for transistor elements in a power amplifier circuit. Namely, an example system may include a plurality of high electron mobility transistors disposed on a first substrate. A first portion of the plurality of high electron mobility transistors are electrically coupled via respective first level interconnects disposed on the first substrate. The system also includes a plurality of second level interconnects disposed on a second substrate. A second portion of the plurality of high electron mobility transistors are electrically coupled via respective second level interconnects. The first substrate and the second substrate are coupled such that the plurality of high electron mobility transistors provides an amplified output signal via at least one of the first level interconnects or the second level interconnects.

Abstract: According to an embodiment, a photon detecting element includes one or more avalanche photodiodes and a circuit. The circuit is connected between cathodes of the one or more avalanche photodiodes and an external power source. The circuit is configured in which a first temperature coefficient representing variation of a setting potential with respect to temperature variation when constant-current driving is performed so that electrical potential of the cathodes becomes equal to the setting potential is substantially the same as a second temperature coefficient representing variation of breakdown voltage of the one or more avalanche photodiodes with respect to temperature variation.

Abstract: An RF transmitter with a power combiner and a differential amplifier is provided. The power combiner converts a differential output signal to a single-end output signal and transmits the single-end output signal to the antenna. The differential amplifier includes common-source input transistors, common-gate output transistors and a switch module. The common-source input transistors amplify a differential input signal and output an amplified differential signal. The common-gate output transistors, including sources electrically coupled to the common-source input transistors and drains electrically coupled to the power combiner, generate the differential output signal according to the amplified differential signal. The switch module is electrically coupled between the gates. The switch module electrically couples the gates of the common-gate output transistors if the RF transmitter is in operation and electrically isolates the gates if the RF receiver is in operation.

Abstract: Certain aspects of the present disclosure generally relate to a multi-output amplifier implemented using a capacitive attenuator. For example, the multi-output amplifier generally includes a first capacitive attenuator coupled to an input node of the multi-output amplifier. In certain aspects, the multi-output amplifier also includes a first amplification stage having an input coupled to a tap node of the first capacitive attenuator and an output coupled to a first output node of the multi-output amplifier, and a second amplification stage having an output coupled to a second output node of the multi-output amplifier. For certain aspects, the multi-output amplifier includes a second capacitive attenuator coupled to the input node of the multi-output amplifier, and the second amplification stage may have an input coupled to a tap node of the second capacitive attenuator.

Abstract: A multi-stage low-noise amplifier (LNA) device with a band pass response includes a first LNA in series with a second LNA. The device further includes multiple outputs coupled to the second LNA. Each of the outputs is capable of being active at the same time. The device further includes a high pass filter coupled between the first LNA and the second LNA.

Abstract: Amplifier circuits comprising an input transistor, a load transistor, and a feedback resistor. In one example, one embodiment is directed to an amplifier circuit comprising an input transistor, a load transistor having a control terminal and a reference terminal, and a feedback transistor. The input transistor receives an input signal, the input transistor is electrically coupled to the load transistor and the feedback transistor, the control terminal of the load transistor is electrically coupled to a bias voltage, the feedback transistor is electrically coupled to the load transistor providing negative feedback, and the reference terminal of the load transistor serves as an output of the amplifier circuit.

Abstract: A circuit includes an amplifier having an input that receives an alternating current (AC) waveform and an output that is coupled to a power source via a bias resistor. A bulk acoustic wave (BAW) resonator is coupled in parallel to the bias resistor via the power source and the amplifier output. The BAW resonator and the amplifier output forms a band pass filter to filter the AC waveform received at the amplifier input and to provide a filtered AC waveform at the amplifier output.

Abstract: A passive equalizer is provided. The passive equalizer includes a first resistive element, a first inductive element, a second resistive element, and a first variable capacitor. The first resistive element is coupled between an input node and an output node. The first inductive element and the second resistive element are coupled in series between the output node and a first voltage supply node. The first variable capacitor is coupled between the input node and a first node located between the first inductive element and the second resistive element.

Abstract: A method and a system for ultra-low-power acoustic sensor including a buffer transistor, which gate terminal is connected to a first terminal of a capacitive acoustic sensor, which drain terminal is connected via a load network to a power source and to an output terminal, and which source terminal is connected to the regulated current source, where the regulated current source is connected between the source terminal of the buffer transistor and a reference terminal, and where the reference terminal being connectable to a second terminal of the capacitive acoustic sensor.

Abstract: An amplifier arrangement comprises N amplifier stages, wherein N is an integer equal or greater than five. The amplifier arrangement comprises a first cascade of quarter wavelength transmission line segments coupled to receive a first set of amplifier stages, and at least a second cascade of quarter wavelength transmission line segments coupled to receive a second set of amplifier stages. The first cascade and second cascade are connected to a common node, for example in parallel to an output node, or in parallel to an intermediate node.

Abstract: An integrated matching circuits for a high frequency amplifier transistor having an input terminal, an output terminal and a reference terminal. The reference terminal is coupled to a reference potential. The integrated matching circuit comprises an inductive element, and a capacitive element arranged in a series arrangement with the inductive element. The series arrangement has a first terminal end connected to the input terminal or to the output terminal and a second terminal end connected to the reference terminal. The first terminal end and the second terminal end are arranged at a same lateral side of the integrated matching circuit to obtain a geometry with the first terminal end adjacent to the input terminal or to the output terminal and the second terminal end adjacent to the reference terminal.

Abstract: Amplifiers can be used for a variety of electronic-based applications. Therefore, amplifier performance is of importance. A low noise amplifier can be interfaced after an antenna or a band-select filter as a first active stage, in a receiver since its bandwidth characteristics can be closely related to a system data rate. A bandwidth enhancement technique can be leverage for low noise amplifiers by embedding a transformer between a gate and a drain terminal of a common gate transistor in a cascode topology. The embedded transformer can introduce an additional high-frequency conjugate zero pair, which can push the gain rolling-off start-up point to a higher frequency, peak the higher frequency gain, and broaden the low noise amplifier gain bandwidth.

Abstract: A semiconductor integrated circuit includes a transformer that includes a first winding and a second winding, a low-noise amplifier circuit that includes an input terminal in which at least one end of the second winding of the transformer is connected to the input terminal; and a switch that is provided between the one end and another end of the second winding of the transformer. The switch is opened and the transformer functions as an input impedance matching circuit for the low-noise amplifier circuit in a period in which a reception signal is supplied to the first winding of the transformer. On the other hand, the switch is closed and the transformer is caused to become an element including a predetermined capacitance in a period in which another circuit connected to the predetermined node operates.

Abstract: A thermal protecting device of a speaker is provided. The thermal protecting device includes an amplifier and a temperature detecting unit. An input end of the amplifier receives an audio reference signal, an output end of the amplifier provides an audio output signal to the speaker. The temperature detecting unit receives an audio input signal to provide the audio reference signal, and detects an operation temperature of the speaker to determine an amplitude of the audio reference signal. The amplitude is inversely proportional to the operation temperature.

Abstract: A transistor stack can include a combination of floating and body tied devices. Improved performance of the RF amplifier can be obtained by using a single body tied device as the input transistor of the stack, or as the output transistor of the stack, while other transistors of the stack are floating transistors. Transient response of the RF amplifier can be improved by using all body tied devices in the stack.

Abstract: An amplifier circuit (100) comprises three amplifier subcircuits (121,131,141) connected via a network of transmission lines to a common node. A control circuit is configured to control the three amplifier subcircuits (121,131,141) to operate in first, second, and third operating modes, such that a first subcircuit (121) is active in the first, second, and third modes, a second sub-circuit (141) is inactive in the first mode but active in the second and third modes, and a third subcircuit (131) is inactive in the first and second modes but active in the third. A quarter-wavelength transmission line (170) couples the output node of the second sub circuit (141) to the output node (160) of the third subcircuit (131).

Abstract: A transistor package according to one exemplary embodiment includes main transistors and a sub-transistor placed in the same package as the main transistors and having a smaller size than the main transistors. It is thereby possible to provide a transistor package with more versatility capable of forming various types of Doherty amplification circuits such as a Doherty amplification circuit with auto-biasing function and an extended Doherty amplification circuit with desired operating characteristics, an amplification circuit including the same, and a method of forming a transistor.

Abstract: An audio signal amplification device of the disclosure includes: a delta-sigma modulation part configured to resample an input digital audio signal with a quantization number smaller than a quantization number of the digital audio signal; a pulse-width modulation part configured to convert an output signal from the delta-sigma modulation part into a pulse-width modulation signal which sets a gradation of the output signal in an amplitude direction at a gradation of a pulse width; a power amplification part configured to perform power amplification on an output signal from the pulse-width modulation part; a low-pass filter configured to diminish a component higher than a predetermined cutoff frequency, in an output signal from the power amplification part, and to output the resultant signal; and a correction processing part configured to generate a correction signal for correcting the digital audio signal.

Abstract: A voltage supply unit includes a regulator unit, a current mirror, and a cascode unit. The regulator unit is configured to receive first and second voltage signals and generate a third voltage signal. The current mirror is configured to generate first and second current signals based on the third voltage signal. The cascode unit includes a first terminal configured to receive the first current signal, a second terminal configured to receive a first bias voltage signal, a third terminal configured to receive a second bias voltage signal, and a fourth terminal electrically connected to the regulator unit. An output voltage supply signal is controlled by the second current signal.

Abstract: Circuits, methods and devices are disclosed, related to fast turn-on of radio-frequency (RF) amplifiers. In some embodiments, an RF amplifier circuit includes an amplification path implemented to amplify an RF signal, where the amplification path includes a switch and an amplifier. In some embodiments, each of the switch and the amplifier are configured to be ON or OFF to thereby enable or disable the amplification path, respectively. In some embodiments, the RF amplifier circuit includes a compensation circuit coupled to the amplifier, where the compensation circuit is configured to compensate for a slow transition of the amplifier between its ON and OFF states resulting from a signal applied to the switch.

Abstract: Compression control of cascode power amplifiers. A power amplifier module can include a power amplifier including a cascode transistor pair. The cascode transistor pair can include a first transistor and a second transistor. The power amplifier module can include a current comparator configured to compare a first base current of the first transistor and a second base current of the second transistor to generate a comparison signal. The power amplifier module can include a saturation controller configured to maintain the power amplifier out of saturation based on the comparison signal.

Abstract: Embodiments relate to systems, methods and computer-readable media to enable design and creation of receiver circuitry. One embodiment is a receiver apparatus comprising a first resistor connected to a first receiver input, four N-type metal oxide semiconductor (NMOS) field effect transistors (FETs), two PMOS FETS, and a trans-impedance amplifier wherein an input terminal of the trans-impedance amplifier is connected to a drain terminal of the second NMOS FET. Additional embodiments including other circuitry, associated methods, and media comprising instructions associated with generation of circuit design files are also described.

Abstract: A radio frequency (RF) power transistor circuit includes a power transistor and a decoupling circuit. The power transistor has a control electrode coupled to an input terminal for receiving an RF input signal, a first current electrode for providing an RF output signal at an output terminal, and a second current electrode coupled to a voltage reference. The decoupling circuit includes a first inductive element, a first resistor, and a first capacitor coupled together in series between the first current electrode of the power transistor and the voltage reference. The decoupling circuit is for dampening a resonance at a frequency lower than an RF frequency.

Abstract: According to one embodiment, an amplifier includes: a transistor; a ground circuit connected to a ground terminal of the transistor; a first capacitor connected between an output terminal of the transistor and the ground circuit; a first inductor connected to the output terminal of the transistor; a second capacitor connected between the first inductor and the ground circuit; a bias circuit connected between the first inductor and the ground circuit; a first circuit connected to the output terminal of the transistor, the first circuit including a second inductor and a third capacitor connected in series to the second inductor; a fourth capacitor connected between the first circuit and a load circuit; a fifth capacitor connected between an output terminal of the first circuit and the ground circuit; and a third inductor connected between a terminal on a load circuit side of the fourth capacitor and the ground circuit.

Abstract: Power amplification system with shared common base biasing. A power amplification system can include a plurality of cascode amplifier sections. Each one of the plurality of cascode amplifier sections can include including a first transistor and a second transistor. The power amplification system can include a plurality of common emitter biasing components. Each one of the plurality of common emitter biasing components can be coupled to a base of the first transistor of a respective one of the plurality of cascode amplifier sections and can be controllable to bias the first transistor of the respective one of the plurality of cascode amplifier sections. The power amplification system can include a common base biasing component coupled to a base of the second transistor of each of the plurality of cascode amplifier sections and controllable to bias the second transistor of each of the plurality of cascode amplifier sections.

Abstract: The present disclosure provides a distributed amplifier, including: a drain transmission line; a gate transmission line; GFETs, in which sources of the graphene field-effect transistors are respectively grounded; gates of the graphene field-effect transistors respectively connected with a plurality of first shunt capacitors which are grounded; the gate transmission line is connected with a plurality of first nodes respectively between the gates of the graphene field-effect transistors and the plurality of first shunt capacitors, having a plurality of first inductors respectively between each two first nodes; drains of the graphene field-effect transistors respectively connected with a plurality of second shunt capacitors which are grounded; the drain transmission line is connected with a plurality of second nodes respectively between the drains of the graphene field-effect transistors and the plurality of second shunt capacitors, having a plurality of second inductors respectively between each two second node