Abstract: The invention relates to an amplifier circuit (10a, 10b) for a two-wire interface, comprising a first current path (1), comprising a voltage-controlled current source (T1) having a gate (GT1), which is connected to an input connection (E1) of the amplifier circuit. A second current path (2) of the amplifier circuit comprises a voltage-controlled current source (T2), which is connected in series with the second resistor (R2). The first resistor (R1) and a parallel connection of the first and second current paths (1, 2) are connected in series between an output connection (A) and a reference voltage connection (B) of the amplifier circuit. The amplifier circuit (10a, 10b) makes it possible to adjust the gain and to provide a supply voltage and a useful signal over a common conducting track (L).

Abstract: A circuit may increase input transconductance. An input stage may include a field effect transistor (FET) that has a gate, source, drain, and body terminal. An amplifier may generate an amplified version of the input voltage received that is applied to the body terminal of the FET. Application of the amplified version to the body terminal of the FET may increase the transconductance of the FET compared to what it would be in the same circuit without the amplified version being applied to the body terminal of the FET.

Abstract: An amplifier circuit includes: first and second nodes configured to receive input of differential signals; third and fourth nodes; a plurality of first inductors configured to be connected in series between the first and second nodes; a plurality of second inductors configured to be connected in series between the third and fourth nodes; a plurality of field effect transistors configured to have gates each configured to be connected between the plurality of first inductors, sources each configured to be connected to a reference potential node, and drains each configured to be connected between the plurality of second inductors; and a synthesizing unit configured to synthesize signals at the third and fourth nodes.

Abstract: A power amplifier includes: an amplifier; an input matching circuit connected to an input of the amplifier; an output matching circuit connected to an output of the amplifier; and a low-frequency processing circuit connected to the input matching circuit or the output matching circuit, wherein the low-frequency processing circuit includes a first line having a first end connected to the input matching circuit or the output matching circuit, a first shot stub connected to a second end of the first line and including a second line and a first capacitor connected in series each other, and a second short stub connected to the second end of the first line in parallel with the first short stub and including a third line and a second capacitor which are connected in series each other, the first line has a length of ?/8, the second line has a length of ?/4, and the third line has a length of ?/8 with respect to a wavelength ? of a fundamental frequency.

Abstract: A multi-stage amplifier having a first amplifier stage comprising: a pair of transistors arranged in a cascade amplifier arrangement; and an isolation circuit; and a second amplifier stage coupled to an output of the first amplifier stage; and bias regulator having a reference transistor. The cascode amplifier stage includes a pair of transistors arranged in a cascode amplifier arrangement. The bias regulator produces a reference current through the reference transistor and DC bias voltages for the control electrodes of each of the pair of transistors in the cascode amplifier arrangement and for the second stage's transistor as a function of the reference current through the reference transistor.

Abstract: A signal amplifier may include a first common gate-type amplifying unit connected to a source voltage terminal, dividing an input signal into two signals, amplifying the two divided signals, respectively, and providing a first signal and a second signal, a second common gate-type amplifying unit connected to a ground, dividing the input signal into two signals, amplifying the two divided signals, respectively, and providing a third signal and a fourth signal, a signal summing unit summing the first signal and the second signal from the first common gate-type amplifying unit and the third signal and the fourth signal from the second common gate-type amplifying unit, and an impedance matching unit impedance-matching a signal summed by the signal summing unit.

Abstract: Embodiments of apparatuses and systems for a bias network providing accurate quiescent current control are generally described herein. Other embodiments may be described and claimed.

Abstract: An amplifier is disclosed that may include a filter, such as a notch-filter, to filter an output signal provided by the amplifier. The included filter may suppress and/or reduce a gain of the amplifier for a particular range of frequencies. In one embodiment, a frequency response of the filter may be determined by one or more reactive components included within the amplifier. In at least one embodiment, the amplifier may include two or more mutual inductors to reduce the gain of the amplifier when operated at or near a predetermined frequency. In another embodiment, the amplifier may include one or more variable capacitors that may enable the frequency response of the filter to be changed and/or modified.

Abstract: A high voltage metal-oxide-semiconductor transistor device having stepped gate structure and a manufacturing method thereof are provided. The manufacturing method includes following steps. A gate structure is formed on a semiconductor substrate. The semiconductor substrate includes a first region and a second region disposed on a side of a first part of the gate structure and a side of a second part of the gate structure respectively. A patterned mask layer is formed on the semiconductor substrate and the gate structure. The patterned mask layer covers the first region and the first part. The second part is uncovered by the patterned mask layer. An implantation process is performed to form a drift region in the second region. An etching process is performed to remove a part of the second part uncovered by the patterned mask layer. A thickness of the second part is less than that of the first part after the etching process.

Abstract: A condenser microphone includes a condenser microphone unit having a diaphragm and a fixed electrode disposed opposite to the diaphragm; a field effect transistor serving as an impedance converter; and a transistor to generate operational power for the field effect transistor; wherein the field effect transistor comprises a gate, a source and a drain, the gate is connected to the fixed electrode or the diaphragm, the diaphragm disposed opposite to the fixed electrode connected to the gate or the fixed electrode facing the diaphragm connected to the gate is grounded; the source is connected to a base of the transistor; the drain is connected to an emitter of the transistor; and a resistor establishing a base potential of the transistor is disposed between the base of the transistor and a ground.

Abstract: An amplifier includes: a first transistor that includes a first main electrode, a second main electrode, and a first control electrode, a first input signal being input to the first main electrode, a first output signal being output from the second main electrode; a reference potential line that is disposed on a signal line connected to the second main electrode with an insulator interposed therebetween; a first capacitor that is disposed between the first control electrode and the reference potential line; and a first phase shifter configured to shift a phase of a first return current such that the phase of the first return current which flows from the second main electrode to the first control electrode via the reference potential line and the first capacitor has a phase difference, which is greater than 90 degrees and less than 270 degrees, from the phase of the first input signal.

Abstract: A conductive circuit of a thin film for using in a planar magnetic transducer, where the conductive circuit is created from laser etching, including laser ablation or laser delamination of portions of a conductive material disposed on a diaphragm substrate. The conductive circuit so formed has varied widths, height, or spacing throughout the diaphragm, allowing for adaptation to certain desired performance characteristics. Performance characteristics include a uniform force distribution on the diaphragm, creating very high impedance circuits, increasing current in the circuit, increasing force, and increasing efficiency.

Abstract: Methods and devices are described for compensating an effect of aging due to, for example, hot carrier injection, or other device degradation mechanisms affecting a current flow, in an RF amplifier. In one case a replica circuit is used to sense the aging of the RF amplifier and adjust a biasing of the RF amplifier accordingly.

Abstract: Circuits and methods related to power detectors for radio-frequency (RF) applications. In some embodiments, a power amplifier (PA) system can include a PA circuit having a driver stage and an output stage. The PA system can further include a detector configured to receive a portion of an RF signal from a path between the driver stage and the output stage. The detector can be further configured to generate an output signal representative of power associated with the RF signal and compensated for variation in at least one operating condition associated with the PA circuit.

Abstract: An inductor for an integrated circuit can include a first turn comprising a first through silicon via (TSV) coupled to a second TSV. The inductor can include a third TSV coupled to the second TSV.

Abstract: A voltage supply unit including a regulator unit, a voltage divider and a first current mirror. The regulator unit is configured to receive a first voltage signal and a second voltage signal, and is configured to generate a third voltage signal. The voltage divider is connected between the first current mirror and the regulator unit, and controls the second voltage signal. The first current mirror is connected to the regulator unit, an input voltage supply and the voltage divider. The first current mirror is configured to generate a first current signal and a second current signal, the second current signal is mirrored from the first current signal, the first current signal is controlled by the third voltage signal and the second current signal controls an output voltage supply signal.

Abstract: Embodiments include but are not limited to semiconductor devices including a barrier layer, a gallium nitride channel layer having a Ga-face coupled with the barrier layer, and a thermoconductive layer having a thermal conductivity of at least 500 W/(m·K) within 1000 nanometers of a Ga-face of the gallium nitride channel layer. The semiconductor device may be a high-electron-mobility transistor or a semiconductor wafer. Methods for making the same also are described.

Abstract: An amplifier includes a first FET having a first back-gate end, a second FET having a second back-gate end, a third FET having a third back-gate end, a first power supply terminal configured to apply a voltage to the first back-gate end, a second power supply terminal configured to apply a voltage to the second back-gate end, and a third power supply terminal configured to apply a voltage to the third back-gate end. In the stated amplifier, the first through third power supply terminals are configured such that different voltages can be set to the first through third power supply terminals.

Abstract: An embodiment of a compound semiconductor device includes: a substrate; a nitride compound semiconductor stacked structure formed on or above the substrate; and a gate electrode, a source electrode and a drain electrode formed on or above the compound semiconductor stacked structure. A recess positioning between the gate electrode and the drain electrode in a plan view is formed at a surface of the compound semiconductor stacked structure.

Abstract: A common source or common emitter LNA circuit for amplifying signals at an operating frequency f in a receiver circuit is disclosed. The LNA circuit comprises an input transistor arranged to, in operation, be biased to have a transconductance gm at the operating frequency f, and having a first terminal, which is a gate or base terminal, operatively connected to an input terminal of the LNA circuit. The LNA circuit further comprises a shunt-feedback capacitor operatively connected between the first terminal of the input transistor and a second terminal, which is a drain or collector terminal, of the input transistor. Furthermore, the LNA circuit comprises an output capacitor operatively connected between the second terminal of the input transistor and an output terminal of the LNA circuit. The output capacitor has a capacitance value CL<gm/f.

Abstract: A sensor amplifier arrangement includes an amplifier having a signal input to receive a sensor signal and a signal output to provide an amplified sensor signal, and a feedback path that couples the signal output to the signal input and provides a feedback current that is an attenuated signal of the amplified sensor signal and is inverted with respect to the sensor signal.

Abstract: A firing circuit for a thermal inkjet-printing nozzle includes a heater resistor and a switch. The heater resistor heats ink to cause the ink to be ejected from the nozzle. The heater resistor has a first end and a second end, the second end connected to a ground. The switch controls activation of the heater resistor. The switch has a first end connected to a voltage source and a second end connected to the first end of the heater resistor. The switch operates in a constant current mode, such that an at least substantially constant current flows through the heater resistor upon activation.

Abstract: An approach for a transconductance cell for use in a voltage controlled oscillator (VCO) is provided. The transconductance cell includes a first NFET stack connected in series to a first PFET stack. The transconductance cell includes a second NFET stack connected in series to a second PFET stack. The first NFET stack and the first PFET stack are cross-coupled to the second NFET stack and the second PFET stack. The first NFET stack and the second NFET stack are connected to a tail node. The first PFET stack and the second PFET stack are connected to a power supply node.

Abstract: A DC-DC converter control circuit has an inductor configured to be interposed between a first node which is set to a first direct current voltage or a second direct current voltage and a second node which outputs an output voltage at a predetermined direct current voltage level, an error signal generator configured to generate an error signal depending on a voltage difference between a reference voltage and a voltage correlating with the output voltage, a ripple extractor configured to extract and output ripple components contained in the voltage of the first node, a single-ended signal generator configured to generate a single-ended signal based on the error signal and an output signal from the ripple extractor, and a switch drive unit configured to drive and control, based on the single-ended signal, a switch circuit which sets the first node to the first direct current voltage or the second direct current voltage.

Abstract: A current reuse amplifier is disclosed. The amplifier includes a first field effect transistor (FET); and a second FET with a source coupled with a gate of the second FET and a drain of the first FET through a first resistor in a DC mode but floated from a ground in an AC mode. A feature of the current reuse amplifier is that the amplifier further includes a shunt block connected in the source of the second FET to shunt a DC current flowing in the second FET to the ground. A DC current flowing in the first FET is smaller than a DC current flowing in the second FET, and the first FET has a size smaller than a size of the second FET.

Abstract: The present technology relates to a gain control circuit, a communication device, an electronic appliance, and a gain control method which aim to provide a technology capable of suppressing intermodulation distortion. The gain control circuit includes a first amplifier for amplifying an input signal, and a signal determination unit for determining an input signal to be input to the first amplifier, and controlling an amplification factor of the first amplifier based on the determination result. The communication device includes a first amplifier for amplifying a received signal, a receiving unit for performing a receiving process based on a signal output from the first amplifier, and a signal determination unit for determining a received signal to be input to the first amplifier, and controlling the amplification factor of the first amplifier based on the determination result.

Abstract: A variety of circuits, methods and devices are implemented for providing an adjustable resistance. According to one such implementation an adjustable resistive device includes a metal-oxide semiconductor (MOS) transistor having a gate, a drain, a source, and a body. First circuitry controls a resistance from drain to source by applying a gate voltage that is a function of a variable control input. Second circuitry adjusts a voltage at the body according to a drain voltage and a source voltage, whereby the resistance from drain to source is substantially linear for a given value of the variable control input and over a voltage range.

Abstract: Designs and techniques for improving the linearity of the power amplifiers, especially of the non-linear types, operated in microwave and millimeter-wave frequency using method through purposely designed active transistors or passive devices or both, are disclosed. The techniques use the manipulation of transistors' cut-off frequencies (fT) design, attached loaded linearization stub and characteristics of space attenuation of microwave signals individually or in combination of them. The disclosed techniques provide the advantages to compromise the performance among linearity, gain and power consumption in a wide range of power amplifier types, such as Class-AB, B, C, D, E and F in the different application scenarios.

Abstract: A preamplifier (46) comprises a field effect transistor (64) in common source configuration. While the gate of the field effect transistor is coupled to an amplifier input circuit (e.g. MRI coil), the drain of the field effect transistor (64) is coupled to an amplifier output. The preamplifier comprises furthermore a first (66) and a second (68) source-ground connection. The first source-ground lead (66) couples the source of the field effect transistor to the ground node of the amplifier input circuit, while the second source-ground lead (68) couples the source of the field effect transistor to the ground node of the amplifier output circuit. As a result, amplifier output currents generate basically a voltage drop across the second source-ground lead (68). Thus, the amplifier input circuit is less influenced by any common voltage drop across any common source-ground connection.

Abstract: An RF amplifier includes an input stage, a buffer stage, and an output stage. The input stage is configured to provide attenuation and impedance matching for an input radio frequency (RF) signal by providing shunt and series variable resistance current paths and RF power to RF current conversion. The input stage routes the RF current between the current paths resulting in an attenuation of the RF input current. The buffer stage is configured to provide an intermediate RF current which tracks the current level of the attenuated RF input current, thereby providing isolation between the input and output stages. The output stage is configured to provide RF current to RF power conversion, utilizing the intermediate RF current to provide an RF signal having an RF output power proportional to the RF input power.

Abstract: An electronic biasing circuit provides a DC bias voltage to a circuit to be biased. The biasing circuit has a first transistor and a second transistor. A gate of the first transistor is connected to a gate of the second transistor and supplies the DC bias voltage. A source of the first transistor is connected to a supply reference voltage. A source of the second transistor is connected to the supply reference voltage via a resistor element. The currents flowing through the first and second transistor are forced to be equal. A third transistor is connected in series with the first transistor and a fourth transistor is connected in series with the second transistor. Currents flowing through the third and fourth transistors are forced to be equal.

Abstract: A low voltage, switch mode PHEMT power amplifier with a 0.1 ?m gate length and a low loss, lumped element, output matching circuit is disclosed that provides high performance over a frequency range of 1.4 GHz-2.5 GHz. The amplifier makes use of monolithic circuit technology for the first stage and output transistor, and uses a printed circuit board with surface mount components for the output matching network. The power output of the power amplifier is stable over a range of 60 degrees centigrade, has high power efficiencies of 44-53% with greater than 2 watts output power over the frequency range of 1.4 GHz and 2.5 GHz. In addition, through drain voltage control, the output power can be varied over a wide range between about 0.8 to 2.5 watts while still maintaining a high efficiency in the range of 50±3%.

Abstract: A high frequency power amplifier includes an FET chip, a wire connected at a first end to the FET chip, an input-side matching circuit substrate, a resistive element on the input-side matching circuit substrate and connected in series with the FET chip, a transmission portion of a conductive material on the input-side matching circuit substrate, in contact with one end of the resistive element, and connected to an input electrode, a wire connection portion of a conductive material on the input-side matching circuit substrate, in contact with a second end of the resistive element, and connected to a second end of the wire, and a shorting portion of a conductive material having a smaller width than the resistive element and on the resistive element, connecting the transmission portion to the wire connection portion.

Abstract: In one embodiment, a method includes: detecting one of a short-to-ground condition and a short-to-supply condition at an output node; after a delay, selectively activating a feedback control transistor according to the detecting; detecting a first current passing through a first transistor using a second transistor sized to be smaller than the first transistor; mirroring the detected current using a plurality of transistors to form a feedback current; and providing the feedback current to a gate electrode of the first transistor according to the selectively activating the feedback control transistor.

Abstract: An integrated circuit device, set forth by way of example and not limitation, includes an IC package provided with a plurality of leads and enclosing: a) a buffer amplifier, b) a switching-mode power amplifier having an input coupled to the output of the buffer amplifier and having an output coupled to at least one of the plurality of leads, and c) a digital controller. A method, set forth by way of example and not limitation, for controlling the power output of a RF transmitter circuit without the need for an attenuator includes developing a signal source, applying the signal source to a buffer amplifier to provide an amplified signal, applying the amplified signal to a switching-mode power amplifier to provide a power output signal, and controlling a gain of the switching-mode power amplifier in response to a digital command.

Abstract: An amplifier circuit with at least one basic transistor, at least one load transistor, and at least one impedance element, the basic transistor being connected to the impedance element and the load transistor, an amplifier input and output, the amplifier input being connected to the gate contact of the basic transistor and the amplifier output being connected to a source contact of the load transistor. Here the amplifier circuit has at least two combined amplifying cells, with each combined amplifying cell respectively including a basic transistor, a load transistor, and an impedance element, with the basic transistor and the load transistor being non-complementary single-pin transistors, and arranged cooperating with the impedance element, and every combined amplifying cell has an input and an output, which cell input being connected to a gate contact of the basic transistor and which cell output being connected to a contact of the impedance element.

Abstract: A compound semiconductor device includes a substrate; a buffer layer formed on the substrate; an electron transit layer and an electron donating layer formed on the buffer layer; a gate electrode, a source electrode, and a drain electrode formed on the electron donating layer; and an embedded electrode to which a potential independent of the gate electrode, the source electrode, and the drain electrode is supplied to control a potential of the buffer layer.

Abstract: Disclosed embodiments include a direct current to direct current (DC-DC) converter including one or more charge pumps and configured to receive an input voltage and a first clock signal and a second clock signal. The first clock signal and second clock signal may be non-overlapping, and each may alternate between a ground voltage and a first voltage. The DC-DC converter may be configured to produce an output voltage over the clock cycle that has a negative polarity with a magnitude substantially equal to a sum of magnitudes of the input voltage and an integer multiple of the first voltage, the integer multiple being equal to a number of the one or more charge pumps in the DC-DC converter.

Abstract: An amplifier circuit includes: first and second nodes configured to receive input of differential signals; third and fourth nodes; a plurality of first inductors configured to be connected in series between the first and second nodes; a plurality of second inductors configured to be connected in series between the third and fourth nodes; a plurality of field effect transistors configured to have gates each configured to be connected between the plurality of first inductors, sources each configured to be connected to a reference potential node, and drains each configured to be connected between the plurality of second inductors; and a synthesizing unit configured to synthesize signals at the third and fourth nodes.

Abstract: According to embodiments of the present invention, an over-input signal may be limited to be within a range between adjustable upper limit voltage and lower limit voltage while suppressing deterioration of a noise figure. An amplifier circuit includes an input transistor; an input transistor; a resistor element having a first terminal connected to a gate of the input transistor and a second terminal connected to a bias voltage; and a protective circuit connected to the gate of the input transistor and limiting an input to the gate of the input transistor to be within a range between an upper limit voltage and lower limit voltage adjustable based on the bias voltage.

Abstract: Linearity and power efficiency in a power amplifier circuit are enhanced. The power amplifier circuit includes a first transistor that amplifies a signal input to the base and that outputs the amplified signal from the collector and a first capacitor that is disposed between the base and the collector of the first transistor and that has voltage dependency of a capacitance value lower than that of a base-collector parasitic capacitance value of the first transistor.

Abstract: An amplifier is disclosed that avoids an increase in circuit scale and an increase in power consumption, and easily avoids the odd-order harmonics. This amplifier includes a MOS transistor including a plurality of gate fingers or a plurality of MOS transistors each including a single gate finger; a dielectric capacitor that is added to each of the gate fingers; and a variable resistor that is connected between an input terminal to which an AC signal is input, and a gate input terminal. In the amplifier, the variable resistor, gate resistors of the respective gate fingers, and the dielectric capacitors form a plurality of low pass filters having desired frequency characteristics, and the gate fingers are different from each other in width or length from the gate input terminal to an oxide diffusion (OD) area boundary.

Abstract: Various embodiments include a power amplifier having power amplifier cells located in a die, conductive contacts overlying a surface of the die and coupled to the amplifier cells, and conductive lines overlying a surface of the die between the conductive contacts and coupled to the power amplifier cells. Additional apparatus are described.

Abstract: A circuit may include one or more transistors connected directly to an output, and an inductance network. The inductance network may connect to a source node of at least one of the transistors, to compensate capacitance of the output. Thus, the response time of the circuit may decrease, and a non-dominant frequency response pole frequency of the circuit may increase.

Abstract: A combination NMOS/PMOS power amplifier is disclosed. In an exemplary embodiment, the amplifier includes a first amplifier section comprising a first NMOS transistor that is configured to provide a first amplified output and a second amplifier section comprising a first PMOS transistor that is configured to provide a second amplified output. The first PMOS transistor is coupled to the first NMOS transistor at a selected node to reduce capacitance variation at the selected node.

Abstract: An apparatus, comprises three driver FETs coupled at their sources; note-driver circuit; a first sense FET coupled to the sources of the three driver FETs; a current mirror having the first sense FET and a mirror FET; wherein the first sense FET is coupled to the mirror FET; a first transconductance amplifier coupled to the first sense FET; a second amplifier coupled to the current mirror, and an output of the first transconductance amplifier is an input to the second amplifier.

Abstract: A current mirror circuit is described. The current mirror circuit includes a first transistor and a second transistor. The gates of the first transistor and the second transistor are coupled at a bias voltage. The current mirror circuit also includes an auxiliary transistor that is biased into weak inversion by receiving the bias voltage at a gate of the auxiliary transistor after being reduced by an offset voltage. The sources of the first transistor, second transistor and auxiliary transistor are coupled together. A primary current from the drain of the second transistor is combined with an auxiliary current from the drain of the auxiliary transistor to produce an output current.

Abstract: A radio frequency (RF) power amplifier (PA) may include a first transistor and a second transistor. A first power cell may be coupled with the first transistor, and a second power cell may be coupled with the second transistor. In embodiments, the first transistor may be scaled to operate at a first current density, while the second transistor may be scaled to operate at a second current density.

Abstract: An apparatus comprising an amplifier comprising an input, a capacitor having a capacitor first side and a capacitor second side, wherein the capacitor first side is coupled to the input, a switch having a switch first side and a switch second side, wherein the switch first side is coupled to the capacitor second side, and a transistor having a transistor gate, and a transistor source, wherein the transistor gate is coupled to the input and the capacitor first side, wherein the transistor source is coupled to the switch second side and wherein the switch is positioned directly between the capacitor second side and the transistor source.

Abstract: A system comprises a power amplifier configured to amplify an input signal, a splitter configured to split the amplified input signal into a plurality of output signals, a plurality of filters configured to filter the plurality of output signals, respectively, to produce a plurality of filtered output signals, and a combiner configured to combine the filtered output signals to produce a combined output signal.