Having Different Configurations Patents (Class 330/311)
  • Patent number: 11223329
    Abstract: A power amplifier circuitry (100) comprises: a transistor stack (110) comprising at least two stacked transistor units (112A, 112B, 112C) for amplifying input signals; wherein each stacked transistor unit (112A, 112B, 112C) comprises a plurality of controllable segments (120-1 to 120-N, 130-1 to 130-N, 140-1 to 140-N), each comprising a segment transistor (122, 132, 142), wherein source terminals (123, 133, 143) within each transistor unit are connected, drain terminals (125, 135, 145) within each transistor unit are connected and gate terminals (124, 134, 144) within each transistor unit are connected, wherein each segment transistor (122, 132, 142) further comprises a back gate terminal (126, 136, 146) for setting a body bias, wherein at least two of the segment transistors (122, 132, 142) within each transistor unit have independently connected back gate terminals (126, 136, 146); and a control unit (190) configured to control the body bias for selecting an amplifier class of each of the controllable segme
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: January 11, 2022
    Assignees: IMEC USA NANOELECTRONICS DESIGN CENTER, Inc., IMEC VZW
    Inventors: Aritra Banerjee, Pierre Wambacq
  • Patent number: 11201594
    Abstract: An amplifier circuit is a cascade amplifier circuit that includes a first transistor circuit including a signal input portion to which a signal is input from outside; a load circuit connected between the first transistor circuit and a power-supply line; and a second transistor cascode-connected between the load circuit and the first transistor circuit. The first transistor circuit is constituted by a plurality of transistors connected in parallel, and a bias circuit is provided that selectively supplies a bias voltage to the plurality of transistors.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: December 14, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Nobuyasu Beppu
  • Patent number: 11190139
    Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: November 30, 2021
    Assignee: pSemi Corporation
    Inventors: Poojan Wagh, Kashish Pal, Robert Mark Englekirk, Tero Tapio Ranta, Keith Bargroff, Simon Edward Willard
  • Patent number: 11177782
    Abstract: Methods and devices to fabricate low-cost wideband LNAs that are tunable to multiple frequency bands. Decoupling capacitors are used as part of a tuning circuit implemented at the LNA input. The capacitors are switchably selectable to also tune a signal into desired frequency bands.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: November 16, 2021
    Assignee: PSEMI CORPORATION
    Inventor: Cheng-Kai Luo
  • Patent number: 11133783
    Abstract: A power amplifier may comprise: an element for amplifying an electrical signal received through an input terminal, and outputting the amplified electrical signal through an output terminal; a first impedance adjustment circuit connected to the input terminal of the element and adjusting impedance with respect to a frequency of a fundamental component at the input terminal; a second impedance adjustment circuit connected to the input terminal of the element and adjusting impedance with respect to a frequency of a multiplied harmonic component at the input terminal; a third impedance adjustment circuit connected to the output terminal of the element and adjusting impedance with respect to the frequency of the fundamental component at the output terminal; a fourth impedance adjustment circuit connected to the output terminal of the element and adjusting impedance with respect to the frequency of the multiplied harmonic component at the output terminal; a first frequency separation circuit which prevents an imped
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: September 28, 2021
    Inventors: Sung-Ku Yeo, Bum-Man Kim, Yun-Sik Park, Sang-Wook Kwon, Dong-Gyu Min, Sung-Bum Park
  • Patent number: 11025205
    Abstract: When a potential difference V1 between a source terminal of an E-type FET (11) and a source terminal of a D-type FET (12) is larger than a threshold voltage Vth, a protection circuit (13) starts an operation to reduce the potential difference V1 such that the potential difference V1 is smaller than the threshold voltage Vth. This makes it possible to prevent destruction of the E-type FET (11) even when a signal to be amplified is an RF signal.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: June 1, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Eigo Kuwata, Yutaro Yamaguchi
  • Patent number: 10958220
    Abstract: A biasing circuit with high current drive capability for fast settling of a biasing voltage to a stacked cascode amplifier is presented. According to a first aspect, the biasing circuit uses transistors matched with transistors of the cascode amplifier to generate a boost current during a transition phase that changes the biasing voltage by charging or discharging a capacitor. The boost current is activated during the transition phase and deactivated when a steady-state condition is reached. According to a second aspect, the biasing circuit uses an operational amplifier in a feedback loop that forces a source node of a cascode transistor of a reference circuit, that is a scaled down replica version of the cascode amplifier, to be at a reference voltage. The high gain and high current capability of the operational amplifier, provided by isolating a high frequency signal processed by the cascode amplifier from the reference circuit, allow for a quick settling of the biasing voltage.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: March 23, 2021
    Assignee: pSemi Corporation
    Inventors: Jonathan James Klaren, Tero Tapio Ranta
  • Patent number: 10951171
    Abstract: Power amplifiers and related methods are disclosed having configurable switched mode operation in a high-power mode of operation and a low-power mode of operation. The power amplifiers have a first cascode amplifier coupled to receive a positive differential input and a second cascode amplifier coupled to receive a negative differential input. The first and second cascode amplifiers include output stages and first/second input stages. The first input stages and the second input stages are enabled in a high-power mode of operation. The first input stages are disabled and the second input stages are enabled during a low-power mode of operation. For further embodiments, a switchable clamp operates in the low-power mode to clamp a voltage output for the second input stages. For further embodiments, the output stages are provided a variable voltage bias or are coupled to tunable capacitances that are varied between the low-power and high-power modes.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: March 16, 2021
    Assignee: NXP USA, Inc.
    Inventors: Maicol Cannella, Aurelien Larie, Stefano Dal Toso
  • Patent number: 10917057
    Abstract: A power amplifier circuit includes a first transistor, wherein a radio frequency signal is inputted to a base or gate of the first transistor; a second transistor having an emitter connected to a collector or drain of the first transistor, wherein a first voltage is supplied to a collector of the second transistor, and a first amplified signal obtained by amplifying the radio frequency signal is outputted from the collector of the second transistor; and a third transistor configured to supply a bias voltage to a base of the second transistor. A second voltage is supplied to a collector or drain of the third transistor, a third voltage corresponding to the first voltage is supplied to a base or gate of the third transistor, and the bias voltage, which corresponds to the third voltage, is supplied from an emitter or source of the third transistor.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: February 9, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hidetoshi Matsumoto, Satoshi Tanaka, Masatoshi Hase
  • Patent number: 10804849
    Abstract: A self-biased amplifier includes a capacitor, a bias generation circuit and a common source amplifier. The capacitor is used to receive an input voltage and output an alternating component of the input voltage. The bias generation circuit is coupled to the capacitor, and used to generate a first bias voltage according to the alternating component. The common source amplifier is coupled to the bias generation circuit, and used to generate an amplified voltage according to the first bias voltage.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: October 13, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ke-Han Chen, Min-Chia Wang
  • Patent number: 10804951
    Abstract: Described herein are variable-gain amplifier configurations that include a multi-input gain stage, a cascode buffer, and a bypass block. Degeneration switching blocks can be used for the entire multi-input gain stage or for individual input nodes of the multi-input gain stage. This advantageously reduces or eliminates performance penalties in one or more gain modes. The variable impedances can be configured to improve linearity of the amplification process in targeted gain modes. The variable gain amplifier can be configured to provide a low-loss bypass mode in a low gain mode to improve signal quality.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: October 13, 2020
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Johannes Jacobus Emile Maria Hageraats, Junhyung Lee, Joshua Haeseok Cho, Aravind Kumar Padyana, Bipul Agarwal
  • Patent number: 10771023
    Abstract: An amplifier including a signal input terminal, at least one signal output terminal, a first and a second cascode amplifier circuits, a capacitor and a loading circuit. The signal input terminal receives an input signal. The first cascode amplifier circuit includes a first and a second input terminals and a first and a second output terminals. The first input terminal coupled to the signal input terminal receives the input signal. The second cascode amplifier circuit includes a third and a fourth input terminals and a third output terminal. The third input terminal is coupled to the first output terminal, and the third output terminal is coupled to the second input terminal. Two terminals of the capacitor are coupled to the fourth input terminal and the first output terminal respectively. A terminal of the loading circuit is coupled to the third output terminal, and another terminal of the loading circuit is coupled to the second output terminal.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: September 8, 2020
    Assignee: RichWave Technology Corp.
    Inventor: Ting-Yuan Cheng
  • Patent number: 10756684
    Abstract: A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: August 25, 2020
    Assignee: pSemi Corporation
    Inventors: Dan William Nobbe, David Halchin, Jeffrey A. Dykstra, Michael P. Gaynor, David Kovac, Kelly Michael Mekechuk, Gary Frederick Kaatz, Chris Olson
  • Patent number: 10715200
    Abstract: A monolithic integrated circuit (IC), and method of manufacturing same, that includes all RF front end or transceiver elements for a portable communication device, including a power amplifier (PA), a matching, coupling and filtering network, and an antenna switch to couple the conditioned PA signal to an antenna. An output signal sensor senses at least a voltage amplitude of the signal switched by the antenna switch, and signals a PA control circuit to limit PA output power in response to excessive values of sensed output. Stacks of multiple FETs in series to operate as a switching device may be used for implementation of the RF front end, and the method and apparatus of such stacks are claimed as subcombinations. An iClass PA architecture is described that dissipatively terminates unwanted harmonics of the PA output signal.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: July 14, 2020
    Assignee: pSemi Corporation
    Inventors: Mark L. Burgener, James S. Cable
  • Patent number: 10530412
    Abstract: Described herein are variable gain amplifiers that selectively provide variable or tailored impedances at a degeneration block and/or feedback block depending at least in part on a gain mode of the variable gain amplifier. This advantageously reduces or eliminates performance penalties in one or more gain modes. The variable impedances can be configured to improve linearity of the amplification process in targeted gain modes. The variable gain amplifier can be configured to provide a low-loss bypass mode in a low gain mode to improve signal quality. The degeneration block can be selectively isolated from a reference potential node to improve performance.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: January 7, 2020
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Johannes Jacobus Emile Maria Hageraats, Junhyung Lee, Joshua Haeseok Cho, Aravind Kumar Padyana, Bipul Agarwal
  • Patent number: 10469039
    Abstract: In an exemplary structure, a transformer has a primary side and a secondary side. Output from the primary side is coupled to the secondary side. A first power supply is connected to a center tap of the primary side of the transformer. An oscillator includes a first transistor and a second transistor. The front-gate of the first transistor is connected to the drain of the second transistor and the primary side of the transformer. The front-gate of the second transistor is connected to the drain of the first transistor and the primary side of the transformer. A third transistor is connected to the first transistor and a fourth transistor is connected to the second transistor. The third and fourth transistors inject a desired frequency to the oscillator. A voltage source is connected to the back-gate of the first transistor and the back-gate of the second transistor.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: November 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: See T. Lee, Abdellatif Bellaouar
  • Patent number: 10454426
    Abstract: Methods and apparatus for providing high efficiency power amplifiers for both high and low output power levels are disclosed. An example apparatus includes a first amplifier to amplify a signal from a host device; and transmit the amplified signal to an antenna; a second amplifier to amplify the signal from the host device; and transmit the amplified signal to the antenna; and first, second, and third switches to: when the first and second switches are closed and the third switch is open, couple the first amplifier to the second amplifier in a parallel structure; and when the first and second switches are open and the third switch is closed, couple the first amplifier to the second amplifier in a stacked structure.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: October 22, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Oddgeir Fikstvedt
  • Patent number: 10333471
    Abstract: A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: June 25, 2019
    Assignee: pSemi Corporation
    Inventors: Dan Willaim Nobbe, David Halchin, Jeffrey A. Dykstra, Michael P. Gaynor, David Kovac, Kelly Michael Mekechuk, Gary Frederick Kaatz, Chris Olson
  • Patent number: 10291194
    Abstract: In accordance with an embodiment, a circuit includes: a replica input transistor, a first replica cascode transistor, an active current source, and an active cascode biasing circuit. The active current source is configured to set a current flowing through the first replica cascode transistor and the replica input transistor to a predetermined value by adjusting a voltage of a control node of the replica input transistor; and an active cascode biasing circuit including a first output coupled to the control node of the first replica cascode transistor, and the active cascode biasing circuit configured to set a drain voltage of the replica input transistor to a predetermined voltage by adjusting a voltage of the control node of the first replica cascode transistor.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: May 14, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Nikolay Ilkov, Andreas Baenisch, Peter Pfann, Hans-Dieter Wohlmuth
  • Patent number: 10243523
    Abstract: Design of ultra broadband transimpedance amplifiers (TIA) for optical fiber communications is disclosed. In one embodiment, a TIA comprises a gm-boosted dual-feedback common-base stage, a level shifter and an RC-degenerated common-emitter stage, and a first emitter-follower stage, wherein the first emitter follower stage is inductively degenerated. An output of the TIA is buffered using a second emitter-follower stage.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: March 26, 2019
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Payam Heydari, Seyed Mohammad Hossein Mohammadnezhad, Alireza Karimi Bidhendi, Michael M. Green, David Howard, Edward Preisler
  • Patent number: 10243519
    Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can have a varying supply voltage that varies according to a control voltage. The control voltage can be related to a desired output power of the amplifier and/or to an envelope signal of an input signal to the amplifier. Particular biasing for selectively controlling the stacked transistors to operate in either a saturation region or a triode region is also presented. Benefits of such controlling, including increased linear response of an output power of the amplifier, are also discussed.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: March 26, 2019
    Assignee: pSemi Corporation
    Inventors: Jeffrey A. Dykstra, David Kovac
  • Patent number: 10236872
    Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: March 19, 2019
    Assignee: pSemi Corporation
    Inventors: Simon Edward Willard, Tero Tapio Ranta
  • Patent number: 10230417
    Abstract: Described herein are variable gain amplifiers that selectively provide variable or tailored impedances at a degeneration block and/or feedback block depending at least in part on a gain mode of the variable gain amplifier. This advantageously reduces or eliminates performance penalties in one or more gain modes. The variable impedances can be configured to improve linearity of the amplification process in targeted gain modes. The variable gain amplifier can be configured to provide a low-loss bypass mode in a low gain mode to improve signal quality.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: March 12, 2019
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Johannes Jacobus Emile Maria Hageraats, Junhyung Lee, Joshua Haeseok Cho, Aravind Kumar Padyana, Bipul Agarwal
  • Patent number: 10199992
    Abstract: System-on-chip (SOC) products using high frequency, wideband, highly linear, CMOS and BiCMOS processes will be the next evolution of wireless and wireline communications integrated circuits. Aspects described herein can provide enhanced overall performance over existing prior art single-ended, wideband RF amplifier topologies. A single-ended third order intermodulation distortion nulling circuit can extend the dynamic range for wideband amplifiers up to an order-of-magnitude, without a DC power or noise figure (NF) penalty. The application of distortion nulling can be extended to all the building blocks used in CMOS/BiCMOS RF transceivers to improve performance. The application of this concept to all of the building blocks in an RF transceiver will allow the dynamic range of the transceiver to be increased without suffering a DC power dissipation increase or a significant noise increase.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: February 5, 2019
    Inventors: Wais M. Ali, Lloyd F. Linder
  • Patent number: 10187016
    Abstract: An amplifier having improved linearity is disclosed. The amplifier includes a main transistor having a first current input terminal, a first current output terminal, and a first control terminal coupled to an RF input terminal that receives a signal voltage. A cascode transistor has a second current input terminal coupled to an RF output terminal for outputting an amplified signal. The cascode transistor has a second control terminal, and a second current output terminal coupled to the first current input terminal. Linearization circuitry has a bias output terminal coupled to the second control terminal. The linearization circuitry is configured to generate a bias signal at the bias output terminal to maintain a quiescent point of the main transistor for a given load coupled to the RF output terminal such that output conductance of the main transistor decreases nonlinearly with increasing main voltage and increases nonlinearly with decreasing main voltage.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: January 22, 2019
    Assignee: Qorvo US, Inc.
    Inventors: George Maxim, Kelvin Kai Tuan Yan, Marcus Granger-Jones, Dirk Robert Walter Leipold, Baker Scott
  • Patent number: 10177724
    Abstract: A power amplifier circuit includes first and second transistors and a first voltage output circuit. A radio frequency signal is input into a base of the first transistor. The first voltage output circuit outputs a first voltage in accordance with a power supply voltage. The first voltage is supplied to a base or a gate of the second transistor. An emitter or a source of the second transistor is connected to a collector of the first transistor. A first amplified signal generated by amplifying the radio frequency signal is output from a collector or a drain of the second transistor.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: January 8, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Kazuo Watanabe, Takayuki Tsutsui, Masao Kondo, Satoshi Arayashiki, Fumio Harima, Masatoshi Hase
  • Patent number: 10148234
    Abstract: Systems, methods and apparatus for practical realization of an integrated circuit comprising a stack of transistors operating as an RF amplifier are described. As stack height is increased, capacitance values of gate capacitors used to provide a desired distribution of an RF voltage at the output of the amplifier across the stack may decrease to values approaching parasitic/stray capacitance values present in the integrated circuit which may render the practical realization of the integrated circuit difficult. Coupling of an RF gate voltage at the gate of one transistor of the stack to a gate of a different transistor of the stack can allow for an increase in the capacitance value of the gate capacitor of the different transistor for obtaining an RF voltage at the gate of the different transistor according to the desired distribution.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: December 4, 2018
    Assignee: pSemi Corporation
    Inventor: Jaroslaw Adamski
  • Patent number: 10044330
    Abstract: A power amplifier module includes a first current source that outputs a first current corresponding to a level control voltage for controlling a signal level of an amplified signal, a second current source that outputs a second current corresponding to the level control voltage, a first transistor in which an input signal and a first bias current are supplied to a base and an emitter is grounded, a second transistor in which an emitter is connected to a collector of the first transistor, the second current is supplied to a base, and a first amplified signal obtained by amplifying the input signal is output from a collector, and a third transistor in which the first current is supplied to a collector, a bias control current or voltage is supplied to a base, and the first bias current is supplied from an emitter to the base of the first transistor.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: August 7, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shota Ishihara, Seiko Ono, Yusuke Shimamune, Fuminori Morisawa, Shizuki Nakajima, Yuri Honda, Kazuhiro Koshio, Masato Sato
  • Patent number: 9973145
    Abstract: An envelope tracking amplifier having stacked transistors is presented. The envelope tracking amplifier uses dynamic bias voltages at one or more gates of the stacked transistors in addition to a dynamic bias voltage at a drain of a transistor.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: May 15, 2018
    Assignee: pSemi Corporation
    Inventors: Dan William Nobbe, Jeffrey A. Dykstra, Chris Olson, James S. Cable
  • Patent number: 9960737
    Abstract: Systems, methods and apparatus for efficient power control of an RF amplifier for amplification of a constant envelope RF signal are described. A reduction in a size of a pass device of an LDO regulator is obtained by removing the pass device of the LDO regulator from a main current conduction path of the RF amplifier. Power control is provided by varying one or more gate voltages to cascoded transistors of a transistor stack of the RF amplifier according to a power control voltage. Various configurations for controlling the gate voltages are presented by way of a smaller size LDO regulator or by completely removing the LDO regulator. In a case where a supply voltage to the transistor stack varies, such as in a case of a battery, a compensation circuit is used to adjust the power control voltage in view of a variation of the supply voltage, and therefore null a corresponding drift in output power of the RF amplifier.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: May 1, 2018
    Assignee: pSemi Corporation
    Inventor: David Kovac
  • Patent number: 9935585
    Abstract: Embodiments of a radio frequency (RF) amplification are disclosed. The RF amplification device includes a first RF amplification circuit, a second RF amplification circuit, and power control circuitry operable in a first power mode and a second power mode. The first RF amplification circuit has a cascode amplifier stage configured to amplify an RF signal. The cascode amplifier stage has an input transistor and a cascode output transistor that are stacked in cascode. The second RF amplification circuit is configured to amplify the RF signal. The power control circuitry is configured to bias the first cascode output transistor so that the first cascode output transistor operates in a saturation region in the first power mode and bias the first cascode output transistor so that the first cascode output transistor operates in a triode region in the second power mode. The second RF amplification circuit is assisted without introducing additional loading.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: April 3, 2018
    Assignee: Qorvo US, Inc.
    Inventor: Alireza Shirvani
  • Patent number: 9923521
    Abstract: Systems, methods and apparatus for efficient power control of an RF amplifier for amplification of a constant envelope RF signal are described. A reduction in a size of a pass device of an LDO regulator is obtained by removing the pass device of the LDO regulator from a main current conduction path of the RF amplifier. Power control is provided by varying one or more gate voltages to cascoded transistors of a transistor stack of the RF amplifier according to a power control voltage. Various configurations for controlling the gate voltages are presented by way of a smaller size LDO regulator or by completely removing the LDO regulator. In a case where a supply voltage to the transistor stack varies, such as in a case of a battery, a compensation circuit is used to adjust the power control voltage in view of a variation of the supply voltage, and therefore null a corresponding drift in output power of the RF amplifier.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: March 20, 2018
    Assignee: pSemi Corporation
    Inventor: David Kovac
  • Patent number: 9838047
    Abstract: A method is provided for reducing non-linear effects in an electronic circuit including an amplifier. The method may include receiving a modulated signal at an input of the amplifier, the modulated signal comprising a baseband signal modulated by an oscillator frequency. The method may further include substantially attenuating counter-intermodulation in the modulated signal caused by harmonics of the oscillator frequency and the baseband signal by a resonant circuit. In some embodiments, the resonant circuit may include at least one inductive element and one capacitive element coupled to the at least one inductive element, the at least one inductive element and the at least one capacitive element configured to substantially attenuate counter-intermodulation in the modulated signal.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: December 5, 2017
    Assignee: Intel IP Corporation
    Inventor: Omid Oliaei
  • Patent number: 9787252
    Abstract: Embodiments of a radio frequency (RF) amplification are disclosed. The RF amplification device includes a first RF amplification circuit, a second RF amplification circuit, and power control circuitry operable in a first power mode and a second power mode. The first RF amplification circuit has a cascode amplifier stage configured to amplify an RF signal. The cascode amplifier stage has an input transistor and a cascode output transistor that are stacked in cascode. The second RF amplification circuit is configured to amplify the RF signal. The power control circuitry is configured to bias the first cascode output transistor so that the first cascode output transistor operates in a saturation region in the first power mode and bias the first cascode output transistor so that the first cascode output transistor operates in a triode region in the second power mode. The second RF amplification circuit is assisted without introducing additional loading.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: October 10, 2017
    Assignee: Qorvo US, Inc.
    Inventor: Alireza Shirvani
  • Patent number: 9780746
    Abstract: An apparatus includes an input port, an output port, and a plurality of amplifier stages connected in parallel between the input port and the output port. Each of the amplifier stages comprises a common source field effect transistor (CSFET) and at least two common gate field effect transistors (CGFETs) coupled in series with a drain of the common source FET. At least one of the common gate field effect transistors of each stage includes a stabilizing network connected between drain and source diffusions.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: October 3, 2017
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventor: Kohei Fujii
  • Patent number: 9780738
    Abstract: A semiconductor device is provided with: a field-effect transistor that has a source electrode and a drain electrode that are connected to a semiconductor layer, a gate electrode that is provided on the surface of the semiconductor layer between the source electrode and the drain electrode, and a field plate electrode that is provided on the surface of the semiconductor layer in the vicinity of the gate electrode via an insulating layer, wherein the field-effect transistor amplifies high frequency signals received by the gate electrode to be outputted from the drain electrode; and a voltage dividing circuit that divides a potential difference between the drain electrode and a reference potential GND, and applies a bias voltage such that respective parts of the field plate electrode have a mutually equal potential.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: October 3, 2017
    Assignee: Renesas Electronics Corporation
    Inventor: Kazuki Ota
  • Patent number: 9755595
    Abstract: A device includes: a transistor having an input terminal configured to receive an input signal and to amplify the input signal; a bias current source configured to set a bias current of the input terminal of the transistor, the bias current source having a control input for receiving a control signal for selecting the bias current to have one of a plurality of selectable bias current levels; a bias resistance connected between the bias current source and the input terminal of the transistor; a bypass switch for selectively bypassing a first part of the bias resistance; and a control circuit for controlling the bypass switch to bypass the part of the bias resistance for a predefined time period in response to a change in the bias current level, and for controlling the bypass switch to stop bypassing the first part of the bias resistance after the predefined time period expires.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: September 5, 2017
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventor: Saihua Lin
  • Patent number: 9748905
    Abstract: The disclosure provides a communication circuit including an amplification circuit, a replicator circuit, and a correction circuit. Specifically, the amplification circuit generates an amplified signal. The replicator circuit emulates the amplification circuit and generates a replicated signal that approximates the amplified signal. The replicated signal is used by the correction circuit to generate control signals for controlling the amplification circuit.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: August 29, 2017
    Assignee: Qorvo US, Inc.
    Inventors: Baker Scott, Dirk Robert Walter Leipold, George Maxim
  • Patent number: 9559654
    Abstract: Disclosed is a power amplification module which has a comparatively small size and is capable of adjusting the rising characteristic of a gain. The power amplification module includes a first gain control current generation circuit which generates a first gain control current changing with a control voltage, a first bias current generation circuit which generates a first bias current according to the first gain control current, a gain control voltage generation circuit which generates a gain control voltage changing with the control voltage, a first transistor which is emitter-grounded and in which an input signal and the first bias current are supplied to a base thereof, and a second transistor which is cascode-connected to the first transistor and in which the gain control voltage is supplied to a base thereof and a first output signal obtained by amplifying the input signal is output from a collector thereof.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: January 31, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hayato Nakamura, Mitsuo Ariie, Tadashi Matsuoka, Tsutomu Onaro
  • Patent number: 9543909
    Abstract: An amplifier includes a variable shunt circuit including a first transistor group and a second transistor group. The first transistor group includes at least one transistor including a first terminal connected directly or indirectly to a voltage-current conversion circuit, a second terminal connected directly or indirectly to a load, and a third terminal connected directly or indirectly to a control circuit. The second transistor group includes at least one transistor including a first terminal connected directly or indirectly to the voltage-current conversion circuit, a second terminal connected directly or indirectly to a power source or a ground, and a third terminal connected directly or indirectly to the control circuit. The amplifier is configured to amplify the input signal under exclusive control from the control circuit on a pair of the at least one transistor of the first transistor group and the at least one transistor of the second transistor group.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: January 10, 2017
    Assignee: Sony Corporation
    Inventor: Katsuaki Takahashi
  • Patent number: 9520846
    Abstract: Certain aspects of the present disclosure provide methods and apparatus for processing an input signal. One example apparatus is a circuit that generally includes an amplifier, comprising a first transistor and a second transistor connected in cascode with the first transistor; a buffer coupled to an output of the amplifier and configured to provide feedback to the amplifier; and a current source coupled to the second transistor and incorporated into a loop of the feedback to the amplifier.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: December 13, 2016
    Assignee: Qualcomm Incorporated
    Inventors: Seyed Hossein Miri Lavasani, Cheng-Han Wang, Abbas Komijani, Mohammad Bagher Vahid Far
  • Patent number: 9496827
    Abstract: An RF amplifier includes a branch with an inductor series-connected with a capacitor between first and second power supply nodes, a junction point between the inductor and capacitor forming an output node. A further branch includes a MOS transistor series-connected with a switch between the output node and the second power supply node. The switch has a control node coupled to receive a first input signal. The MOS transistor has a gate coupled to receive a second input signal. A control circuit applies the power supply voltage as the second input signal when a frequency/phase-modulated signal is applied as the first input signal. The control circuit further applies a variable signal as the second input signal when a radio frequency signal of constant frequency, phase, and amplitude is applied as the first input signal, and in this mode the MOS transistor is constrained to operate as a current source.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: November 15, 2016
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventor: Michel Ayraud
  • Patent number: 9467106
    Abstract: The present disclosure includes circuits and methods for wideband biasing. In one embodiment, an amplifier includes a cascode transistor between an input and an output of the amplifier. The cascode transistor receives a bias from a bias circuit comprising a resistor between the power supply and a first node, a resistor between the first node and a reference voltage, and a capacitor between the power supply and the first node. The power supply may be a modulated power supply, which is coupled through the bias circuit to a capacitance at the control terminal of the cascode transistor. An inductor is configured between a terminal of the cascode transistor and the power supply. The inductor may isolate the output from the modulated supply signal.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: October 11, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Jose Cabanillas, Calogero Davide Presti
  • Patent number: 9444413
    Abstract: An amplifier (100) comprising: first, second, third and fourth transistors (M1, M2, M3, M4), an input (10) for an input signal, and a first output (22) for a first amplified signal; a first terminal (T11) of the first transistor (M1) coupled to a first voltage rail (12), a second terminal (T12) of the first transistor (M1) coupled to a first terminal (T31) of the third transistor (M3), and a gate (G1) of the first transistor (M1) coupled to the input (10); a first terminal (T21) of the second transistor (M2) coupled to a second voltage rail (14), a second terminal (T22) of the second transistor (M2) coupled to the first output (22), and a gate (G2) of the second transistor (M2) coupled to the input (10); a load (40) coupled between a second terminal (T32) of the third transistor (M3) and a third voltage rail (20), and a gate (G3) of the third transistor (M3) coupled to a bias node (16) for applying a bias voltage to the gate (G3) of the third transistor (M3); a first terminal (T41) of the fourth transistor
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: September 13, 2016
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Daniele Mastantuono, Sven Mattisson
  • Patent number: 9444416
    Abstract: An apparatus includes a first depletion-mode transistor, a first enhancement-mode transistor, and a pull down switch. The first depletion-mode transistor has a common source configuration. The first enhancement-mode transistor has a common gate configuration. The first depletion-mode transistor and the first enhancement-mode transistor are coupled in a cascode arrangement. The pull down switch is operatively coupled between a gate of the enhancement-mode transistor and a circuit ground.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: September 13, 2016
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventor: Ian M. Bisby
  • Patent number: 9431975
    Abstract: In some embodiments, circuits for providing Class-E power amplifiers are provided, the circuits comprising: a first switch having a first side and a second side; a first Class-E load network coupled to the first side of the first switch; a second Class-E load network: and a second switch having a first side and a second side, the first side of the second switch being coupled the second side of the first switch and the second Class-E load network. In some embodiments, the circuits further comprise: a third switch having a first side and a second side; a third Class-E load network coupled to the first side of the third switch; a fourth Class-E load network; and a fourth switch having a first side and a second side, the first side of the fourth switch being coupled the second side of the third switch and the fourth Class-E load network.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: August 30, 2016
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Anandaroop Chakrabarti, Harish Krishnaswamy
  • Patent number: 9413298
    Abstract: An envelope tracking amplifier having stacked transistors is presented. The envelope tracking amplifier uses dynamic bias voltages at one or more gates of the stacked transistors in addition to a dynamic bias voltage at a drain of a transistor.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 9, 2016
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Dan William Nobbe, Jeffrey A. Dykstra, Chris Olson, James S. Cable
  • Patent number: 9407211
    Abstract: An apparatus having a first circuit and a second circuit. The first circuit may be configured to generate an output signal in response to an intermediate signal. The first circuit may be implemented using a first transistor type. The second circuit may be configured to generate the intermediate signal in response to (i) an input signal and (ii) a feedback of the output signal. The second circuit may be implemented using a second transistor type. The output signal is an amplified version of the input signal while maintaining linearity.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: August 2, 2016
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventor: Brian J. McNamara
  • Patent number: 9407210
    Abstract: An amplifier for amplifying signals is presented. A cascode power amplifies includes two or more adjacent cascode amplifiers and at least one remote cascode amplifier. The adjacent cascode amplifiers are lined up adjacent each other with inputs of the adjacent cascode amplifiers connected to a common input line and outputs of the of adjacent cascode amplifiers connected to a common output line. The adjacent cascode amplifiers generally operate in parallel. The remote cascode amplifier is spaced apart from the adjacent cascade amplifiers. An input transmission line connects an input of the remote cascode amplifier to the common input line. An output transmission line connects an output of the remote cascode amplifier to the common output line. Amplified outputs of the adjacent cascode amplifiers and amplified outputs of the remote cascode amplifier are power combined and summed into a coherent amplified output signal that is output on the output transmission line.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: August 2, 2016
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventor: James J. Komiak
  • Patent number: 9374040
    Abstract: The linearity of a power amplifying module employing an envelope tracking scheme is improved. The power amplifying module includes a first bipolar transistor having a base to which a first radio frequency signal is input and an emitter grounded, and a second bipolar transistor having a base to which a first constant voltage is applied, a collector to which a first power supply voltage is applied, the first power supply voltage adapted to vary in accordance with an amplitude of the first radio frequency signal, and an emitter connected to a collector of the first bipolar transistor. The second bipolar transistor is configured to output a first amplified signal, obtained by amplifying the first radio frequency signal, from the collector of the second bipolar transistor.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: June 21, 2016
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Toshiki Matsui