Abstract: Circuits and methods for improving IC yield during automated test equipment (ATE) calibration of circuit designs which require IDD calibration and use a closed feedback bias circuit, such as amplifier circuits. The circuit designs include bias branch/active circuit architectures where the active circuit includes one or more active devices. An example first embodiment uses an on-chip calibration switch between the on-chip grounds of a bias network and an active circuit comprising an amplifier. During calibration of the active circuit by the ATE, the calibration switch is closed, and after completion of calibration, the calibration switch is opened. An example second embodiment utilizes an active on-chip feedback loop calibration circuit to equalize voltages between the on-chip grounds of a bias network and an active circuit comprising an amplifier during calibration of the active circuit.

Abstract: A modeling circuit of a field effect transistor includes a first field effect transistor, a first bipolar transistor, a second bipolar transistor and a substrate resistor. The first bipolar transistor has a collector electrode connected to a first node corresponding to a first electrode of the first field effect transistor, an emitter electrode connected to a second node corresponding to a second electrode of the first field effect transistor, and a base electrode. The second bipolar transistor has a collector electrode connected to the second node, an emitter electrode connected to the first node, and a base electrode connected to the base electrode of the first bipolar transistor. The substrate resistor is connected between the base electrodes of the first and second bipolar transistors and a first surface of a semiconductor substrate on which the first field effect transistor is formed.

Abstract: An amplifier device includes a regulator circuit, a first voltage converting circuit, a first control circuit, and an amplifier circuit. The regulator circuit is configured to output a first driving voltage. The first voltage converting circuit is coupled to the regulator circuit, and is configured to output one of the first driving voltage and at least one first voltages related to the first driving voltage, as a first operating voltage. The first control circuit is coupled to the first voltage converting circuit through a first node, and is configured to receive the first operating voltage and generate a first operating signal according to the first operating voltage and a first control signal. The amplifier circuit is coupled to the first control circuit and the regulator circuit, and is configured to receive the first driving voltage, and is controlled by the first operating signal to generate an output voltage.

Abstract: High accuracy current sense circuitry for power switching devices comprising GaN power transistors provides for current feedback functions, e.g. current loop control, over-current protection (OCP) and short-circuit protection (SCP). The current sense circuitry comprises a current mirror sense GaN transistor (Sense_GaN) and a power GaN transistor (Power_GaN) and a sampling circuit. The sampling circuit comprises first and second stage operational amplifiers to provide fast response and improved current sense accuracy, e.g. better than 1%, over a range of junction temperatures Tj. The Sense_GaN, Power_GaN and first stage operational amplifier have a common ground referenced to a Kelvin Source of the Power_GaN, so that the Sense_GaN and Power_GaN operate with the same gate-to-source voltage Vgs, to provide an accurate current ratio. Applications include current sensing for switching mode power supplies that need high speed and lossless current sense for current protection and feedback.

Abstract: In some embodiments, a power amplification system can comprise a current source, an input switch configured to alternatively feed current from the current source to a high-power circuit path and a low-power circuit path, and a band switch including a switch arm for switching between a plurality of bands. Each of the high-power circuit path and the low-power circuit path can be connected to the switch arm.

Abstract: Compact low noise amplifiers that have wide-band coverage while meeting necessary input matching and output matching characteristics. Embodiments include a wide-band, two-stage LNA with minimum degradation in performance compared to multiple narrow-band, single-stage LNAs. A generalized embodiment includes a first amplifier stage having a terminal coupled to a mutually coupled inductor circuit and to a second amplifier stage. The second amplifier stage includes a terminal coupled to the mutually coupled inductor circuit. The mutually coupled inductor circuit comprises electromagnetically coupled inductors L1, L2. Second terminals of the first and second amplifier stages are coupled to respective degeneration inductors. The electromagnetically coupled inductors L1, L2 of the inductor circuit substantially increase the output bandwidth of the LNA with minimum degradation in performance.

Abstract: A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes.

Abstract: Methods and apparatuses for controlling gain of a single stage cascode FET amplifier are presented. According to one aspect, a series-connected resistor and capacitor is coupled to a gate of a cascode FET transistor of the amplifier, the capacitor providing a short at frequencies of operation of the amplifier. According to another aspect, values of the resistor can be used to control gain of the amplifier. According to yet another aspect, the resistor is a variable resistor whose value can be controlled/adjusted to provide different gains of the amplifier according to a linear function of the resistor value. An input matching network coupled to an input of the amplifier can be used to compensate for different noise figure degradations from different values of the resistor.

Abstract: Embodiments described herein present a new LDO design that eliminates the need for the sleep bias circuitry included in other systems. Further, the new LDO design can be biased with a small fraction of the operating current enabling the LDO to wake up substantially faster than previous LDO designs that include separate sleep circuitry. In some cases, the LDO can instantly (or faster than other LDOs) transition from a sleep mode to an operating mode enabling improved operation compared to prior LDOs. Furthermore, the new LDO design maintains a non-breakdown voltage across the transistors reducing the need to enter sleep mode to prevent transistors of the LDO from entering a breakdown region.

Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

Abstract: Methods and circuital arrangements for turning OFF branches of a multi-branch cascode amplifier are presented. First and second switching arrangements coupled to a branch allow turning OFF the branch while protecting transistors of the branch from a supply voltage that may be greater than a tolerable voltage of the transistors. The first switching arrangement includes a transistor-based switch that is in series connection with the transistors of the branch. The first switching arrangement drops the supply voltage during the OFF state of the branch and provides a conduction path for a current through the branch during the ON state of the branch. A resistor and a shunting switch are coupled to a gate of the transistor-based switch to reduce parasitic coupling effects of the transistor-based switch upon an RF signal coupled to the branch during the ON state and OFF state of the branch.

Abstract: A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs). Cascode circuits, each having a “common source” configured input FET and a “common gate” configured output FET, serve as the LNAs. An amplifier-branch control switch, configured to withstand relatively high voltage differentials by means of a relatively thick gate oxide layer and coupled between a terminal of the output FET and a power supply, controls the ON and OFF state of each LNA while enabling use of a relatively thin gate oxide layer for the output FETs, thus improving LNA performance. Some embodiments may include a split cascode amplifier and/or a power amplifier.

Abstract: Mechanisms for evaluating amplitude for current pulses provided to a transimpedance amplifier (TIA) for current levels beyond the linear range of the TIA where clipping circuit(s) may limit the input voltage of the TIA are disclosed. In one aspect, an example TIA arrangement includes a clipping arrangement that includes multiple clipping circuits. Each clipping circuit can be biased by different bias voltages such that the different clipping circuits are activated at different input current amplitudes. Different clipping circuits can have different impedances, which can result in different recovery time characteristics. With the multiple clipping circuits in clipping arrangements discussed herein, a saturated dynamic range of a TIA can be divided into sub-regions and different pulse widening characteristics for each region may be defined, which may enable determination of amplitude for current pulses provided to the TIA even for current levels beyond the linear range of the TIA.

Abstract: Amplifiers, amplification circuits, and phase shifters, for example, for flexibly adjusting an output phase to thereby meet a requirement of a constant phase on a link in a communications field, are provided. In one aspect, an amplifier includes first, second, and third MOS transistors. The first MOS transistor includes a gate separately coupled to a signal input end and a bias voltage input end, a source coupled to a power supply, and a drain separately coupled to sources of the second and third MOS transistors. A drain of the third MOS transistor is coupled to a ground, and a drain of the second MOS transistor is coupled to a signal output end. The bias voltage input end is configured to receive a bias voltage to adjust a phase difference between an input signal at the signal input end and an output signal at the signal output end.

Abstract: In a distributed amplifier, a plurality of cascode amplifiers connected in parallel between an input side transmission line and an output side transmission line are provided, a transmission line is connected to an input terminal of an output transistor of each of the amplifiers, and a bias potential is applied from a bias circuit to the input terminal of the output transistor via the transmission line.

Abstract: A configurable serial link interface circuit includes a first transceiver for coupling to a first serial link. The first transceiver includes a first transmit circuit to selectively drive first transmit data along the first serial link and a first receive circuit. The first receive circuit selectively receives first receive data along the first serial link. The interface includes a second transceiver for coupling to a second serial link. The second transceiver includes a second transmit circuit to selectively drive second transmit data along the second serial link, a second receive circuit to selectively receive second receive data along the second serial link, and control circuitry to control the selectivity of the first transmit circuit, the second transmit circuit, the first receive circuit and the second receive circuit. For a first mode of operation, the control circuitry configures the first and second transceivers to define a dual-duplex architecture.

Abstract: A power amplifier circuit includes first and second bias circuits configured to provide first and second biases, respectively, a first transistor having an emitter connected to a reference potential, a base configured to receive the first bias via a first resistor and receive a radio-frequency input signal via a first capacitor, and a collector configured to output an amplified radio-frequency signal, a second transistor having a base connected to the reference potential via a second capacitor and configured to receive the second bias via a second resistor, an emitter configured to receive the radio-frequency signal, and a collector connected to a power supply potential via a third inductor and configured to output a radio-frequency output signal, and an impedance circuit having a first end connected to an output section of the second bias circuit and configured to apply an alternating-current signal to a path extending from the second bias circuit.

Abstract: A digitally modulated polar power amplifier uses a thin-oxide amplifying transistor with a protection diode. The polar power includes a driver amplifier in a driver stage that can receive a phase-modulated signal with a constant envelope and amplify the signal for the output stage, which includes only a single thin-oxide transistor, leading to improved efficiency over systems that require a thick-oxide transistor. A protection diode can be added between the output of the polar power amplifier and the supply voltage to limit the output to the sum of the supply voltage plus the forward voltage of the diode. Amplitude modulation can be achieved through dynamically turning on and off the digital power amplifier via an amplitude control word (acw) input signal.

Abstract: The present invention relates to a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. In particular, the present invention relates to a solid state device based on a complementary pair of n-type and p-type current field-effect transistors, each of which has two control ports, namely a low impedance port and gate control port, while a conventional solid state device has one control port, namely gate control port. This novel solid state device provides various improvement over the conventional devices.

Abstract: The measurement method includes operations of applying a first gate bias voltage to a gate terminal of a first transistor that is included in a radio frequency (RF) power amplifier during a direct current (DC) measurement period, wherein the first transistor operates in a linear operation mode during the DC measurement period; measuring a first drain-source voltage of the first transistor and a current flowing through the first transistor via a connection node during the DC measurement period; applying a second gate bias voltage and a drain bias voltage to a gate terminal and a drain terminal of a second transistor that is electrically connected to the first transistor via the connection node; and measuring a DC value of the second transistor via the connection node during the DC measurement period.

Abstract: A radio-frequency module includes an integrated circuit (IC) device and an external inductor provided outside the IC device. The IC device includes a plurality of low-noise amplifiers, one or more inductors, and a switching circuit. The plurality of low-noise amplifiers includes a plurality of transistors in one to one correspondence. The one or more inductors are coupled to one or more of the plurality of transistors. Each inductor is coupled to the emitter or source of a corresponding one of the plurality of transistors. The switching circuit is coupled between the emitter or source of each of the plurality of transistors and the external inductor. The external inductor is coupled between the switching circuit and ground in series with each of the one or more inductors via the switching circuit.

Abstract: A power amplifier including a cascode output stage, a bias circuit, and a temperature compensation and bias boost circuit. The cascode output stage has an input and an output and includes first and second transistors connected in series. A base of the first transistor is coupled to the input, an emitter of the first transistor is coupled to a reference potential, a collector of the first transistor is coupled to an emitter of the second transistor, and a collector of the second transistor is coupled to a supply voltage and the output. The bias circuit is coupled to the base of the second transistor. The bias boost circuit is coupled to the base of the first transistor, compensates for changes in temperature of the cascode output stage, and increases a bias current provided to the first transistor responsive to an increase in the temperature of the cascode output stage.

Abstract: A power amplifier circuit includes a lower-stage transistor having a first power supply voltage supplied to a first terminal, a second terminal connected to ground, and a first signal supplied to a third terminal; an upper-stage transistor having a second power supply voltage supplied to a first terminal, a second signal obtained by amplifying the first signal being output from the first terminal, a second terminal connected to the first terminal of the lower-stage transistor via a first capacitor, and a third terminal connected to ground via a ground path; an inductor that connects the second terminal of the upper-stage transistor to ground; and an adjustment circuit that adjusts impedance seen from the third terminal of the upper-stage transistor. The adjustment circuit includes a second capacitor and at least one resistance element connected in series with the ground path between the third terminal of the upper-stage transistor and ground.

Abstract: An amplifier includes amplifier circuits connected in series between a ground and a power supply, each amplifier circuit includes: a transistor; and a first capacitance, one end of which is connected to a drain of the transistor, a first amplifier circuit connected closest to the power supply includes a load connected between the drain of the transistor and the power supply, each of the amplifier circuits except for the first amplifier circuit includes a load connected between the drain of the transistor of an own amplifier circuit and a source of the transistor of an amplifier circuit adjacent to the own amplifier circuit, each of the amplifier circuits except for an amplifier circuit connected farthest from the power supply includes a second capacitance connected between the source of the transistor and the ground, and the second capacitance has a capacitance value larger than a capacitance value of the first capacitance.

Abstract: An amplifier circuit (1) includes a FET (10) having a source terminal (S1), a drain terminal (D1), and a gate terminal (G1), a FET (20) having a source terminal (S2), a drain terminal (D2), and a gate terminal (G2) and coupled in parallel with the FET (10), a FET (30) having a source terminal (S3) coupled to the drain terminals (D1 and D2), a drain terminal (D3), and a gate terminal (G3) and cascoded with the FETs (10 and 20), and feedback circuits (21 and 22) configured to feed back to the gate terminal (G2) a high frequency signal outputted from the source terminal (S2) or the drain terminal (D2).

Abstract: A receiver topology for supporting various combinations of interband carrier aggregation (CA) signals, intraband non-contiguous CA and non-CA signals having different combinations of signals aggregated therein.

Abstract: A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes.

Abstract: Systems, methods, and apparatuses for improving reliability and/or reducing the likelihood of breakdown of an amplifier or a component thereof. A system can include a sensing circuit electrically coupled to a transistor of the amplifier and configured to sense an AC voltage associated with the transistor. A protection circuit can be electrically coupled to the sensing circuit and the amplifier and can be configured to supply a DC voltage to the transistor of the amplifier based on the AC voltage sensed by the sensing circuit.

Abstract: An amplifier circuit that amplifies a high frequency signal includes a transistor that is an example of an amplifier integrated into an IC device and an inductor connected to an input terminal of the transistor, and the inductor includes a first inductor integrated into the IC device and a second inductor connected in series to the first inductor and included in a first component different from the IC device.

Abstract: A power amplifier circuit includes a first transistor, a capacitor, and a second transistor. The first transistor has an emitter electrically connected to a reference potential, a base, and a collector electrically connected to a first power supply potential. A first end of the capacitor is electrically connected to the collector of the first transistor. The second transistor has an emitter electrically connected to a second end of the capacitor and electrically connected to the reference potential, a base, and a collector electrically connected to the first power supply potential. An RF output signal obtained by amplifying the RF input signal is output from the collector of the second transistor. A second bias circuit includes a third transistor having a collector electrically connected to a second power supply potential, a base, and an emitter from which the second bias current or voltage is output.

Abstract: A power amplifier circuitry (100) comprises: a transistor stack (110) comprising at least two stacked transistor units (112A, 112B, 112C) for amplifying input signals; wherein each stacked transistor unit (112A, 112B, 112C) comprises a plurality of controllable segments (120-1 to 120-N, 130-1 to 130-N, 140-1 to 140-N), each comprising a segment transistor (122, 132, 142), wherein source terminals (123, 133, 143) within each transistor unit are connected, drain terminals (125, 135, 145) within each transistor unit are connected and gate terminals (124, 134, 144) within each transistor unit are connected, wherein each segment transistor (122, 132, 142) further comprises a back gate terminal (126, 136, 146) for setting a body bias, wherein at least two of the segment transistors (122, 132, 142) within each transistor unit have independently connected back gate terminals (126, 136, 146); and a control unit (190) configured to control the body bias for selecting an amplifier class of each of the controllable segme

Abstract: An amplifier circuit is a cascade amplifier circuit that includes a first transistor circuit including a signal input portion to which a signal is input from outside; a load circuit connected between the first transistor circuit and a power-supply line; and a second transistor cascode-connected between the load circuit and the first transistor circuit. The first transistor circuit is constituted by a plurality of transistors connected in parallel, and a bias circuit is provided that selectively supplies a bias voltage to the plurality of transistors.

Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.

Abstract: Methods and devices to fabricate low-cost wideband LNAs that are tunable to multiple frequency bands. Decoupling capacitors are used as part of a tuning circuit implemented at the LNA input. The capacitors are switchably selectable to also tune a signal into desired frequency bands.

Abstract: A power amplifier may comprise: an element for amplifying an electrical signal received through an input terminal, and outputting the amplified electrical signal through an output terminal; a first impedance adjustment circuit connected to the input terminal of the element and adjusting impedance with respect to a frequency of a fundamental component at the input terminal; a second impedance adjustment circuit connected to the input terminal of the element and adjusting impedance with respect to a frequency of a multiplied harmonic component at the input terminal; a third impedance adjustment circuit connected to the output terminal of the element and adjusting impedance with respect to the frequency of the fundamental component at the output terminal; a fourth impedance adjustment circuit connected to the output terminal of the element and adjusting impedance with respect to the frequency of the multiplied harmonic component at the output terminal; a first frequency separation circuit which prevents an imped

Abstract: When a potential difference V1 between a source terminal of an E-type FET (11) and a source terminal of a D-type FET (12) is larger than a threshold voltage Vth, a protection circuit (13) starts an operation to reduce the potential difference V1 such that the potential difference V1 is smaller than the threshold voltage Vth. This makes it possible to prevent destruction of the E-type FET (11) even when a signal to be amplified is an RF signal.

Abstract: A biasing circuit with high current drive capability for fast settling of a biasing voltage to a stacked cascode amplifier is presented. According to a first aspect, the biasing circuit uses transistors matched with transistors of the cascode amplifier to generate a boost current during a transition phase that changes the biasing voltage by charging or discharging a capacitor. The boost current is activated during the transition phase and deactivated when a steady-state condition is reached. According to a second aspect, the biasing circuit uses an operational amplifier in a feedback loop that forces a source node of a cascode transistor of a reference circuit, that is a scaled down replica version of the cascode amplifier, to be at a reference voltage. The high gain and high current capability of the operational amplifier, provided by isolating a high frequency signal processed by the cascode amplifier from the reference circuit, allow for a quick settling of the biasing voltage.

Abstract: Power amplifiers and related methods are disclosed having configurable switched mode operation in a high-power mode of operation and a low-power mode of operation. The power amplifiers have a first cascode amplifier coupled to receive a positive differential input and a second cascode amplifier coupled to receive a negative differential input. The first and second cascode amplifiers include output stages and first/second input stages. The first input stages and the second input stages are enabled in a high-power mode of operation. The first input stages are disabled and the second input stages are enabled during a low-power mode of operation. For further embodiments, a switchable clamp operates in the low-power mode to clamp a voltage output for the second input stages. For further embodiments, the output stages are provided a variable voltage bias or are coupled to tunable capacitances that are varied between the low-power and high-power modes.

Abstract: A power amplifier circuit includes a first transistor, wherein a radio frequency signal is inputted to a base or gate of the first transistor; a second transistor having an emitter connected to a collector or drain of the first transistor, wherein a first voltage is supplied to a collector of the second transistor, and a first amplified signal obtained by amplifying the radio frequency signal is outputted from the collector of the second transistor; and a third transistor configured to supply a bias voltage to a base of the second transistor. A second voltage is supplied to a collector or drain of the third transistor, a third voltage corresponding to the first voltage is supplied to a base or gate of the third transistor, and the bias voltage, which corresponds to the third voltage, is supplied from an emitter or source of the third transistor.

Abstract: A self-biased amplifier includes a capacitor, a bias generation circuit and a common source amplifier. The capacitor is used to receive an input voltage and output an alternating component of the input voltage. The bias generation circuit is coupled to the capacitor, and used to generate a first bias voltage according to the alternating component. The common source amplifier is coupled to the bias generation circuit, and used to generate an amplified voltage according to the first bias voltage.

Abstract: Described herein are variable-gain amplifier configurations that include a multi-input gain stage, a cascode buffer, and a bypass block. Degeneration switching blocks can be used for the entire multi-input gain stage or for individual input nodes of the multi-input gain stage. This advantageously reduces or eliminates performance penalties in one or more gain modes. The variable impedances can be configured to improve linearity of the amplification process in targeted gain modes. The variable gain amplifier can be configured to provide a low-loss bypass mode in a low gain mode to improve signal quality.

Abstract: An amplifier including a signal input terminal, at least one signal output terminal, a first and a second cascode amplifier circuits, a capacitor and a loading circuit. The signal input terminal receives an input signal. The first cascode amplifier circuit includes a first and a second input terminals and a first and a second output terminals. The first input terminal coupled to the signal input terminal receives the input signal. The second cascode amplifier circuit includes a third and a fourth input terminals and a third output terminal. The third input terminal is coupled to the first output terminal, and the third output terminal is coupled to the second input terminal. Two terminals of the capacitor are coupled to the fourth input terminal and the first output terminal respectively. A terminal of the loading circuit is coupled to the third output terminal, and another terminal of the loading circuit is coupled to the second output terminal.

Abstract: A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes.

Abstract: A monolithic integrated circuit (IC), and method of manufacturing same, that includes all RF front end or transceiver elements for a portable communication device, including a power amplifier (PA), a matching, coupling and filtering network, and an antenna switch to couple the conditioned PA signal to an antenna. An output signal sensor senses at least a voltage amplitude of the signal switched by the antenna switch, and signals a PA control circuit to limit PA output power in response to excessive values of sensed output. Stacks of multiple FETs in series to operate as a switching device may be used for implementation of the RF front end, and the method and apparatus of such stacks are claimed as subcombinations. An iClass PA architecture is described that dissipatively terminates unwanted harmonics of the PA output signal.

Abstract: Described herein are variable gain amplifiers that selectively provide variable or tailored impedances at a degeneration block and/or feedback block depending at least in part on a gain mode of the variable gain amplifier. This advantageously reduces or eliminates performance penalties in one or more gain modes. The variable impedances can be configured to improve linearity of the amplification process in targeted gain modes. The variable gain amplifier can be configured to provide a low-loss bypass mode in a low gain mode to improve signal quality. The degeneration block can be selectively isolated from a reference potential node to improve performance.

Abstract: In an exemplary structure, a transformer has a primary side and a secondary side. Output from the primary side is coupled to the secondary side. A first power supply is connected to a center tap of the primary side of the transformer. An oscillator includes a first transistor and a second transistor. The front-gate of the first transistor is connected to the drain of the second transistor and the primary side of the transformer. The front-gate of the second transistor is connected to the drain of the first transistor and the primary side of the transformer. A third transistor is connected to the first transistor and a fourth transistor is connected to the second transistor. The third and fourth transistors inject a desired frequency to the oscillator. A voltage source is connected to the back-gate of the first transistor and the back-gate of the second transistor.

Abstract: Methods and apparatus for providing high efficiency power amplifiers for both high and low output power levels are disclosed. An example apparatus includes a first amplifier to amplify a signal from a host device; and transmit the amplified signal to an antenna; a second amplifier to amplify the signal from the host device; and transmit the amplified signal to the antenna; and first, second, and third switches to: when the first and second switches are closed and the third switch is open, couple the first amplifier to the second amplifier in a parallel structure; and when the first and second switches are open and the third switch is closed, couple the first amplifier to the second amplifier in a stacked structure.

Abstract: A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes.

Abstract: In accordance with an embodiment, a circuit includes: a replica input transistor, a first replica cascode transistor, an active current source, and an active cascode biasing circuit. The active current source is configured to set a current flowing through the first replica cascode transistor and the replica input transistor to a predetermined value by adjusting a voltage of a control node of the replica input transistor; and an active cascode biasing circuit including a first output coupled to the control node of the first replica cascode transistor, and the active cascode biasing circuit configured to set a drain voltage of the replica input transistor to a predetermined voltage by adjusting a voltage of the control node of the first replica cascode transistor.

Abstract: Design of ultra broadband transimpedance amplifiers (TIA) for optical fiber communications is disclosed. In one embodiment, a TIA comprises a gm-boosted dual-feedback common-base stage, a level shifter and an RC-degenerated common-emitter stage, and a first emitter-follower stage, wherein the first emitter follower stage is inductively degenerated. An output of the TIA is buffered using a second emitter-follower stage.