Abstract: A multi-mode low noise amplifier (LNA) with transformer source degeneration is described. In an exemplary design, the multi-mode LNA includes first, second, and third transistors and first and second inductors. The first transistor has its source coupled to the first inductor, amplifies an input signal, and provides a first amplified signal in a first mode. The second transistor has its source coupled to the second inductor, amplifies the input signal, and provides a second amplified signal in a second mode. The third transistor has its source coupled to the second inductor. The first and third transistors receive the input signal and conduct current through the first and second inductors, respectively, in a third mode. The first transistor observes source degeneration from a transformer formed by the first and second inductors, amplifies the input signal, and provides a third amplified signal in the third mode.

Abstract: Provided is controlled-gain wideband feedback low-noise amplifier. The controlled-gain wideband feedback low-noise amplifier includes: a feedback amplifier configured to isolate an input signal and an output signal obtained by amplifying the input signal, feed back the output signal to the input signal to amplify wideband input signals, resonate a low-frequency band signal among the wideband input signals to amplify the low-frequency band signal among the wideband input signals, and be switched in accordance with a control signal to control an amplification gain of the low-frequency band signal among the wideband input signals; and a cascode amplifier configured to amplify a high-frequency band signal among the wideband signals inputted from the feedback amplifier, and be switched in accordance with a control signal to control an amplification gain of the high-frequency band signal among the wideband signals.

Abstract: A broadband high output current output stage includes at least one first differential pair for enhancing the bandwidth. A second differential pair is further disposed in the circuit. The second differential pair is coupled to one of the first differential pair, such that a large output voltage swing is distributed to all transistors to avoid breakdowns thereof. A feedback unit is connected between each bias unit and the first differential pair. The first compensation unit compensates the electric characteristic of the high-frequency zero of the feedback unit and the bias unit, thereby broadening the linear bandwidth of the frequency response. The second compensation units are disposed between the first differential pairs. Each second compensation unit compensates the high-frequency zero of the node where each two first differential pairs are cascaded, thereby further broadening the linear bandwidth of the frequency response.

Abstract: According to one embodiment, a radio frequency receiver includes a quadrature mixer for converting radio frequency signals to baseband signals or intermediate frequency signals. The quadrature mixer includes an in-phase passive mixer and a quadrature-phase passive mixer. Each passive mixer includes a mixer core having a plurality of mixer input switch transistors and a plurality of output switch transistors connected to the mixer input switch transistors. Clock circuitry generates a first set of clock signals and a second set of clock signals. The first set of clock signals has a frequency twice that of the second set of clock signals. The first set of clock signals is arranged to drive the mixer input switch transistors and the second set of clock signals is arranged to drive the output switch transistors.

Abstract: One embodiment of the present invention relates to a method for transistor matching. The power transmitter comprises a first, second, and third amplification path. The paths are selectively activated and deactivated to output a received signal with high efficiency and linearity. The first amplification path is configured to receive a first signal and output a first amplified signal to a first port of a output power combiner when activated and provide an impedance that results in a high reflection factor when deactivated. The second amplification path is configured to receive a second signal with 90° phase shift with respect to the first signal and output a second amplified signal to a second port of the combiner when activated and provide an impedance that results in a high reflection factor when deactivated.

Abstract: A cascode amplification unit includes a plurality of cascode amplifiers connected in parallel. Each of the cascode amplifiers has two transistors. A cascode current source unit includes a plurality of cascode current sources connected in parallel. Each of the cascode current sources has two transistors. Both the output end of the cascode amplification unit and the output end of the cascode current source unit are connected to a load circuit. The control circuit turns on and off each cascode transistor of the cascode amplifier and each cascode transistor of the cascode current source so that an amount of current passing through the load circuit is constant.

Abstract: A Radio Frequency (RF) cascode power amplifier operates with differing battery supply voltages. A transconductance stage has a transistor with an RF signal input at its gate. A cascode stage has at least one cascode transistor, the cascode stage coupled in series with the transconductance stage between a battery voltage node and ground, the cascode stage having an RF signal output at the battery voltage node and at least one bias input to the at least one cascode transistor. Cascode bias feedback circuitry applies fixed bias voltage(s) to the at least one two bias inputs for a low battery voltage and applies feedback bias voltage(s) to the at least two bias inputs for a high battery voltage, the feedback bias voltage(s) based upon a voltage of the battery voltage node. More than two differing battery supply voltages are supported.

Abstract: A folded cascode receiver amplifier with constant gain has inputs coupled to PMOS and NMOS differential transistors pairs with scaled geometries. The transconductance of both PMOS and NMOS transistors is the same whether the common mode input voltage is low or high. In a first version the transconductance of both PMOS and NMOS differential transistor pairs is reduced when the common mode input voltage is at mid-rail. Resistive means between current sources and the sources of the PMOS and NMOS transistor pairs force the current source transistors into the triode region of operation. A second version insures a constant voltage gain through control means which maintain a constant ratio of the transconductance of the output stage transistors versus the PMOS and NMOS differential transistor pairs when active.

Abstract: A system includes an input multi-level channelizer, an output multi-level channelizer, and more than one amplifiers connected between the input and output channelizers. The input and output channelizers cover an operating frequency band. Each level of the input multi-level channelizer comprises a plurality of input channels, which may be bandpass filters, and may be grouped into input sub-channelizers. Each successive level of the input multi-level channelizer is configured to divide the incoming signals into smaller frequency bands. Each level of the output multi-level channelizer comprises a plurality of output channels, which may be bandpass filters, and may be grouped into output sub-channelizers. Each successive level of the output multi-level channelizer is configured to combine the incoming signals into larger frequency bands. The signal output from the output multi-level channelizer represents a filtered version of the signal input into the input multi-level channelizer.

Abstract: The present invention relates to a low noise cascode amplifier comprising a first transistor, a second transistor, a third transistor, a first inductor, and a second inductor. Furthermore, the first transistor can connect with the second transistor via the first inductor, and the second transistor can connect with the third transistor via the second inductor; thereby, a cascode device can be formed. The inductor and the parasitic capacitances can resonate at high frequency, so that the noise figure of the cascode amplifier can be reduced.

Abstract: A low noise amplifier includes an input stage. The input stage includes a first device configured to receive an input signal. A second device is connected to the first device. The second device has a predetermined input impedance. The input stage is configured so that a change in the input signal to the first device causes a linearly proportional change in a conductance of the first device. A voltage at a junction between the first device and the second device remains substantially constant due to the predetermined input impedance of the second device.

Abstract: Techniques for designing a low-noise amplifier (LNA) for operation over a wide range of input power levels. In an exemplary embodiment, a first gain path is provided in parallel with a second gain path. The first gain path includes a differential cascode amplifier with inductor source degeneration. The second gain path includes a differential cascode amplifier without inductor source degeneration. The cascode transistors of the gain paths may be selectively biased to enable or disable the first and/or second gain path. By selectively biasing the cascode transistors and input transistors, various combinations of the first and second gain paths may be selected to provide an optimized gain configuration for any input power level.

Abstract: A switched capacitor circuit utilizes a pair of serially connected differential amplifiers that have plus inputs, minus inputs, plus outputs, and minus outputs. Feedback to the plus/minus inputs is in a first configuration relative to the output of the pair of differential amplifiers in a sampling mode and a second configuration in a hold mode. Similarly, the plus/minus inputs relative to the plus/minus outputs of the serially connected differential amplifiers is reversed between the sampling and hold modes.

Abstract: A cascode amplifier with protection circuitry is described. In one exemplary design, the amplifier includes multiple branches coupled in parallel, with at least one branch being switchable between “on” and “off” states. Each switchable branch includes a gain transistor coupled to a cascode transistor. The gain transistor amplifies an input signal and provides an amplified signal in the on state and does not amplify the input signal in the off state. The cascode transistor buffers the amplified signal and provides an output signal in the on state. The output signal swing may be split between the gain transistor and the cascode transistor in both the on and off states with the protection circuitry. Each transistor may then observe a fraction of the voltage swing. The voltage splitting in the off state may be achieved by floating the gain transistor and shorting the gate and source of the cascode transistor.

Abstract: Embodiments of a high-linearity low-noise amplifier (LNA) are generally described herein. Other embodiments may be described and claimed. In some embodiments, an RF input signal may be amplified with a cascode amplifier. The cascode amplifier may include integrated notch filters to attenuate undesired signals. The cascode amplifier may operate from a large power supply when blockers are present to avoid voltage swing compression at its output. The cascode amplifier may be biased and designed to operate in a class AB mode to produce linear output current to avoid current compression or excessive current expansion.

Abstract: An output-impedance in a power amplifier is provided. A first transistor QBUF of a buffer stage is connected to a first side of a resistor RF and a second transistor QAMP to a second opposite side of the resistor RF. The first transistor feeds a current IRF to the second resistor QAMP. The current IRF at the second transistor is copied and multiplied by a factor (n) to form an output current IOUT, as (1+n)*IRF. The current IRF is fed back to the first transistor and the output current IOUT is fed to a load resistor R.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: Multiple-Input-Single-Output (MISO) amplification and associated VPA control algorithms are provided herein. According to embodiments of the present invention, MISO amplifiers driven by VPA control algorithms outperform conventional outphasing amplifiers, including cascades of separate branch amplifiers using conventional power combiner technologies. MISO amplifiers can be operated at enhanced efficiencies over the entire output power dynamic range by blending the control of the power source, source impedances, bias levels, outphasing, and branch amplitudes. These blending constituents are combined to provide an optimized transfer characteristic function.

Abstract: Embodiments include but are not limited to apparatuses and systems including a unit cell having a source electrode, a gate electrode to receive an input radio frequency (RF) signal, and a drain electrode to output an amplified RF signal. A field plate may be coupled with the source electrode, and a feedback resistor may be coupled between the field plate and the source electrode.

Abstract: A rail-to-rail Miller compensation method without feed forward path includes forming a first compensation branch including a first amplifier, wherein an input of the first amplifier is electrically connected with an output of a second stage gain amplifier, the second stage gain amplifier is electrically connected the first stage gain amplifier in series forming an operational amplifier; and forming a second compensation branch including a second amplifier, wherein a dual relation is provided between an input stage of the first amplifier and that of the second amplifier, namely, if the input stage of the first amplifier is N-type, the input stage of the second amplifier is P-type, and vice versa. The present invention is capable of achieving the rail-to-rail output range without affecting the system stability. The N-type and P-type inputs are simultaneously applied to the input of the amplifier of the compensation branches.

Abstract: Systems and methods are provided for positive and negative feedback of cascode transistors for a power amplifier. The systems and methods may include a first cascode stage comprising a first common-source device and a first common-gate device; a second cascode stage comprising a second common-source device and a second common-gate device; a first degenerative element or block provided for the first common-source device; a second degenerative element or block provided for the second common-source device; a first positive feedback block or element that connects a first gate of the first common-source device with a second drain of the second common-source device; and a second positive feedback block or element that connects a second gate of the second common-source device with a first drain of the first common-source device.

Abstract: A novel RF power amplifier integrated circuit (PA IC), unit cell, and method for amplifying RF signals are disclosed. One embodiment of a PA IC includes at least two linear arrays comprising transistor device units, and at least one linear array comprising capacitors. The transistor device units include source nodes that are jointly coupled to a source bus, and selected gate nodes that are jointly coupled to a gate bus. First electrodes of the capacitors are also jointly coupled to the source bus, and second electrodes of the capacitors are jointly coupled to the gate bus. Each linear array comprising capacitors is disposed between at least two linear arrays comprising transistor device units. In one embodiment, the PA IC includes unit cells. In some embodiments, each unit cell comprises two transistor device units and one or more capacitors. The capacitors are disposed between the transistor device units.

Abstract: An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero.

Abstract: There is provided a wide-band amplifier circuit with improved gain flatness. The wide-band amplifier circuit includes a first resonant load unit connected to an operating power terminal, providing a preset first load, and forming a preset first resonant point, a second resonant load unit connected to the operating power terminal, providing a preset second load, and forming a second resonant point set to a frequency different from the first resonant point; a first amplification unit receiving operating power via the first load of the first resonant load unit, having an amplification band characteristic determined according to the first resonant point of the first resonant load unit, and amplifying an input signal; and a second amplification unit receiving operating power via the second load, having an amplification band characteristic determined according to the second resonant point, and amplifying an input signal from the first amplification unit.

Abstract: An amplifier including a first transistor including a gate coupled to an input terminal and a grounded source; a load resistor provided between a drain of the first transistor and a power supply; an output terminal coupled to a node between the drain of the first transistor and the load resistor; a feedback path coupled to the input terminal and the output terminal and including a resistor and a capacitor; a bias voltage generator applying a gate bias voltage to the gate of the first transistor in response to an enable signal; a supply resistor provided between an output node for the gate bias voltage of the bias voltage generator and the gate of the first transistor; and an enable switch lowering a resistance value between the output node for the gate bias voltage and a node in the feedback path.

Abstract: Linearization circuits of the invention are used in conjunction with power amplification circuits that comprise a power amplifier core. Exemplary linearization circuits comprise a replica of the power amplifier core. In operation, the linearization produces an envelope signal from an RF signal. The envelope signal is used to control the replica to produce an analog output signal which represents the inverse of the AM to AM distortion of the power amplifier core. The linearization circuit then biases the RF signal with the inverted non-linear signal of the replica to control the power amplifier core. The power amplifier core and the replica thereof can be defined on the same semiconductor die so both respond to process variables similarly.

Abstract: A system for a power transmitter may be provided. The system may include a first amplifier stage having at least a first transistor and a second transistor that are connected in a first cascode configuration; a second amplifier stage having at least a third transistor and a fourth transistor that are connected in a second cascode configuration, where the first transistor receives a system input of the power transmitter, where the second transistor is connected to the third transistor, and where the fourth transistor provides a system output of the power transmitter; and a feedback network that connects a first gate or base of the fourth transistor with a second gate or base of the second transistor.

Abstract: A source follower circuit is disclosed with an added amplifier that extends the low input voltage linear range while providing a lower output impedance. The drain of the source follower MOSFET is coupled to a gain stage that drives a second MOSFET (or other type transistor) with its drain coupled to the follower output. High impedance current sources bias the circuitry, and the difference amplifier has a reference voltage at one input. The difference amplifier with the reference voltage provides a feedback mechanism that maintain adequate drain to source voltage across the follower MOSFET to enhance the low input voltage linearity along with reducing the follower output resistance.

Abstract: The present invention discloses a power amplifier, comprising: a first transistor having a gate receiving an input signal; a second transistor coupled to the first transistor in a cascode configuration, in which a source of the second transistor is coupled to a drain of the first transistor, and a drain of the second transistor outputs an amplified signal; and a dynamic biasing circuit having two input terminals, one of which receiving the input signal, and the other one coupled to the drain of the first transistor, and an output terminal being coupled to a gate of the second transistor, thereby modulating the voltage at the drain of the first transistor.

Abstract: A composite device includes a depletion mode FET coupled to a bipolar transistor. The FET includes gate, drain and source terminals, and the bipolar transistor includes base, collector and emitter terminals. The collector terminal of the bipolar transistor and the source terminal of the depletion mode FET are directly connected to each other. Additionally, the emitter terminal of the bipolar transistor and the gate terminal of the depletion mode FET are directly connected to each other. The voltage between the collector and emitter terminals, VCE, is configured to bias the depletion mode FET. The VCE voltage has a value that is equal and opposite to a voltage VGS between the gate and source terminals of the depletion mode FET.

Abstract: Provided is a signal amplification apparatus with advanced linearization, the signal amplification apparatus including: a driving unit having a structure of a cascode amplifier including a first active element and a second active element and outputting an amplification signal in which an input signal is amplified, to an output terminal; a third active element receiving a signal diverged between the first active element and the second active element while gate and drain terminals of the third active element are shorted; a fourth active element of which gate and drain terminals are connected to a source terminal of the third active element; and a fifth active element of which gate terminal is connected to the drain terminal of the fourth active element, outputting a non-linear signal having an opposite phase to the amplification signal to the output terminal so as to cancel a third-order inter-modulation distortion component included in the input signal.

Abstract: A communications transceiver includes a baseband processor, a receiver section, and a transmitter section that includes a power amplifier. The receiver and transmitter sections communicatively couple to the baseband processor. In a calibration operation, the baseband processor produces a test signal to the transmitter section. Further, the baseband processor causes each of a plurality of power amplifier bias settings to be applied to the power amplifier. For each of the plurality of power amplifier bias settings, the power amplifier produces an amplified test signal, the receiver section couples back a portion of the amplified test signal to the baseband processor, and the baseband processor produces a characterization of the amplified test signal respective. Based upon a plurality of characterizations of the amplified test signal and respective power amplifier bias settings, the baseband processor determines power amplifier bias control settings.

Abstract: Techniques for improving the linearity of a cascode amplifier. In an exemplary embodiment, an auxiliary common-gate amplifier is provided in parallel with the principal cascode branch. The auxiliary common-gate amplifier samples a cascoded node in the principal cascode branch. The auxiliary common-gate amplifier generates a current which, when combined with the current generated by the principal cascode branch, cancels a distortion component to generate an output current with improved linearity characteristics. In an exemplary embodiment, a phase shifting network couples the cascoded node to the auxiliary common-gate amplifier, and may include, e.g., a capacitor coupled to an inductor.

Abstract: An amplifying device includes a cascode amplifier and a biasing circuit. The cascode amplifier is configured to receive an input signal and to output an amplified output signal corresponding to the input signal. The biasing circuit is configured to bias the cascode amplifier, the biasing circuit including a first current mirror and a second current mirror stacked on the first current mirror. The biasing circuit improves linearity of the cascode amplifier across a wide temperature range.

Abstract: An amplifier stage for generating an amplified output signal from an input signal, a mobile device comprising an audio amplifier, and an amplification method for generating an amplified output signal from an input signal using an amplifier stage are described.

Abstract: An amplifier, which has good linearity and noise performance, includes first, second, third, and fourth transistors and an inductor. The first and second transistors are coupled as a first cascode pair, and the third and fourth transistors are coupled as a second cascode pair. The third transistor has its gate coupled to the source of the second transistor, and the fourth transistor has its drain coupled to the drain of the second transistor. The first transistor provides signal amplification. The second transistor provides load isolation and generates an intermediate signal for the third transistor. The third transistor generates distortion components used to cancel third order distortion component generated by the first transistor. The inductor provides source degeneration for the first transistor and improves distortion cancellation. The sizes of the second and third transistors are selected to reduce gain loss and achieve good linearity for the amplifier.

Abstract: A rail-to-rail Miller compensation method without feed forward path includes forming a first compensation branch including a first amplifier, wherein an input of the first amplifier is electrically connected with an output of a second stage gain amplifier, the second stage gain amplifier is electrically connected the first stage gain amplifier in series forming an operational amplifier; and forming a second compensation branch including a second amplifier, wherein a dual relation is provided between an input stage of the first amplifier and that of the second amplifier, namely, if the input stage of the first amplifier is N-type, the input stage of the second amplifier is P-type, and vice versa. The present invention is capable of achieving the rail-to-rail output range without affecting the system stability. The N-type and P-type inputs are simultaneously applied to the input of the amplifier of the compensation branches.

Abstract: A programmable gain MOS amplifier is disclosed. The programmable gain MOS amplifier is capable of increasing its programmable gain linearly in dB unit by increasing its gain level data linearly. The programmable gain MOS amplifier includes a plurality of gain providers for providing predetermined gains respectively, and a plurality of gain tuners. Each of the plurality of the gain tuners is disposed for adjusting the predetermined gain from the corresponding gain provider. Each of the gain tuners includes a gain enabling module and a gain decreasing module. The gain enabling module allows the corresponding predetermined gain to add to the programmable gain of the MOS amplifier. The gain decreasing module declines the corresponding predetermined gain added to the programmable gain of the MOS amplifier.

Abstract: A controllable amplifier amplifies a radiofrequency input signal on the basis of a control signal. A current path is formed between a supply potential connection and a reference potential connection. The current path includes an amplifier transistor and a cascode transistor, the cascode transistor being connected to the input for supplying the control signal. The output power of the amplifier is controlled using the cascode transistor, as a result of which a low power consumption is achieved in conjunction with good noise properties.

Abstract: A high gain stacked cascade amplifier includes a first amplifying element, a second amplifying element, a current mirror bias element, and a dynamic bias adjustment element. The first and second amplifying elements are coupled in series to form the high gain stacked cascade amplifier configuration. The current mirror bias element provides a bias to the first and second amplifying elements. The dynamic bias adjustment element is coupled to the second amplifying element. The dynamic bias adjustment element is configured to increase a gain compression point of a composite filter, formed by the first and second amplifying elements, in response to a determination that an input signal causes gain compression in the first amplifying element.

Abstract: A converting circuit for converting differential signals to a single-ended signal. The converting circuit comprises a cascode amplifier comprising a first transistor and a second transistor, wherein the first transistor comprises a control terminal, a first terminal, and a second terminal, the control terminal to which one of the differential signals is input, the control terminal being electrically-grounded; and, the second transistor comprises a first terminal and a second terminal, the first terminal of the second transistor being connected to the first terminal, the second terminal of the second transistor from which output signal is outputted, a capacitor for adjusting the phase, the capacitor being connected to the second terminal; and a current source being connected to the second terminal.

Abstract: A power amplifier subsystem that includes a first stage amplifier and a second stage amplifier. A first bias circuit is coupled to the first stage amplifier, and the first bias circuit has a variable impedance that increases with radio frequency (RF) power. A second bias circuit is coupled to the second stage amplifier, and the second bias circuit has impedance relatively fixed with respect to radio frequency (RF) power. According to an embodiment of the invention, the first bias circuit comprises a transistor having a collector current that increases as radio frequency (RF) power increases. The second bias circuit can have a relatively fixed impedance. A method of designing an amplifier subsystem, where transistor size and resistor values are selected to obtain the desired bias and linearity characteristics, or transistor size and resistor values are selected to operate within a selected range, and amplifier performance is adjusted by changing the bias control voltage.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: Complimentary Metal-Oxide-Semiconductor (CMOS) circuits made with core transistors are capable of reliable operation from an IO power supply with voltage that exceeds the reliability limit of the transistors. In embodiments, biasing of an operational amplifier is changed in part to a fixed voltage corresponding to the reliability limit. In embodiments, switched capacitor networks are made with one or more amplifiers and switches including core transistors, but without exposing the core transistors to voltages in excess of their reliability limit. In embodiments, operational transconductance amplifiers (OTAs) include core transistors and operate from IO power supplies. Level shifters for shifting the levels of a power down signal may be used to avoid excessive voltage stress of the OTAs' core transistors during turn-off. Non-level shifting means may be used to clamp output voltages and selected internal voltages of the OTAs, also avoiding excessive voltage stress of the core transistors during turn-off.

Abstract: An amplifier circuit includes three amplifier units connected in series. The first amplifier unit includes an input connector for inputting signals and a first transistor amplifier module connected to the input connector. The second amplifier unit includes a notch-filter circuit, a main filter circuit and a second transistor amplifier module. The notch-filter circuit allows only signals in a predetermined frequency to be transmitted from the first transistor amplifier module to the second transistor amplifier module and amplified. The main filter circuit filters signals in frequencies different from the predetermined frequency. The third amplifier unit includes a third transistor amplifier module and an output connector for outputting amplified signals.

Abstract: A post-distortion method for cascading amplifier stages in a two-stage microwave power amplifier and a dynamic biasing method using back-end processing for correcting nonlinearity in the power amplifier output. A first or driver stage biased in a near-A region with low distortion is cascaded with a second or power stage biased in a near-C region with high efficiency. The amplitude and phase responses of the two stages compensate another to yield a more linear overall gain for the overall power amplifier. The dynamic biasing scheme modulates the source to drain voltages of the transistors used in the amplifier stages based on the harmonics in amplifier output in order to minimize the harmonics and correct non-linearity in the output.

Abstract: A high performance follower device coupled with a slew enhancement circuit includes an amplifier circuit containing a follower device connected to a three-terminal device, whereupon current drawn through the three-terminal device is amplified through a current amplifier and sent to the source terminal of the follower device to stabilize the output voltage when the input signal is changed rapidly or if the output voltage is disturbed by a changing output load. The presence of a cascode device also allows for the bootstrapping of the follower device.

Abstract: A cascoded current-mirror circuit includes a first N channel MOS transistor, a second N channel MOS transistor, a third N channel MOS transistor and a fourth N channel MOS transistor. The first N channel MOS transistor and the second N channel MOS transistor are cascode-connected between a higher voltage source and a lower voltage source. The third N channel MOS transistor and the fourth N channel MOS transistor are cascode-connected between the higher voltage source and the lower voltage source. A drain of the first N channel MOS transistor is connected to gates of the first N channel MOS transistor, the second N channel MOS transistor, the third N channel MOS transistor and the fourth N channel MOS transistor. The threshold voltages of the second N channel MOS transistor and the fourth N channel MOS transistor are larger than those of the first N channel MOS transistor and the third N channel MOS transistor.

Abstract: A low-noise amplifier circuit includes a MOS transistor in a common gate amplifier configuration. A single-ended input is at a source of the MOS transistor. A resonant cavity filter circuit is coupled to a gate of the MOS transistor.

Abstract: Aspects provide for the broadband amplification of RF signals. Other aspects provide for the conversion of single ended input to differential output. Various aspects provide for tuning the response to a particular frequency band. Other aspects provide for various transconductance elements. In several aspects, broadband current to voltage converters and voltage to current converters are presented. Some implementations incorporate a buffer circuit, and various implementations incorporate feedback circuits.