Including Plural Stages Cascaded Patents (Class 330/310)
  • Patent number: 11088664
    Abstract: A signal generator is configured to generate a signal with an amplitude sweep, the signal generator having circuitry comprising: a set of control components, each control component of the set being arranged to be switchably activated in parallel in the circuitry such that an amplitude of the signal has an intrinsic dependence on the number of the control components activated; a shift register controllable by a clock line and comprising a number of bits, each bit of the number of bits controlling activation of a respective control component of the set of control components such that the control components are arranged to be activated or de-activated in a pre-determined order by shifting activation or de-activation bits into the shift register, wherein the shifting is paced by the clock line; and a clock signal generator configured to output a clock signal with a time modulation on the clock line.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: August 10, 2021
    Assignee: IMEC vzw
    Inventors: Wilfried Zomagboguelou, Paul Mateman, Yao-Hong Liu
  • Patent number: 11082008
    Abstract: Aspects of this disclosure relate to an amplification circuit that includes a stacked amplifier and a bias circuit. The stacked amplifier includes at least a first transistor and a second transistor in series with each other. The stacked amplifier is operable in at least a first mode and a second mode. The bias circuit is configured to bias the second transistor to a linear region of operation in the first mode and to bias the second transistor as a switch in the second mode. In certain embodiments, the amplification circuit can be a power amplifier stage configured to receive a supply voltage that has a different voltage level in the first mode than in the second mode.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: August 3, 2021
    Assignee: Skyworks Solutions, Inc.
    Inventor: Yasser Khairat Soliman
  • Patent number: 10903798
    Abstract: A novel and useful noise reduction technique that improves the noise figure (NF) of a common-source (CS) low noise amplifier (LNA). The technique exploits dc current reuse and increases transconductance of the CS transistor while maintaining its power consumption. By using noise reduction and dc current reuse techniques, the thermal current noise of the noise cancellation stage is reduced without adding any extra branch to the circuit. As a result, the current thermal noise of second stage decreases dramatically leading to better NF without consuming any extra power. Moreover, since the circuit block is implemented using a pMOS transistor, the second order nonlinearity of pMOS and nMOS transistors cancel each other, resulting in improved nonlinearity performance of the LNA, including improvements to both IIP2 and IIP3.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: January 26, 2021
    Assignee: Short Circuit Technologies LLC
    Inventors: Amirhossein Ansari Bozorg, Robert Bogdan Staszewski
  • Patent number: 10804862
    Abstract: High frequency signal amplifier including balun is disclosed. The amplifier comprises an input terminal (Vin) through which the high frequency signal is input; a balun which is connected to the input terminal and outputs a first differential signal and a second differential signal based on the high frequency signal; a transistor (M) which is connected to the balun and outputs an amplified high frequency signal based on the first differential signal and the second differential signal; an output terminal which is connected to the transistor (M) and through which the amplified high frequency signal is acquired and the amplified high frequency signal is output. Therefore, performance of the amplifier can be enhanced.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: October 13, 2020
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sun Woo Kong, Myung Don Kim, Cheol Ho Kim, Hui Dong Lee
  • Patent number: 10700642
    Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: June 30, 2020
    Assignee: pSemi Corporation
    Inventors: Poojan Wagh, Kashish Pal, Robert Mark Englekirk, Tero Tapio Ranta, Keith Bargroff, Simon Edward Willard
  • Patent number: 10651798
    Abstract: Aspects of this disclosure relate to an amplification circuit that includes a stacked amplifier and a bias circuit. The stacked amplifier includes at least a first transistor and a second transistor in series with each other. The stacked amplifier is operable in at least a first mode and a second mode. The bias circuit is configured to bias the second transistor to a linear region of operation in the first mode and to bias the second transistor as a switch in the second mode. In certain embodiments, the amplification circuit can be a power amplifier stage configured to receive a supply voltage that has a different voltage level in the first mode than in the second mode.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: May 12, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventor: Yasser Khairat Soliman
  • Patent number: 10615762
    Abstract: Provided is a power amplification module that includes: a first amplification circuit that amplifies a first signal and outputs the amplified first signal as a second signal; a second amplification circuit that amplifies the second signal and outputs the amplified second signal as a third signal; and a feedback circuit that re-inputs/feeds back the second signal outputted from the first amplification circuit to the first amplification circuit as the first signal. The operation of the first amplification circuit is halted and the first signal passes through the feedback circuit and is outputted as the second signal at the time of a low power output mode.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: April 7, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Shota Ishihara
  • Patent number: 10547289
    Abstract: An N-path filter with one or more branches selectively coupled to a shared circuit node includes a first branch having a first feedback path and a second feedback path. The first feedback path includes a Miller amplifier having an input coupled to an input voltage and a first capacitor coupled to both the input voltage and an output of the Miller amplifier. The second feedback path includes a node in common with the first feedback path. The second feedback path also includes a first high pass filter coupled to the output of the Miller amplifier and a second capacitor coupled to both the first capacitor and the first high pass filter.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: January 28, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Joung Won Park, Li-chung Chang, Faramarz Sabouri
  • Patent number: 10511265
    Abstract: A Doherty power amplifier circuit comprises: a power divider, a carrier amplifier subcircuit, a combiner, and a peaking amplifier subcircuit, wherein a series resonance circuit is disposed between the carrier amplifier subcircuit and the combiner. In this way, reactance that would be introduced during an operating process of a conventional Doherty power amplifier circuit can be neutralized, such that a superior performance of the Doherty power amplifier circuit is ensured, and at the same time, a load-pull effect of the Doherty power amplifier circuit is improved to have a wider bandwidth, thereby realizing a communication device supporting operations in multiple frequency bands and multiple systems at the same time, and effectively lowering manufacturing and operation costs.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: December 17, 2019
    Assignee: Datang Mobile Communications Equipment Co., Ltd.
    Inventors: Baoqiang Ai, Yang Fang, Shimin Yang
  • Patent number: 10505543
    Abstract: In various embodiments, a level shifter circuit is provided. The level shifter circuit may include a signal source and a level shifter. The signal source, on the output side, is capacitively coupled to an input of the level shifter. The signal source and the level shifter are galvanically isolated from one another.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: December 10, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Michael Reinhold, Ulrich Reichold
  • Patent number: 10389306
    Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: August 20, 2019
    Assignee: pSemi Corporation
    Inventors: Poojan Wagh, Kashish Pal, Robert Mark Englekirk, Tero Tapio Ranta, Keith Bargroff, Simon Edward Willard
  • Patent number: 10340971
    Abstract: A PA module (10A) includes a previous stage amplification element (12) to amplify a high-frequency signal, a posterior stage amplification element (13) to amplify the high-frequency signal amplified by the previous stage amplification element (12), and a variable filter circuit arranged between the previous stage amplification element (12) and the posterior stage amplification element (13) to vary a pass band and an attenuation band in accordance with a frequency band of the high-frequency signal, in which the variable filter circuit includes a filter portion (16) and switches (14 and 15) to vary the pass band and the attenuation band of the variable filter circuit, and the previous stage amplification element (12) and at least a part of the switches (14 and 15) are formed in one chip using a chip A, the posterior stage amplification element (13) are included in a second chip which is different from the chip A.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: July 2, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hidenori Obiya, Reiji Nakajima, Shinya Hitomi
  • Patent number: 10326412
    Abstract: An amplifier includes an input terminal for receiving an input signal, an output terminal for outputting an output signal, a first transistor, a second transistor having a first terminal coupled to a second terminal of the first transistor, a third transistor having a first terminal coupled to a second terminal of the second transistor, a capacitor coupled between a control terminal and a second terminal of the third transistor, a bias circuit coupled to the first terminal of the third transistor for providing a bias voltage to the third transistor, a fourth transistor having a first terminal coupled to the input terminal and a second terminal coupled to the output terminal for providing a bypass path, and a fifth transistor having a first terminal coupled to the first terminal of the first transistor and a second terminal coupled to the output terminal.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: June 18, 2019
    Assignee: RichWave Technology Corp.
    Inventors: Chih-Sheng Chen, Chang-Yi Chen
  • Patent number: 10187013
    Abstract: Systems, methods and apparatus for efficient power control of an RF amplifier for amplification of a constant envelope RF signal are described. A reduction in a size of a pass device of an LDO regulator is obtained by removing the pass device of the LDO regulator from a main current conduction path of the RF amplifier. Power control is provided by varying one or more gate voltages to cascoded transistors of a transistor stack of the RF amplifier according to a power control voltage. Various configurations for controlling the gate voltages are presented by way of a smaller size LDO regulator or by completely removing the LDO regulator. In a case where a supply voltage to the transistor stack varies, such as in a case of a battery, a compensation circuit is used to adjust the power control voltage in view of a variation of the supply voltage, and therefore null a corresponding drift in output power of the RF amplifier.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: January 22, 2019
    Assignee: pSemi Corporation
    Inventor: David Kovac
  • Patent number: 10181829
    Abstract: An amplification circuit includes a first switching circuit that includes input terminals and first and second output terminals and that puts the second output terminal into an open state with respect to the input terminals while selectively putting the first output terminal into a state of being connected to any of the input terminals or selectively puts the second output terminal into a state of being connected to any of input terminals while putting the first output terminal into a state of being open with respect to the input terminals; a matching network that is connected to the first output terminal; an amplifier that is connected to an output side of the matching network; a second switching circuit that is connected to an output side of the amplifier; and a bypass path that electrically connects the second output terminal and an output terminal of the second switching circuit. The amplifier is a variable-gain amplifier.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: January 15, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Teruaki Oshita
  • Patent number: 10171050
    Abstract: In some embodiments, circuits for providing Class-E power amplifiers are provided, the circuits comprising: a first switch having a first side and a second side; a first Class-E load network coupled to the first side of the first switch; a second Class-E load network; and a second switch having a first side and a second side, the first side of the second switch being coupled the second side of the first switch and the second Class-E load network. In some embodiments, the circuits further comprise: a third switch having a first side and a second side; a third Class-E load network coupled to the first side of the third switch; a fourth Class-E load network; and a fourth switch having a first side and a second side, the first side of the fourth switch being coupled the second side of the third switch and the fourth Class-E load network.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: January 1, 2019
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Anandaroop Chakrabarti, Harish Krishnaswamy
  • Patent number: 10110168
    Abstract: Aspects of this disclosure relate to an amplification circuit that includes a stacked amplifier and a bias circuit. The stacked amplifier includes at least a first transistor and a second transistor in series with each other. The stacked amplifier is operable in at least a first mode and a second mode. The bias circuit is configured to bias the second transistor to a linear region of operation in the first mode and to bias the second transistor as a switch in the second mode. In certain embodiments, the amplification circuit can be a power amplifier stage configured to receive a supply voltage that has a different voltage level in the first mode than in the second mode.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: October 23, 2018
    Assignee: Skyworks Solutions, Inc.
    Inventor: Yasser Khairat Soliman
  • Patent number: 10075132
    Abstract: An amplifier includes a semiconductor substrate. A first conductive feature partially covers the bottom substrate surface to define a conductor-less region of the bottom substrate surface. A first current conducting terminal of a transistor is electrically coupled to the first conductive feature. Second and third conductive features may be coupled to other regions of the bottom substrate surface. A first filter circuit includes an inductor formed over a portion of the top substrate surface that is directly opposite the conductor-less region. The first filter circuit may be electrically coupled between a second current conducting terminal of the transistor and the second conductive feature. A second filter circuit may be electrically coupled between a control terminal of the transistor and the third conductive feature. Conductive leads may be coupled to the second and third conductive features, or the second and third conductive features may be coupled to a printed circuit board.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: September 11, 2018
    Assignee: NXP USA, INC.
    Inventors: Jeffrey K. Jones, David F. Abdo, Basim H. Noori
  • Patent number: 9972588
    Abstract: In a circuit substrate, a plurality of first microstrip lines connect outputs of a plurality of circuit patterns containing a parallel capacitor to a plurality of first output pads respectively. A plurality of second wires connect the first output pads of the circuit substrate to inputs of a plurality of transistor cells of a semiconductor substrate respectively. The numbers of the fingers of the transistor cells are the same. The first microstrip lines connected to the circuit patterns disposed on both sides of the lining-up circuit patterns are longer than the other first microstrip lines.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: May 15, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsuya Kato
  • Patent number: 9966988
    Abstract: A monolithic integrated circuit (IC), and method of manufacturing same, that includes all RF front end or transceiver elements for a portable communication device, including a power amplifier (PA), a matching, coupling and filtering network, and an antenna switch to couple the conditioned PA signal to an antenna. An output signal sensor senses at least a voltage amplitude of the signal switched by the antenna switch, and signals a PA control circuit to limit PA output power in response to excessive values of sensed output. Stacks of multiple FETs in series to operate as a switching device may be used for implementation of the RF front end, and the method and apparatus of such stacks are claimed as subcombinations. An iClass PA architecture is described that dissipatively terminates unwanted harmonics of the PA output signal.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: May 8, 2018
    Assignee: pSemi Corporation
    Inventors: Mark L. Burgener, James S. Cable
  • Patent number: 9887727
    Abstract: A transmit-and-receive module includes a duplexer, a power amplifier, and a low-noise amplifier. The duplexer includes a transmit filter and a receive filter. The power amplifier and the low-noise amplifier are integrated with each other. In a Smith chart, impedance in a receive band of the receive filter seen from a receive terminal intersects a line connecting a center point of noise figure circles and a center point of gain circles. The center point of the noise figure circles represents the impedance at which the noise figure of the low-noise amplifier is minimized. The center point of the gain circles represents the impedance at which the gain of the low-noise amplifier is maximized.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: February 6, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Jin Yokoyama, Shiro Masumoto
  • Patent number: 9871493
    Abstract: A first transistor has a first terminal and a second terminal. A second transistor has a third terminal, a fourth terminal and a fifth terminal electrically connected to the second terminal of the first transistor during amplification performed by the first transistor. A first bias circuit is electrically connected to the first terminal of the first transistor and supplies a first bias to the first terminal so that a magnitude of the first bias is increased with a rise in circuit temperature. A second bias circuit is electrically connected to the third terminal of the second transistor and supplies a second bias to the third terminal so that the magnitude of the second bias is constantly maintained with respect to changes in the circuit temperature.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: January 16, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventor: Tetsuya Heima
  • Patent number: 9806680
    Abstract: Apparatus and methods for radio frequency (RF) amplifiers are disclosed herein. In certain implementations, a packaged RF amplifier includes a first bipolar transistor including a base electrically connected to an RF input pin and a collector electrically connected to an RF output pin, and a second bipolar transistor including a base electrically connected to an emitter of the first bipolar transistor and a collector electrically connected to the RF output pin. The packaged RF amplifier further includes a first bias circuit electrically connected between the base of the first bipolar transistor and the RF output pin, a second bias circuit electrically connected between the base of the first bipolar transistor and a power low pin, an inductor implemented at least partly by a bond wire, and a third bias circuit electrically connected in series with the inductor between the base of the second bipolar transistor and the power low pin.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: October 31, 2017
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Alan William Ake, David C. Dening
  • Patent number: 9515906
    Abstract: A transceiver integrated circuit (IC) device for a multi-channel, and a method of operating the same are provided. The transceiver IC device transmits and receives information and data between a central gateway (CGW) and a plurality of electronic control units (ECUs) using a controller area network (CAN). The transceiver IC device includes a plurality of CAN transceivers and a monitoring sensor that detects whether a transceiver IC device operates normally. A wake-up detector detects a wake-up signal transmitted via a network and a controller transmits and receives a CAN signal to and from the plurality of CAN transceivers. In addition, a serial peripheral interface (SPI) communication portion transmits and receives information and data from the controller to and from a microcomputer of the CGW.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: December 6, 2016
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventors: Sang Hyun Jang, Hee Jun Lee
  • Patent number: 9485815
    Abstract: A backlight driving circuit is disclosed. The backlight driving circuit includes a steady voltage circuit, a boost converter, a current setting circuit, and a control circuit. The steady voltage circuit receives an input voltage, filters the input voltage and outputs a steady DC voltage. The boost converter connects to the steady voltage circuit to receive the steady DC voltage. The control circuit provides a first PWM square wave such that the boost converter may supply power to the LED light bar. Wherein the boost converter includes a first MOSFET or a triode. At least three parallel connected resistors are arranged between a source of the first MOSFET or a collector of the triode and the ground, and the three resistors have the same or similar resistance. In addition, a liquid crystal display includes the backlight driving circuit is also disclosed.
    Type: Grant
    Filed: December 25, 2012
    Date of Patent: November 1, 2016
    Assignees: Shenzhen China Star, Optoelectronics Technology Co., Ltd
    Inventor: Xianming Zhang
  • Patent number: 9431968
    Abstract: A circuit is disclosed to enhance slew rate of an amplifier. An amplifier includes an output, a first input, and a second input in a differential pair configuration. A slew rate enhancer includes a first slew rate enhancer and a second slew rate enhancer. The first slew direction enhancer is configured to detect a first slew rate condition in a first direction responsive to the first input and the second input and provide additional current for a first side of the differential pair of the amplifier during the first slew rate condition. The second slew direction enhancer is configured to detect a second slew rate condition in a second direction responsive to the first input and the second input and provide additional current for a second side of the differential pair of the amplifier during the second slew rate condition.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: August 30, 2016
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventor: G. Hossein Montazer
  • Patent number: 9424770
    Abstract: An error compensator and an organic light emitting display device using the same. The organic light emitting display device includes pixels each having a driving transistor and an organic light emitting diode; and a sensing unit extracting at least one of a first information including the threshold voltage of the driving transistor or a second information including the degradation of the organic light emitting diode from a pixel of the pixels. In the organic light emitting display device, the sensing unit includes an amplifier amplifying a voltage corresponding to the at least one of the first information or the second information; and an error compensator compensating for error components of elements included in the amplifier and the error compensator.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: August 23, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Bo-Yeon Kim, Oh-Jo Kwon, Hee-Sun Ahn
  • Patent number: 9379761
    Abstract: An impedance measurement system (IMS) is provided that comprises an RSSI chain (RSSI), a limiter RSSI chain (LIMRSSI) and a limiter chain (LIM). The RSSI chain and the limiter RSSI chain are connected to a subtraction circuit (SC) and the limiter RSSI chain and the limiter chain are connected to a phase detector (PD). Further, a mobile communication device is provided that comprises the impedance measurement system in an adaptive impedance control system.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: June 28, 2016
    Assignee: Qualcomm Technologies, Inc.
    Inventor: Peter Van Der Cammen
  • Patent number: 9300278
    Abstract: A circuit and method for calibrating CMOS (complementary metal-oxide semiconductor) inverters are provided. In a circuit, a first tunable CMOS inverter, controlled by a control signal, receives a first voltage from a first circuit node and outputs a second voltage to a second circuit node. A second tunable CMOS inverter, controlled by the control signal, receives the second voltage from the second circuit node and outputs the first voltage to the first circuit node. A resistor couples the first circuit node to the second circuit node. A switch, controlled by a reset signal, conditionally shorts the first circuit node to the second circuit node. A finite state machine receives the first voltage and the second voltage and outputs the reset signal and the control signal, wherein the control signal is adjusted based on a difference between the first voltage and the second voltage.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: March 29, 2016
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 9276538
    Abstract: Embodiments include an apparatus, system, and method related to a switch circuit. Specifically, embodiments relate to a low noise amplifier (LNA) drain switch circuit that includes a first field effect transistor (FET) where the drain contact of the first FET is coupled with a gate contact of a second FET. The drain contact of the second FET may also be coupled with the gate of the second FET through a resistor. The source contact of the second FET may be coupled with a diode which may be coupled with an LNA.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: March 1, 2016
    Assignee: TriQuint Semiconductor, Inc.
    Inventor: Charles F. Campbell
  • Patent number: 9054773
    Abstract: The invention relates to an apparatus 1 comprising a broadcast receiver circuit, an embedded antenna for receiving broadcast signals and a tuning circuit coupled between the antenna and the receiver circuit, which tuning circuit comprises a filter circuit coupled to ground, wherein the tuning circuit is designed to have a first resonance at a first frequency below a broadcast band of interest, and a second resonance at a second frequency above the broadcast band and wherein the tuning circuit comprises an amplifier with an output to the receiver circuit and with an input to the filter circuit, and wherein the tuning circuit is provided with a carrier to noise ratio (CNR) which is substantially flat across the broadcast band.
    Type: Grant
    Filed: March 19, 2009
    Date of Patent: June 9, 2015
    Assignee: NXP B.V.
    Inventor: Anthony Kerselaers
  • Patent number: 9035704
    Abstract: High impedance, high frequency nanoscale device electronics configured to interface with low impedance loads include an impedance transforming stage constructed of multiple nanoscale devices, such as carbon nanotube field-effect transistors. In an embodiment of the present invention, an impedance transforming output stage of a multistage amplifier is configured to drive a 50 ohm transmission line with unity voltage gain using multiple carbon nanotube field-effect transistors in parallel. In a further embodiment, a receiver provided for an electronically steered receive array is a monolithic, lumped-element system formed from nanoscale devices and configured to interface with the external electrical systems via a single transmission line.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: May 19, 2015
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Aaron A. Pesetski, Hong Z. Pesetski, James E. Baumgardner, II, Dale E. Dawson
  • Patent number: 9007130
    Abstract: A power amplifier configured to boost an AC signal. The power amplifier includes a first transistor, a second transistor, a first inductor connected between the first transistor and a voltage source, and a second inductor connected between the second transistor and ground. A first phase conditioner arranged at an input of the first transistor is configured to condition a phase of the AC signal such that the AC signal as received by the first transistor is out of phase with respect to the AC signal as received by the first inductor. A second phase conditioner arranged at an input of the second transistor is configured to condition a phase of the AC signal such that the AC signal as received by the second transistor is out of phase with respect to the AC signal as received by the second inductor.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: April 14, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Poh Boon Leong, Ping Song, Nuntha Kumar Krishnasamy Maniam
  • Patent number: 9000841
    Abstract: Embodiments of RF switching amplifiers are described generally herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: April 7, 2015
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Vikas Sharma, Jaroslaw Adamski, Neil Calanca, Robert Broughton
  • Patent number: 9000847
    Abstract: A tunable inter-stage matching circuit that can improve performance is described. In an exemplary design, an apparatus comprises a driver amplifier and a power amplifier. The apparatus may further include an inter-stage matching circuit tunable in discrete steps for matching impedances between the driver amplifier and the power amplifier. The tunable inter-stage matching circuit may include a bank of capacitors, each capacitor of the bank coupled in series with a switch for coupling the capacitor to a ground voltage.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: April 7, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Yu Zhao, Babak Nejati, Nathan M Pletcher, Aristotele Hadjichristos
  • Patent number: 8994456
    Abstract: A multi-stage amplifier is provided that uses tunable transmission lines, as well as a calibration method for the multi-stage amplifiers. A multi-stage amplifier, comprises a plurality of tunable amplification stages, wherein each of the tunable amplification stages comprises a tunable resonator based on a transmission line having a tunable element. The tunable elements may vary a capacitance or an inductance to tune a frequency of an applied signal. A calibration method is provided for a multi-stage amplifier having a plurality of transmission lines, an input stage and an output stage. The multi-stage amplifier is calibrated by generating a signal to determine a frequency for a substantially maximum power; generating an error signal by comparing the frequency for the substantially maximum power with a desired frequency; varying a digital control code applied to each of the tunable transmission lines, input stage and output stage until the error signal satisfies predefined criteria.
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: March 31, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mihai A. Sanduleanu, Alberto Valdes Garcia, David Goren, Shlomo Shlafman, Danny Elad
  • Patent number: 8994455
    Abstract: There is provided a radio frequency amplifying apparatus having a protection voltage varying function, including a radio frequency amplifying unit amplifying a radio frequency signal, and a protection circuit unit connected between an output node of the radio frequency amplifying unit and a ground and limiting a voltage in the output node to a level of a preset protection voltage or less when the voltage in the output node is higher than the preset protection voltage, wherein the protection voltage is varied with a control signal.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: March 31, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Youn Suk Kim
  • Patent number: 8988150
    Abstract: An amplifier includes a transformer including a primary coil whose one end is connected to an input port and whose other end is connected to reference potential and a secondary coil magnetically-coupled with the primary coil, and a transistor including a source connected to one end of the secondary coil and a gate connected to other end of the secondary coil and a drain connected to an output port side.
    Type: Grant
    Filed: January 13, 2013
    Date of Patent: March 24, 2015
    Assignee: Fujitsu Limited
    Inventor: Masaru Sato
  • Patent number: 8988149
    Abstract: An amplifier circuit, comprising: an input, for receiving an input signal to be amplified; a power amplifier, for amplifying the input signal; a switched power supply, having a switching frequency, for providing at least one supply voltage to the power amplifier; and a dither block, for dithering the switching frequency of the switched power supply. The dither block is controlled based on the input signal. Another aspect of the invention involves using first and second switches, each having different capacitances and resistances, and using the first or second switch depending on the input signal or volume signal. Another aspect of the invention involves controlling a bias signal provided to one or more components in the signal path based on the input signal or volume signal.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: March 24, 2015
    Assignee: Cirrus Logic International (UK) Limited
    Inventor: John Paul Lesso
  • Patent number: 8981852
    Abstract: A power amplifier includes a power amplifier core including a plurality of gain stages to receive a radio frequency (RF) signal and to output an amplified RF signal, an output network coupled to the power amplifier core to receive the amplified RF signal and output a transmit output power signal, and a directional coupler coupled to the output network to obtain a coupled signal proportional to the transmit output power signal. Each of these components can be configured on a single semiconductor die, in an embodiment.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: March 17, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventor: Timothy Dupuis
  • Patent number: 8975967
    Abstract: A low-noise amplifier (LNA) filter for use with global navigation satellite system (GNSS) devices is disclosed. A first LNA stage, which is configured to connect to an antenna configured to receive GNSS signals, includes an LNA. A second LNA stage, which is connected to the output of the first LNA stage, has a surface acoustic wave (SAW) filter and an LNA. A third LNA stage, which is connected to the output of the second LNA stage, also has a SAW filter and an LNA.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: March 10, 2015
    Assignee: Javad GNSS, Inc.
    Inventors: Javad Ashjaee, Dmitry Dubrovsky
  • Publication number: 20150048887
    Abstract: An amplifier circuit is configured in such a manner that the withstand voltage between the terminals of a FET 2 (withstand voltage B) is higher than the withstand voltage between the terminals of a FET 1 (withstand voltage A), and that the gate width of the FET 1 (Wg1) is narrower than the gate width of the FET 2 (Wg2). This makes it possible to increase the gain while maintaining high output power. The narrow gate width of the FET 1 (Wg1) connected to an input terminal 3 enables reducing the size of the cascode amplifier.
    Type: Application
    Filed: March 12, 2013
    Publication date: February 19, 2015
    Applicant: Mitsubishi Electric Corporation
    Inventors: Naoko Nitta, Katsuya Kato, Kenji Mukai, Kenichi Horiguchi, Morishige Hieda, Kazutomi Mori, Kazuya Yamamoto
  • Publication number: 20150048892
    Abstract: In one example embodiment, a current source is provided to limit noise and offset. In one embodiment, a source transistor is provided, with current sourced at the drain. A feedback network runs from the source node to the gate. The feedback network produces voltage gain by a transconductance, such as a transistor. Appropriate capacitors are also provided, and two pairs of switches are disposed to provide offset cancellation by toggling between gain and clamp modes in the switched capacitor architecture.
    Type: Application
    Filed: August 13, 2013
    Publication date: February 19, 2015
    Applicant: ANALOG DEVICES, INC.
    Inventors: William T. Boles, Michael R. Elliott
  • Patent number: 8922282
    Abstract: A radio frequency (RF) power amplifier includes a low impedance pre-driver driving the input of a common-source output amplifier stage. The preamplifier includes a first transistor that has a first terminal coupled to a preamplifier RF input node, a second terminal coupled to a preamplifier RF output node, and a third terminal coupled to a supply voltage node. A first inductor is coupled between the RF output node and a bias voltage node. A voltage difference between respective first and second voltages on the RF input node and the RF output node that are substantially in phase, determines current through the first transistor.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: December 30, 2014
    Assignee: Black Sand Technologies, Inc.
    Inventors: Susanne Paul, Marius Goldenberg
  • Patent number: 8907724
    Abstract: The embodiments of the present invention disclose a variable gain amplifier and relate to the field of electronic circuits. The linear-in-dB relationship between an output current and a control voltage of the variable gain amplifier is relatively ideal. The variable gain amplifier includes a fitted differential module group and an offset voltage output module, where the fitted differential module group is configured to output, under the control of a driving voltage and offset voltages, an output current of the variable gain amplifier according to a reference current; and the fitted differential module group includes n fitted differential modules, the n fitted differential modules are cascaded in turn, and n is any positive integer larger than 1.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: December 9, 2014
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jin Rao, Quan Liu, Yun Zhu, Huajiang Wang
  • Patent number: 8902003
    Abstract: An amplifier includes an amplifying stage configured to provide an amplifier output signal based on a combination of a received amplifying stage input signal and a received amplified version of the amplifying stage input signal.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: December 2, 2014
    Assignee: Intel Mobile Communications GmbH
    Inventors: Josef Holzleitner, Werner Schelmbauer
  • Publication number: 20140340160
    Abstract: A semiconductor power amplifier comprises an input-side amplifier for inputting and amplifying an input signal, a balanced amplifier which is connected to an output terminal of the input-side amplifier, comprises two hybrid couplers and a plurality of power amplifiers, passes the input signal, and converts a reflective wave into thermal energy, and an output-side amplifier which is connected to an output terminal of the balanced amplifier and amplifies an output signal.
    Type: Application
    Filed: November 18, 2013
    Publication date: November 20, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kenta KURODA
  • Patent number: 8884863
    Abstract: A buffer circuit includes a first transistor circuit having a first conductivity type transistor, a second transistor circuit having a second conductivity type transistors, in which the first and second transistor circuits are serially connected between a first fixed power supply and a second fixed power supply, and input terminals and output terminals of each of the first and second transistor circuits are connected in common respectively, in which at least one transistor circuit of the first transistor circuit and the second transistor circuit is a double gate transistor, and in which wherein a switch element, when any one transistor circuit of the first and the second transistor circuits is in an operating state, is included to supply a voltage of a third fixed power supply to a common connection node of the double gate transistor of the other transistor circuit.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: November 11, 2014
    Assignee: Sony Corporation
    Inventors: Tetsuro Yamamoto, Katsuhide Uchino
  • Patent number: 8854144
    Abstract: Some embodiments provide an amplifier apparatus, comprising: a plurality of amplifier transistor circuits coupled in series, wherein each of the plurality of amplifier transistor circuits comprises: a transistor, wherein the transistors of the plurality of amplifier transistor circuits are coupled in series; a transistor voltage control and drive circuit coupled with the corresponding transistor, wherein the transistor voltage control and drive circuit is configured to control and drive the corresponding transistor in accordance with received control signals and in parallel with the other of the plurality of amplifier transistor circuits; and isolation circuitry that isolates control of the transistor from control of the other of the amplifier transistor circuits; wherein the plurality of amplifier transistor circuits are configured to be controlled and driven in parallel relative to the control signals.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: October 7, 2014
    Assignee: General Atomics
    Inventors: Paul Huynh, Joseph F. Tooker
  • Patent number: 8854133
    Abstract: An amplifier includes an amplifier section having selectable signal paths to provide discrete gain settings, and logic to incrementally select the signal paths. The logic may be configured to increment the gain in response to digital gain control signals or an analog gain control signal. Another amplifier has an input section with one or more input cells and an output section with one or more output cells. Either the input section or the output section includes at least two cells that may be selected to provide discrete gain settings. A loop amplifier is configured in a feedback arrangement with the input section. The input and output sections may have multiple selectable cells to provide coarse and fine gain steps. The gain of the loop amplifier may be coordinated with the gain of the input section to provide constant bandwidth operation.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: October 7, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Barrie Gilbert, John Cowles, Todd C. Weigandt