Abstract: An amplification circuit includes a filter circuit, an amplifier, a capacitor, a bypass line, and a switch circuit that includes a first FET and a second FET connected in series between one end and the other end of the bypass line, a first resistance element connected in series to a gate of the first FET, and a second resistance element connected in series to a gate of the second FET. A first control signal is supplied to the gate of the first FET. A second control signal is supplied to the gate of the second FET. A product of a gate length and a gate width of the first FET and a resistance value of the first resistance element is smaller than a product of a gate length and a gate width of the second FET and a resistance value of the second resistance element.

Abstract: Multi-stage auto-zeroing signal amplifiers are deployed within event-shuttering pixels of a quanta image sensor (QIS) pixel array to enable reliable per-pixel reporting of photonic events, down to resolution of a single photon strike, for each of a continuous sequence of sub-microsecond event-detection intervals.

Abstract: An electronic device including an amplifier which includes a first transistor configured to receive an input signal through a gate terminal thereof and having a source terminal electrically connected to ground, a second transistor configured to transmit an output signal through a drain terminal thereof and having a gate terminal electrically connected to the ground, and a switch electrically connected to the gate terminal of the second transistor and configured to switch a voltage being supplied to the gate terminal of the second transistor in accordance with turn-on or turn-off of the amplifier.

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). An amplifier is provided. The amplifier includes a first resistor electrically connected to the input terminal, a second resistor electrically connected to the output terminal, a switch including a metal-oxide-semiconductor field-effect transistor (MOSFET) and electrically connected to one end of the second resistor, and a switch control processor configured to electrically connect the gate terminal of the MOSFET constituting the switch and the bulk terminal of the MOSFET constituting the switch to an impedance having an impedance value higher than a preset first threshold.

Abstract: A control method for controlling a three-phase dynamoelectric machine that has phase coils arranged in groups includes setting values of a time phase difference of electric currents to be supplied to the in-phase coils of respective groups and a time phase difference of carrier frequencies with which three-phase inverters are PWM-controlled to satisfy a predetermined relationship among the time phase difference of electric currents, the time phase difference of carrier frequencies, and a space phase difference of in-phase coils of the respective groups. The predetermined relationship is based on a result of a comparison between a current amplitude of a primary component and a current amplitude of a secondary component of a carrier harmonic current.

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). An amplifier is provided. The amplifier includes a first resistor electrically connected to the input terminal, a second resistor electrically connected to the output terminal, a switch including a metal-oxide-semiconductor field-effect transistor (MOSFET) and electrically connected to one end of the second resistor, and a switch control processor configured to electrically connect the gate terminal of the MOSFET constituting the switch and the bulk terminal of the MOSFET constituting the switch to an impedance having an impedance value higher than a preset first threshold.

Abstract: A bias timing control circuit includes a current source, a bias switch circuit, a duty cycle sensing circuit, and a switching control circuit. The bias switch circuit includes a first path switch, connected between an output node of the current source and a bias amplifying circuit, and a second path switch, connected between the output node of the current source and a temperature compensation circuit. The duty cycle sensing circuit is configured to generate a timing control signal based on a duty cycle of a transmission enable signal. The switching control circuit is configured to control a first turn-on time of the first path switch during an initial startup period, and a second turn-on time of the second path switch during a normal driving period subsequent to the initial startup period to adjust a warm-up time of a power amplifying circuit based on the timing control signal.

Abstract: An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.

Abstract: An electronic device according to an embodiment disclosed in the present document comprises: a housing; a first antenna element placed on the housing, or at a first position inside the housing; a second antenna element placed on the housing, or at a second position inside the housing; a communication processor; and at least one communication circuit electrically connected to the first antenna element and the second antenna element, wherein the at least one communication circuit can comprise: a first RF circuit, which generates an IF signal having a first frequency, a local oscillation (LO) signal of a second frequency lower than the first frequency, and a control signal of a third frequency lower than the second frequency; a second RF circuit, which provides, to the second antenna element, an RF signal of a fourth frequency higher than the third frequency and lower than the second frequency; and a third RF circuit, which receives the IF signal from the first RF circuit, up-converts the IF signal, and provides

Abstract: An example audio play circuit includes a power supply module, a power amplifier, a coupling capacitor, a load, and a plosive suppression circuit. An output terminal of the power amplifier is connected to a first terminal of the coupling capacitor and an output terminal of the plosive suppression circuit, a second terminal of the coupling capacitor is connected to the load, and an output terminal of the power supply module is connected to a power supply terminal of the power amplifier and a power supply terminal of the plosive suppression circuit. The power supply module is configured to provide a direct current power supply voltage for the power amplifier and the plosive suppression circuit. When the direct current power supply voltage rises to the first voltage threshold, the plosive suppression circuit connects the first terminal of the coupling capacitor to the ground terminal.

Abstract: Various embodiments relate to an amplifier circuit including: a first transistor having a first and second current conducting terminals and a control terminal; a second transistor having a first and second current conducting terminals and a control terminal, in which the second current-conducting terminal of the first transistor is connected to the first current-conducting terminal of the second transistor; a first inductor with a first terminal coupled to a first current-conducting terminal of the first transistor and a second terminal coupled to an output of the amplifier circuit; a feedback circuit connected between the output and the control terminal of the second transistor, wherein the feedback circuit includes a first resistor, a second inductor, and a first capacitor; and an input of the amplifier circuit connected between the first resistor and the second inductor, wherein a second current-conducting terminal of the second transistor is connected to a first ground terminal, and wherein a control term

Abstract: An amplifier circuit includes an output terminal, an amplification unit and a switch. The output terminal is used to output an amplification signal. The amplification unit includes a first transistor and a second transistor. The first transistor includes a control terminal for receiving a first input signal, a first terminal coupled to the output terminal for outputting an amplified first input signal, and a second terminal. The second transistor includes a control terminal for receiving a second input signal, a first terminal coupled to the output terminal for outputting an amplified second input signal, and a second terminal. The switch includes a first terminal coupled to the second terminal of the first transistor, and a second terminal. The amplification signal is generated using at least the amplified first input signal and/or the amplified second input signal.

Abstract: A semiconductor device includes three transistors, five switches, two inductors, and a capacitor. A first transistor has a gate. The switches have one terminal connected in series with a drain of the first transistor in parallel. A second transistor has a source connected to the first switch and a grounded gate. A third transistor having a source connected to the second switch and a grounded gate. A first inductor and a second inductor each has one terminal connected in series with the third switch in parallel. A fourth switch has one terminal connected to the first inductor and another terminal connected to the source of the second transistor. A fifth switch has one terminal connected to the second inductor and another terminal connected to the source of the third transistor. A capacitor connected between the one terminal of the fourth switch and the one terminal of the fifth switch.

Abstract: An envelope tracking (ET) amplifier apparatus is provided. In examples discussed herein, the ET amplifier apparatus can be configured to operate in a fifth-generation (5G) standalone (SA) mode and a 5G non-standalone (NSA) mode. In the SA mode, the ET amplifier apparatus can enable a first pair of amplifier circuits to amplifier a 5G signal for concurrent transmission in a 5G band(s). In the NSA mode, the ET amplifier apparatus can enable a second pair of amplifier circuits to amplify a non-5G anchor signal and a 5G signal for concurrent transmission in a non-5G anchor band(s) and a 5G band(s), respectively. As such, the ET circuit may be provided in a communication apparatus (e.g., a 5G-enabled smartphone) to help improve power amplifier linearity and efficiency in both 5G SA and NSA modes.

Abstract: An audio amplifier includes: a buck controller configured to control an output voltage at a first supply terminal, the output voltage selected from a set including a plurality of output voltages, where the output voltage takes a settling time to settle; a first audio bridge including: a class-AB driver stage coupled to the first supply terminal, and a delay insertion circuit configured to receive a processed digital stream and provide the processed digital stream to the class-AB driver stage a delay time after receiving the processed digital stream, where the delay time is based on the settling time; and an audio amplitude detector configured to detect a first peak amplitude in the first digital audio stream, where the buck controller is configured to select a lowest output voltage from the set that is higher than the first peak amplitude plus a headroom voltage.

Abstract: This disclosure describes auto-zero amplifier circuit that include an additional capacitor (or other capacitive component) that can be switchably coupler to a reference voltage. The auto-zero amplifier circuit can generate an auto-zero compensation signal using a difference between the reference voltage stored on the additional capacitor and a voltage stored on another auto-zero capacitor.

Abstract: A power efficient (PE) amplifier includes a cascode amplifier, a transistor amplifier, and a voltage supply. The transistor amplifier includes at least one differential pair of transistors and a plurality of transformers having a primary winding and a tapped secondary winding. The secondary winding is connected across emitters or sources of each transistor pair. The tap of each secondary has a current source. The primary windings of the plurality of transformers are connected in series. The transistor bases or gates are alternating current (AC) grounded. The collector or drain terminal pairs are connected in parallel. The voltage supply is low voltage and supplies a current to the cascode amplifier. The PE amplifier further includes a plurality of current sources which provide a total current to the transistor amplifier. The PE amplifier has, among other things, improved power gain, improved reverse isolation, improved power dissipation, and improved peak differential swing.

Abstract: Provided in the invention is a circuit for multiplexing an MON pin of a receiver optical sub-assembly for optical communication. Through a first clamping circuit, the high precision of a whole monitoring dynamic range is kept. Through a second clamping circuit, a voltage of the MON pin is clamped into an input voltage Vcont_in of the second clamping circuit, so that an external control signal Vcont_in is copied and input into the trans-impedance amplifier, and then the Vcont_in is converted into various control variables through a comparator or analog-to-digital converter.

Abstract: Audio amplification used in security systems need to be robust and have failsafe capability, they also need to be compact and energy efficient. A means of providing this by combining class D amplifiers in series is provided along with means to disconnect the amplifiers in a failure mode so as to provide ongoing operation should 1 of the amplifiers malfunction or another part of the system associated one of the amplifiers malfunction. The invention comprises an audio output stage which may be further integrated into an audio system having a supervisory controller to manage the transition from normal operation to failure state operation.

Abstract: An integration method for a 3D NAND flash memory device includes disposing a plurality of 3D triple-level cell (TLC) NAND flash memories on a CMOS die; disposing at least a NOR Flash memory on the CMOS die of the 3D NAND flash memory device; and connecting the at least a NOR Flash memory to an Open NAND Flash Interface (ONFI) of the 3D NAND flash memory device; wherein the at least a NOR Flash memory is disposed on an unused area of the CMOS die.

Abstract: In certain aspects, an apparatus includes a first power chain, a second power chain, and an enable circuit having an output coupled to an input of the first power chain. The apparatus also includes a multiplexer having a first input coupled to an output of the first power chain, a second input coupled to the output of the enable circuit, and an output coupled to an input of the second power chain, wherein the multiplexer is configured to receive a select signal, and couple the first input or the second input to the output of the multiplexer based on the select signal.

Abstract: A power amplifier circuit includes a first transistor having a base or gate connected to a signal path, an emitter or source grounded via a first conductor, and a collector or drain, the first transistor amplifying an input signal supplied to the base or gate thereof along the signal path and outputting the amplified signal from the collector or drain thereof; a first element in a preceding stage of the first transistor, the first element having a first end connected to the signal path such that the first element is connected along a path branched from the signal path, and a second end grounded via a second conductor; and a first capacitor having a first end connected to a node between the emitter or source of the first transistor and the first conductor, and a second end connected to a node between the first element and the second conductor.

Abstract: A hearing instrument comprises a wireless communication unit interconnected with an antenna for emission and reception of an electromagnetic field having an RF wavelength, a speaker interconnected with the wireless communication unit and being configured to provide an output audio signal. A battery is configured to supply power to the hearing instrument and a filter circuit interconnects the battery and a power management circuit of the hearing instrument. The antenna extends from a feed and at least a part of the antenna being is arranged adjacent the battery. A distance between the at least part of the antenna and the battery is below 1/40 of the wavelength. The filter circuit is configured to de-couple the battery and the power management circuit at frequencies above 3 MHz and configured to connect the battery to the power management circuit at frequencies below 300 kHz.

Abstract: The disclosure includes a voltage output circuit for use in a process automation field device, the voltage output circuit including an op-amp configured to supply the output voltage. The output circuit's op-amp is connected to the process automation system though a normally open switch. The normally open switch is closed only when the voltage output circuit is properly powered and operating. An improper connection of a power supply to the voltage output circuit will not power the voltage output circuit, and thus the switch remains open and protects the voltage output circuit from power being drawn in from the improper connection. The disclosure includes also a transceiver circuit having similar power draw protection.

Abstract: A driver circuit is provided. The driver circuit includes a first operational amplifier circuit, a second operational amplifier circuit, and at least one power switching circuit is provided. The first operational amplifier circuit receives a first input signal and generates a first output signal according to the first input signal. The second operational amplifier circuit receives a second input signal and generates a second output signal according to the second input signal. The at least one power switching circuit is configured to be coupled to switch a first input stage circuit to one of a first output stage circuit and a second output stage circuit, and the at least one power switching circuit is further coupled to switch a second input stage circuit to the other one of the first output stage circuit and the second output stage circuit.

Abstract: Self-regulating body-biasing techniques for Process, Voltage, and Temperature (PVT) fluctuation compensation in Fully-Depleted Silicon-on-Insulator (FDSOI) semiconductors are disclosed. In an illustrative, non-limiting embodiment, an electronic device may include a logic cell having a plurality of FDSOI transistors manufactured thereon; and at least one current source coupled to a body terminal of each transistor in a subset of the FDSOI transistors, wherein the current source is configured to output a high-impedance current.

Abstract: A high-voltage power amplification system can include a supply circuit configured to provide a high supply voltage in an average power tracking mode. The power amplification system can further include a power amplifier configured to operate with the high supply voltage and provide an impedance that substantially matches an impedance of a component coupled to an output of the power amplifier. The power amplification system can further include a signal path configured to route an amplified signal from the output of the power amplifier to the component, with the output path being substantially free of an output matching network.

Abstract: Disclosed herein are signal amplifiers having a plurality of amplifier cores. Individual amplifier cores can be designed for particular gain modes to enhance particular advantages while reducing other disadvantages. The signal amplifier can then switch between amplifier cores when switching gain modes to achieve desired performance characteristics (e.g., improving noise figure or linearity). Examples of signal amplifiers disclosed herein include amplifier architectures with a high gain amplifier core that reduces the noise figure and a linearity boost amplifier core that increases linearity (e.g., for lower gain modes). The disclosed signal amplifiers have a first active core with amplification chains for each of a plurality of inputs and a second active core with a single amplification chain to amplify signals received at the plurality of inputs.

Abstract: An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.

Abstract: Methods and systems for optimizing amplifier operations are described. The described methods and systems particularly describe a feed-forward control circuit that may also be used as a feed-back control circuit in certain applications. The feed-forward control circuit provides a control signal that may be used to configure an amplifier in a variety of ways.

Abstract: Systems and methods for suppressing transient outputs from an amplifier system are provided. An amplifier having a plurality of bias levels may be controlled to initiate a change in the level of a bias signal provided to the amplifier. The level of the bias signal is ramped from an initial bias level to a final bias level over numerous steps. The steps include at least one step in which the level of the bias signal is between the initial bias level and the final bias level. An amplifier system having multiple stages may be controlled to enable each stage and selectively couple each stage in a sequence that couples an output stage to an output terminal at the completion of the sequence.

Abstract: The Ethernet switch for an optic fiber network includes: a first light emitter designed to transmit a light signal in the optic fiber, first photodetector configured to transform a light signal coming from the optic fiber into an electric signal, at least one communication port of electric signals with a terminal, a power supply circuit configured to supply power to the light emitter and to the first photodetector, a wake-up circuit connected to the first photodetector and to the communication port configured to generate an electric wake-up signal on receipt of a light signal by the first photodetector and/or of an electric signal on the communication port, the wake-up circuit being connected to the power supply circuit to trigger power supply of the first light emitter and of the communication port.

Abstract: This application relates to methods and apparatus for monitoring the operating state of an audio circuit, and in particular for detecting a defective operating state, as may occur after an Electrical Over-Stress (EOS) event. An audio circuit (210) has an input node (103) for receiving an input audio signal (SIN) and an output node (104) for outputting an output audio signal (AOUT) for driving an audio load. A monitoring module (202) receives a first signal (S1) derived from the output audio signal and a second signal (S2) indicative of the input audio signal. The monitoring module (202) monitors the first signal (S1) with respect to the second signal (S2) to determine whether at least one parameter of the first signal corresponds to an expected parameter value based on the indication of input audio signal. If the parameter does not correspond to the expected parameter value, the monitoring module (202) outputs an indication (CTRL) of a defective operating state of the audio circuit (201).

Abstract: A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors and gate to ground caps for each legs can be used to further improve the matching performance of the invention.

Abstract: A signal amplifier includes a first amplifier, a second amplifier, and an output. The first amplifier amplifies a first input signal to form a first amplified output signal. The first input signal has a common mode voltage in a first voltage range, and the first amplified output signal has a common mode voltage in a second voltage range different from the first voltage range. The second amplifier amplifies a second input signal to form a second amplified output signal. The first input signal has the common mode voltage in the second voltage range and the second amplified output signal has the common mode voltage in the second voltage range. The output outputs the first amplified output signal or the second amplified output signal as an amplified output signal.

Abstract: [Object] To provide a communication device, an information processing device, and a communication method. [Solution] A communication device including: a detector configured to detect an optical signal and convert the optical signal to an electric signal; a data processing unit configured to process the electric signal converted by the detector to acquire data; and a controller configured to control an operating state including a standby state in which the data processing unit is deactivated to reduce power consumption and an active state in which the data processing unit is capable of executing acquisition of the data on a basis of the optical signal detected by the detector, in which the detector detects the optical signal in the standby state.

Abstract: An analog multiplexer core circuit (120A) includes a differential pair (121) that includes two transistors (Q1, Q2), a differential pair (122) that includes two transistors (Q3, Q4), a differential pair (123) that includes two transistors (Q5, Q6), and a constant current source (124) that causes a current (IEE) to flow. This analog multiplexer core circuit (120A) time-multiplexes two analog signals (Ain1, Ain2) and outputs a time-multiplexed analog signal (Aout). Each emitter resistor (REA1, REA2, REA3, REA4) is connected to a corresponding one of the transistors (Q1, Q2, Q3, Q4). At this time, a relation of “REA·IEE?the amplitude of an input analog signal” is satisfied. As a result, linearity of response can be ensured by expanding the linear response input range of the differential pairs (121, 122).

Abstract: An amplifier amplifies an input signal. A splitter branches an output signal of the amplifier into a first signal path and a second signal path and performs impedance conversion of the first and second signal paths. A first output terminal outputs the output signal of the amplifier or a signal obtained by branching the output signal of the amplifier into the first signal path by the splitter. A second output terminal outputs the output signal of the amplifier or a signal obtained by branching the output signal of the amplifier into the second signal path by the splitter. An output controller switches whether the output signal of the amplifier is output from the first output terminal, is output from the second output terminal, or is branched by the splitter to be output from both the first and second output terminals.

Abstract: Amplifier systems and methods are provided that include a fixed gain amplification stage coupled to an adjustable attenuation stage further coupled to a variable gain amplification stage. A controller controls an amount of attenuation provided by the adjustable attenuation stage and an amount of gain provided by the variable gain amplification stage to maintain any of various noise, efficiency, and/or linearity requirements of the amplifier system.

Abstract: Disclosed herein are signal amplifiers having a plurality of amplifier cores. Individual amplifier cores can be designed for particular gain modes to enhance particular advantages while reducing other disadvantages. The signal amplifier can then switch between amplifier cores when switching gain modes to achieve desired performance characteristics (e.g., improving noise figure or linearity). Examples of signal amplifiers disclosed herein include amplifier architectures with a high gain amplifier core that reduces the noise figure and a linearity boost amplifier core that increases linearity (e.g., for lower gain modes). The disclosed signal amplifiers can also have switchable reference biases to provide targeted bias current matching. The disclosed signal amplifiers can also include degeneration switching blocks for individual amplifier cores to improve signal linearity.

Abstract: A switching circuit is provided. The switching circuit includes at least one Surface Acoustic Wave (SAW) filter, a Single-Pole n Throw (SPnT) switch connected to an input port of each of the at least one SAW filter, and a Dual-Pole n Throw (DPnT) switch connected to an output port of each of the at least one SAW filter.

Abstract: A power detector with a detection signal input connectable to a source of a radio frequency signal and a detected power level output has a differential amplifier detector circuit with an input connected to the detection signal input and an output corresponding to the detected power level output. A feedback network is connected to the input and the output of the differential amplifier detector circuit. A mirror circuit is connected to the differential amplifier detector circuit. A root mean square current corresponding to a power level of the radio frequency signal from the source is mirrored and integrated, with a direct current voltage level being generated therefrom and output to the detected power level output.

Abstract: A device includes a substrate and a package input terminal. The device includes a driver amplifier mounted to the substrate and configured to receive a radio frequency input signal. A first amplifier is mounted to the substrate. The first amplifier includes a first amplifier input terminal. A second amplifier is mounted to the substrate. The second amplifier includes a second amplifier input terminal. An inter-stage network is connected between the driver amplifier and the first amplifier and between the driver amplifier and the second amplifier. The inter-stage network includes a first capacitor connected between the driver amplifier and the first amplifier input terminal, and an inductor having a first terminal and a second terminal. The first terminal of the inductor is connected to the first capacitor. The inter-stage network includes a second capacitor connected between the second terminal of the inductor and the second amplifier input terminal.

Abstract: A method of characterizing the performance of the payload of a satellite in orbit is executed with the aid of a test ground station including first radio-frequency amplification means and a radio-frequency transmit ground antenna. The method includes a step of providing first amplification means that can be configured to generate at the input of the transmit ground antenna a wide-band test thermal noise the power spectral density of which can be adjusted to a test thermal noise reference power spectral density Dref so that the ratio of the test thermal noise spectral density received at the input of the transponder and that corresponds to it to the thermal noise floor spectral density generated by the satellite alone internally and the natural thermal noise of the Earth is greater than or equal to a first threshold Ds1 equal to 10 dB. An IOT system is configured to execute the method.

Abstract: A front end circuit includes a bypass circuit comprising a first bypass switch and a second bypass switch configured to bypass a signal to a first terminal according to switching operations of the first bypass switch and the second bypass switch; and an amplifier connected in parallel to the bypass circuit and configured to amplify the signal.

Abstract: Certain aspects of the present disclosure provide a switch architecture for switching between a low power amplifier and a high power amplifier. One example amplification system includes a high power amplifier and a low power amplifier. The amplification system further includes a first switch coupled between the high power amplifier and an output. The amplification system further includes a second switch coupled between the output and a reference potential. The second switch is further coupled between the low power amplifier and the output and configured to selectively couple the low power amplifier to the output. The amplification system further includes a third switch coupled between the low power amplifier and the second switch.

Abstract: A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” input stage and a “common gate” output stage can be turned on or off using the gate of the output stage. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input stage of each cascode. Further switches used for switching degeneration inductors, gate/sources caps and gate to ground caps for each legs can be used to further improve the matching performance of the invention.

Abstract: According to an embodiment, a high-frequency semiconductor amplifier circuit includes an input terminal and an output terminal. A gate of a first transistor is connected to the input terminal. A drain of the first transistor is connected to the output terminal. A second transistor is connected between a source of the first transistor and a reference potential terminal. A bias generation circuit has an input control signal terminal, a bias voltage terminal connected to the gate of the first transistor, a control voltage terminal connected to a gate of the second transistor, and an intermediate voltage terminal connected to the drain of the first transistor. The bias generation circuit supplies a control voltage, a bias voltage, and a first voltage according to the input control signal.

Abstract: The invention relates to a method for mixing a plurality of audio streams coded according to a frequency sub-band coding, comprising the steps for decoding (E201) a part of the coded streams over at least a first frequency sub-band, for summing (E202) the streams thus decoded so as to form at least a first mixed stream. The method is such that it comprises the steps for detection (E203), over at least a second frequency sub-band different from the at least first sub-band, of the presence of a predetermined frequency band in the plurality of coded audio streams and for summing (E205) the decoded audio streams (E204) for which the presence of the predetermined frequency band has been detected, over said at least a second sub-band, so as to form at least a second mixed stream. The invention also relates to a mixing device implementing the method described and may be integrated into a conference bridge, a communications terminal or a communications gateway.

Abstract: A method for ramping a switched capacitor power amplifier is disclosed, where the switched capacitor power amplifier comprises a plurality of capacitors in a capacitor bank, and where a number of the capacitors in the capacitor bank are activated. The method comprises changing the number of capacitors in the capacitor bank that are activated, maintaining the changed number of activated capacitors in the capacitor bank for a period of time, and repeating the changing and maintaining, where a length of the period of time is varied between at least two repetitions of the maintaining.