Abstract: The invention relates to a method for configuring a set of multi-carrier power amplifiers, MCPAs, to provide power amplification for a set of base station transmitters. The method is characterized by switching at least a first MCPA in the set of multi-carrier power amplifiers such that the at least first MCPA stops providing power amplification to at least a first subset of the set of base station transmitters, and switching at least a second MCPA in the set of multi-carrier power amplifiers such that the at least second MCPA starts to provide power amplification to the at least first subset of the set of base station transmitters. The invention also relates to a distributing unit connectable to such a base station and a base station comprising a distributing unit.

Abstract: An amplifier with improved noise reduction is disclosed. In one implementation, an amplifier is provided that includes a main output stage configured to output an amplified signal at a main output terminal, a secondary output stage configured to output a copy of the amplified signal at a secondary output terminal, and a signal coupler configured to provide a variable resistance coupling between the secondary output terminal and the main output terminal to reduce noise at the main output terminal.

Abstract: A high-frequency power amplifier that amplifies a high-frequency input signal and outputs a signal having one power selected from a plurality of powers includes a high output route that is a circuit, which amplifies the input signal and outputs a signal of a high power, and a medium output route that is a circuit, which amplifies the input signal and outputs a signal of a medium power. The high output route includes a high-output amplifier that amplifies the input signal, an output matching circuit that is connected to an output node of the high-output amplifier, and a switch element that is connected to an output node of the output matching circuit. The medium output route includes a medium-output amplifier that amplifies the input signal and a switch element that is connected between an output node of the medium-output amplifier and an output node of the output matching circuit.

Abstract: A control method and apparatus of a peak amplifier of a Doherty power amplifier are disclosed, wherein, the control apparatus includes a Radio Frequency (RF) switching circuit in a peak amplification branch of the Doherty power amplifier, which is used to control the turn-on and turn-off of the peak amplifier in the peak amplification branch. The method and apparatus avoid a disadvantage that the peak branch in the Doherty power amplifier is turned on ahead of time, thus reducing the power consumption of the peak power amplifier, and enhancing the mass efficiency of the whole power amplifier; and largely reducing the product expense and production expense of the power amplifier compared to the scheme of some manufacturers improving on-time of the peak power amplifier using complex digital circuits.

Abstract: A power amplifier includes an input terminal into which an input signal is input; a first amplification element amplifying the input signal; a second amplification element amplifying an output signal of the first amplification element; an output terminal from which an output signal of the second amplification element is output; a first matching circuit connected between an output of the second amplification element and the output terminal; a first switch connected between an output of the first amplification element and an input of the second amplification element; a second switch having a first end connected to the output of the first amplification element, and a second end; and a second matching circuit having a first end connected to the second end of the second switch, and a second end directly connected to the output of the second amplification element.

Abstract: A noise reduction circuit for reducing the effects of low frequency noise such as wind noise in communications applications is described. In one embodiment, the noise reduction circuit features a high pass filter formed by exploiting the existing off-chip AC coupling capacitances in making the connection to the source of audio signals. The filter may be adaptive to environmental low frequency noise level through programming the shunt resistances. A low-noise wide dynamic range programmable gain amplifier is also described. Adaptive equalization of the audio signal is also described through the utilization of programmable front-end resistors and a back-end audio equalizer.

Abstract: Switching error in an auto-zero offset amplifier is reduced by keeping a clock level to the auto-zero switches at an amplitude just enough to insure complete switching of the switches of the auto-zero offset buffer amplifier. A level shifting circuit provides the clock at the desired level control and a local voltage regulator provides a regulated voltage to the level shifting circuit.

Abstract: A power amplification circuit having three modes of operation and a single switch is disclosed. Only one switch is used to control three different load impedance levels, one load impedance level for each mode of operation. The remaining “switching” results from selectively biasing each power amplification path by turning ON or OFF amplifiers. A series L-C and a switch are used to control the load impedance. Additional modes of operation may also be created without requiring any additional switch. Further, multiple modes of operation may be implemented using no switches.

Abstract: A communications system includes a communications device having a plurality of access modules each having a port and connected to a communications line and a plurality of transmitters with the respective transmitter associated in one-to-one correspondence with the communications line of an access module. Each transmitter has a line driver and is configured to couple communications signals to a respective communications line. A voltage source is connected to the line drivers and configured to provide a bias voltage to the line drivers that varies depending on a selected minimum power level. A controller is connected to the voltage source and has logic configured to change the bias voltage to the line drivers. The controller is responsive to a minimum data rate for each bias voltage.

Abstract: An amplifier is disclosed, wherein the output stage is split between a primary output stage and a secondary stage. To minimize or eliminate any audible plop when the amplifier is switched on, the primary stage is connected, and the second stage is gradually connected using a switch. The gradual connection can be by means of varying the pulse-density of a pulse wave modulation on the switch, from fully open (0% pulse-density) to fully closed (100%). The inverse process can minimize or eliminate plop during switch-off. Separate feedback loops are switchable, from the primary and secondary stages; in a DC-coupled embodiment, the feedback loop from the secondary stage may include DC-offset cancelling circuitry, to both reduce or eliminate the plop and avoid and DC-offset current through the speaker.

Abstract: Apparatus and methods for capacitive load reduction are disclosed. In one embodiment, a power amplifier system includes a plurality of power amplifiers and an envelope tracking module for generating a supply voltage for the power amplifiers. The power amplifier system further includes a switch and a decoupling capacitor operatively associated with a first power amplifier of the system. The switch is configured to electrically float an end of the decoupling capacitor when the first power amplifier is disabled so as to reduce capacitive loading of the envelope tracker and to operate as a dampening resistor when the power amplifier is enabled so as to improve the stability of the system.

Abstract: A reconfigurable network arrangement of resistors and switches is constructed so that it can be coupled to one or more operational amplifiers and selectively programmed so as to set the gain of the resulting amplifier. The configuration of the network arrangement of resistors and switches to include resistors that can be connected in the feedback path in series and in parallel with each other is such as to provide a wider selection of gain settings, without the need to increase the physical area of the switches on a integrated circuit arrangement.

Abstract: An output circuit includes first to fourth transistors, first and second constant current units, and a differential pair. The gates of the first and second transistors are supplied with two input signals, respectively. The drain of the first transistor is coupled to the drain of the third transistor and the gate of the fourth transistor. The drain of the second transistor is coupled to the gate of the third transistor and the drain of the fourth transistor. The first constant current unit is coupled to the sources of the third and fourth transistors. The differential pair includes two transistors, and the gates of the two transistors are coupled to the drains of the first and second transistors, respectively. The second constant current unit is coupled to the sources of the two transistors. Two output signals are output from two nodes respectively corresponding to the drains of the two transistors.

Abstract: The invention provides an analog circuit that decreases an effect of variation of a transistor. By flowing a bias current in a compensation operation, a voltage between the gate and source of the transistor to be compensated is held in a capacitor. In a normal operation, the voltage stored in the compensation operation is added to a signal voltage. As the capacitor holds the voltage according to the characteristics of the transistor to be compensated, the effect of variation can be decreased by adding the voltage stored in the capacitor to the signal voltage. Further, an analog circuit which decreases the effect of variation can be provided by applying the aforementioned basis to a differential circuit, an operational amplifier and the like.

Abstract: A radio frequency (RF) circuit includes a power supply configured to generate a plurality of voltages, a plurality of power amplifiers, each having an RF output port and a power supply input port, a switch network having a plurality of input ports coupled to the power supply and a plurality of switch network output ports coupled to the power supply input ports of the plurality of power amplifiers, wherein the switch network is configured to output selected ones of the plurality of voltages from the plurality of switch network output ports, at least two of the switch network output port voltages capable of being different ones of the plurality of voltages, and an RF power combiner circuit having a plurality of input ports coupled to RF output ports of the plurality of power amplifiers and an output port at which is provided an output signal of the RF circuit.

Abstract: In a high frequency antenna switch module, an I/O interface generates various control signals for controlling a switch module on the basis of a system data signal and a system clock, a decoder generates a switch control signal SWCNT for controlling a switch in response to a control signal CNT in the control signals, a timing detector for switch-ports switching generates a switch-port switching detection signal t_sw in response to the switch control signal, a frequency control signal generator generates frequency control signals ICONT and CCONT in response to the signal t_sw, and a negative voltage generation circuit generates a negative voltage output signal NVG_OUT while switching the frequency of the clock signal generated in the negative voltage generation circuit to different frequencies in response to signals ICONT and CCONT. The switch switches the paths among the plural switch ports in response to the signals SWCNT and NVG_OUT.

Abstract: A power amplifier includes: a first amplifying element amplifying an input signal; a second amplifying element amplifying an output signal of the first amplifying element; a third amplifying element amplifying the input signal; a first switch connected between an output of the first amplifying element and an input of second amplifying element; a second switch connected between an output of the first amplifying element and an output of the third amplifying element; a third switch connected between an output of the first amplifying element and an output of the second amplifying element; a reference voltage generating a circuit generating reference voltage; a bias circuit supplying a bias current, based on the reference voltage, to inputs of the first, second, and third amplifying elements; and a control circuit controlling the first, second and third switches and the reference voltage generating circuit.

Abstract: The invention is based on the fact that the current output from a DDB controlled amplifier in backoff, i.e. for low amplitudes, is reduced more or less linearly with the amplitude of the signal to be amplified. Therefore, it is enough to use smaller amplifiers which are able to output the necessary RF current. Hence, according to the present invention, the total DDB amplifier is divided into smaller parts that are coupled to the output only when needed.

Abstract: The present invention relates to an amplifier circuit where a load modulation is applied to a segmented amplifier. This will reduce the shunt loss since the loss of a segmented amplifier is reduced by allowing each amplifier segment or combination of segments to operate to their full output power capacity, rather than limited to a lower output power which results in a higher shunt loss. Hence, operation to full capacity before adding more segments is made possible by dynamically modulating the load.

Abstract: The low-noise amplifier with through mode is configured such that a source grounded transistor and a gate grounded transistor are connected in cascode, and a load impedance element and a switching transistor are serially connected between the drain of the gate grounded transistor and a power supply, and a through pass circuit is connected between an input terminal and an output terminal. The gate voltage of the gate grounded transistor is regulated by a bias circuit and the voltage of a mode control terminal is converted by a level shifter to control the gate voltage of the switching transistor, whereby, in the case of using only transistors whose terminal-to-terminal breakdown voltages are each equal to or less than the power supply voltage, it becomes feasible to prevent voltages equal to or more than the terminal-to-terminal breakdown voltages from being applied between the terminals of each transistor.

Abstract: Disclosed herein is a receiver, including: an amplifier for amplifying a received signal; a strain compensator for having a function of compensating for a strain generated in an output signal from the amplifier in accordance with a stain compensation amount which is controlled based on a bias signal from the output signal from the amplifier; and a stain compensation amount controlling portion for generating the bias signal and outputting the bias signal to the strain compensator so that the strain compensation is carried out with a compensation amount corresponding to a strength of the received signal.

Abstract: An apparatus and a method for expanding an operation region in an envelope tracking power amplifier are provided. The apparatus for amplifying power of a transmission signal includes an amplitude component determination unit, a supply modulator, and a power amplify module. The amplitude component determination unit determines an amplitude component of a transmission signal. The supply modulator generates a supply voltage to be provided to the power amplify module depending on the amplitude component of the transmission signal determined by the amplitude component determination unit. The power amplify module amplifies power of the transmission signal depending on the supply voltage generated by the supply modulator.

Abstract: Embodiments of a two-stage bypass power amplifier are provided. In general, the two-stage bypass power amplifier is configured to receive a RF signal that is to be transmitted to a remote device and provide gain to the RF signal prior to the RF signal being transmitted to the remote device. The two-stage bypass power amplifier is configured to operate efficiently (in terms of power) at two different gain or output power levels and can be extended to operate efficiently at additional gain or output power levels.

Abstract: An amplifier and a display driving circuit. The amplifier includes an input stage, a bias stage and an output stage. The input stage determines voltage levels of two nodes in correspondence to two input voltages received in response to a first bias voltage, and includes four path selecting switches, two input transistors and one bias transistor. The bias stage generates two class AB output voltages which correspond to the voltage levels of the two nodes, and includes current mirrors, ten path selecting switches, class AB bias circuits and two bias transistors. The output stage generates an output voltage VOUT that corresponds to the two class AB output voltages, and includes two coupling capacitors and two push-pull transistors. The plurality of path selecting switches operate by one signal of a first path selecting signal and a second path selecting signal that are exclusively enabled with respect to each other.

Abstract: An operational amplifier includes an input stage, an output stage, an output enable switch, an internal capacitor, a coupling effect reduction circuit. The input stage provides an intermediate signal according to an input signal. The output stage, including an output node, provides a driving signal according to the intermediate signal. The output enable switch is turned on during an output enable period, having a start time point, to drive a load with the driving signal. The internal capacitor is coupled between the input stage and the output stage. The coupling effect reduction circuit, coupled between the internal capacitor and the output node or between the internal capacitor and the input stage, is turned off during an operational period starting from the start time point, to prevent coupling charge generated when the output enable switch is turned on from affecting operational voltage levels of the input stage.

Abstract: An amplifier circuit includes an amplifier and a noise suppression block. The amplifier is arranged for receiving an input signal at an input port and generating an output signal at an output port according to the input signal. The noise suppression block is coupled between the input port and the output port of the amplifier, and arranged for receiving the input signal and the output signal and applying noise suppression to the output signal generated from the amplifier according to the received input signal and the received output signal.

Abstract: An amplifier circuit (10) comprises a driver stage (11) with a driver output (13). Moreover, the amplifier circuit (10) comprises a sensor (12). The sensor (12) comprises a variable attenuator (15) with a control input (16) for receiving a mode signal (SMODE). A sensor output (14) of the sensor (12) is coupled to the driver output (13) via the variable attenuator (15). A sensor signal (SE_RFOUT) is provided at the sensor output (14).

Abstract: Provided is a power consumption control circuit, an amplifier circuit and a power consumption control method which control the power consumption associated with an amplification action in real time. A power consumption control circuit of the present invention comprises: a detection means which detects the presence or absence of an input of a digital input signal, spending a first period of time; a signal delay means which delays the digital input signal by a second period of time equivalent to the first period of time, and outputs the delayed signal; a digital-to-analog conversion means which converts the delayed signal into an analog signal, and outputs the analog signal; an amplification means which generates an amplification action when a bias is applied to it; and a bias control means which applies a bias to an amplification device, on the basis of a detection result obtained by the detection means.

Abstract: A transconductance comparator includes a comparator having an output of a detector configured to sense an amplitude of an output of a Variable Gain Amplifier (VGA) of a receiver as a first input and a reference amplitude level as a second input. The comparator generates an error signal based on the first input and the second input. The transconductance comparator also includes a transconductance amplifier having a differential voltage input based on the error signal generated through the comparator and generating an output current. The transconductance amplifier includes current sources associated with programmable current limits thereof and differential pairs associated with the current sources, one or more of which is implemented with a size mismatch between transistors thereof to eliminate an offset error due to a mismatch between the current limits, thereby enabling programmability of an attack time and a decay time during automatic gain control of the VGA.

Abstract: A variable gain amplifier circuit includes output nodes, a plurality of amplifiers, and a detection circuit. The amplifiers are coupled in parallel with each other between the output nodes and a reference node and selectively assume an operating state in accordance with a control signal. The detection circuit outputs a detection signal according to the magnitude of an input signal to each amplifier. Each amplifier includes a first transistor, a second transistor, and a bias circuit. The first transistor receives, at its control electrode, the input signal or a signal proportional to the input signal. The second transistor is series-coupled to the first transistor between the first reference node and an output node. The bias circuit applies a DC voltage of a magnitude according to the detection signal to a control electrode of the second transistor.

Abstract: An exemplary embodiment discloses a digital control block for dynamically regulating power consumption of the transmitter; and a first driver amplifier circuit comprising a plurality of bias-modes each corresponding to a power consumption level in the transmitter, the digital control block to instruct the first driver amplifier circuit to operate in a selected bias-mode to regulate power consumption of the transmitter.

Abstract: An apparatus comprising an amplifier and a switch network. The amplifier may be configured to generate a plurality of output signals in response to an input signal. The switch network may be configured to provide (i) a first path when a power signal is not present and (ii) a second path when said power signal is present. The first path may activate a first of the plurality of output signals. The second path may activate all of the plurality of output signals. An impedance may be connected to the amplifier only when the first path is activated.

Abstract: A power amplifier includes a first amplifier and a second amplifier which include large and small size elements. An RF input signal is amplified by the first and second amplifiers. An output of the first amplifier is connected to an input of a first output matching circuit. An output of the second amplifier is connected to an input of a second output matching circuit. An output of the second output matching circuit is connected to an RF signal output terminal. In a high power state, the RF input signal is amplified by the first amplifier. In a low power state, the RF input signal is amplified by the second amplifier. In amplification with low power and high frequency, reactances of the second output matching circuit are set at predetermined values. In amplification with low power and low frequency, the reactances of the second output matching circuit are set at larger values.

Abstract: A consumer electronic product (e.g., a portable media player ported to a media delivery accessory) is powered by a limited capacity DC power source (such as a battery or mini-fuel cell). The consumer electronic product limits the maximum allowable sound pressure level (SPL) that can be produced by the speakers. In one embodiment, the maximum allowable SPL is based upon an amount of stored energy available in the limited capacity DC power source.

Abstract: A switched amplifier circuit arrangement comprises a main amplifier (Amp) having an input terminal (In) and an output terminal (Out) and a regulating amplifier (rAmp) to set an input and an output operating point of the main amplifier (Amp). The regulating amplifier (rAmp) exhibits an auxiliary amplifier (A) having a first input terminal coupled to a reference level (Vref), a second input terminal (Ain) coupled to the output terminal (Out), and an output terminal (Aout) which is connected via a first switch (S1) to the input terminal (In). Moreover, the switched amplifier circuit arrangement comprises a cancellation capacitor (Cc) coupled to the input terminal (In), a second switch (S2) which is coupled between the output terminal (Out) and the cancellation capacitor (Cc) at a first circuit node (n1), and a third switch (S3) connected between the circuit node (n1) and the reference level (Vref).

Abstract: A multi-mode RF power amplifier circuit that operates under dynamic power supply conditions. The power amplifier circuit operates under a high power mode and a low power mode. The multi-mode RF power amplifier includes a low power path and a high power path. Under the high power mode of operation, the high power path becomes active and the low power path becomes inactive. Each of the low power path and the high power path includes impedance matching networks and power amplifiers. Under either mode of operation, an inactive path will present at least five times higher input impedance than that of an active path. An impedance matching network connected between output terminals of the high power path and the low power path provides isolation between the output terminals of the high power path and the low power path.

Abstract: The present disclosure provides an audio signal amplifying circuit for an electronic device including a processing chip and a speaker. The audio signal amplifying circuit includes an amplifying circuit and an inverting circuit connected to the processing chip to get a first control signal and invert the first control signal to generate a second control signal. The first control signal and/or the second control signal are used to control the operation mode of the amplifying circuit to be in an amplifying mode or in a non-amplifying mode.

Abstract: Apparatus and methods for capacitive load reduction are disclosed. In one embodiment, a power amplifier system includes a plurality of power amplifiers and an envelope tracking module for generating a supply voltage for the power amplifiers. The power amplifier system further includes a switch and a decoupling capacitor operatively associated with a first power amplifier of the system. The switch is configured to electrically float an end of the decoupling capacitor when the first power amplifier is disabled so as to reduce capacitive loading of the envelope tracker and to operate as a dampening resistor when the power amplifier is enabled so as to improve the stability of the system.

Abstract: A communications device may include In-phase (I) power amplifiers configured to respectively generate I amplified signals, Quadrature (Q) power amplifiers configured to respectively generate Q amplified signals, I antennas respectively coupled to the I power amplifiers, and Q antennas respectively coupled to the Q power amplifiers. The communications device may also include an I controller coupled to the I power amplifiers and configured to selectively enable some of the I power amplifiers, and a Q controller coupled to the Q power amplifiers and configured to selectively enable some of the Q power amplifiers.

Abstract: A power amplifier includes: an input terminal at which an input signal is input; a first amplifier element amplifying the input signal; a second amplifier element amplifying an output signal of the first amplifier element; an output terminal from which an output signal of the second amplifier element is output; a matching circuit connected between an output of the second amplifier element and the output terminal; a first switch connected between an output of the first amplifier element and an input of the second amplifier element; and a second switch having a first end connected to the output of the first amplifier element, and a second end. The matching circuit includes a first inductor and a first capacitor connected in series between the output of the second amplifier element and a grounding point. The second end of the second switch is connected to a connecting point of the first inductor to the first capacitor.

Abstract: A reconfigurable amplifier comprising a first operational amplifier having two inputs and an output. A second operational amplifier having two inputs and an output. A plurality of switches coupled to the two inputs and the output of the first operational amplifier and the two inputs and the output of the second operational amplifier, wherein a first configuration of the plurality of switches causes the first operational amplifier and the second operational amplifier to operate as an inverting differential input amplifier, and wherein a second configuration of the plurality of switches causes the first operational amplifier and the second operational amplifier to operate as a non-inverting differential input instrumentation amplifier.

Abstract: Embodiments of the present invention provide a sample and hold amplifier that provides a preamplifier with a multi-stage zeroing architecture. The multi-stage architecture reduces effects of parasitic capacitance exponentially over prior attempts, which yields increased accuracy.

Abstract: Disclosed is a high-frequency power amplifier device capable of reducing a talk current. For example, the high-frequency power amplifier device has first and second power amplifier circuits, first and second transmission lines, and a region in which the first and second transmission lines are disposed close to each other. Either the first or second power amplifier circuit becomes activated in accordance with an output level. When the second power amplifier circuit is activated, currents flowing in the first and second transmission lines are transmitted in the same direction so that magnetic coupling occurs to strengthen each transmission line's magnetic force. When, on the other hand, the first power amplifier circuit is activated, currents flowing in the first and second transmission lines are transmitted in the opposite directions so that magnetic coupling occurs to weaken each transmission line's magnetic force.

Abstract: In general, according to one embodiment, a power amplifier includes an envelope detector, a limiter, and a combiner. The envelope detector is configured to sense an envelope component of an input signal. The limiter includes a PMOS (Positive channel Metal Oxide Semiconductor) transistor and an NMOS (Negative channel Metal Oxide Semiconductor) transistor. The PMOS transistor is configured to sense a phase component of the input signal. The phase component has a second-order distortion controlled within a predetermined range with respect to the input signal. The NMOS transistor is configured to sense a phase component of the input signal. The phase component has the same second-order distortion as the phase component sensed by the PMOS transistor. The combiner is configured to combine the envelope component sensed by the envelope detector and the phase component sensed by the limiter to generate an output signal.

Abstract: Apparatus and methods are disclosed, such as those involving a receiver device. One such apparatus includes an equalizer configured to process an input signal transmitted over a channel. The equalizer can include a programmable gain amplifier (PGA) block which includes an input node configured to receive the input signal; an output node; and a programmable gain amplifier (PGA). The PGA amplifies the input signal with an adjustable gain. The PGA block also includes a gain control block having an input electrically coupled to the input node. The gain control block is configured to adjust the gain of the PGA at least partly in response to the input signal from the input node such that the PGA generates an output signal with a substantially constant amplitude envelope to the output node.

Abstract: An amplification apparatus comprises: an amplifier circuit that amplifies an input audio signal and outputs an output audio signal; a first signal level determining unit that determines whether or not a signal level of the output audio signal outputted from the amplifier circuit is lower than a silence determination reference value; and a power-supply control unit that shifts the amplification apparatus from a power-on state to a power-off state, when it is determined that the signal level of the output audio signal outputted from the amplifier circuit is lower than the silence determination reference value.

Abstract: A communications device may include an In-phase (I) power amplifier configured to generate an I amplified signal, a Quadrature (Q) power amplifier configured to generate a Q amplified signal, an I digital-to-analog converter (DAC) configured to generate an I signal, and a Q DAC configured to generate a Q signal. The communications device may also include an I power supply circuit coupled to the I power amplifier and to the I DAC and configured to cause the I power amplifier to modulate an I carrier signal into the I amplified signal based upon the I signal, a Q power supply circuit coupled to the Q power amplifier and to the Q DAC and configured to cause the Q power amplifier to modulate a Q carrier signal into the Q amplified signal based upon the Q signal, and at least one antenna coupled to the I and Q power amplifiers.

Abstract: A method for offset compensation of a switched-capacitor amplifier comprises a reset phase (?1) and at least one working phase (?2). An output voltage (Vout) of the amplifier (amp) is fed according to a damped feedback loop gain (AB(1)) to a first amplifier input (ain1) in the reset phase (?1) as a function of an offset voltage (Voff). In the least one working phase (?2), an offset of the amplifier (amp) is compensated as a function of the offset voltage (Voff) by superimposing the output voltage (Vout) onto an input voltage (Vin) of the amplifier (amp) according to a loop gain (AB(2)).

Abstract: Disclosed herein is an improved power amplifier, referred to as a Switched-Capacitor Radio Frequency Power Amplification (SCPA). The SCPA may be fabricated with scale CMOS technology. The SCPA may include a plurality of stages, each stage including a storage device, a switch, and selection circuitry. Various combinations of the stages may produce an output signal based on characteristics of a reference signal to be amplified. The output from the stages may be combined to create an amplified approximate square wave. The amplified square wave may be filtered by output circuitry such as a bandpass matching circuit, resulting in an output signal that may be an amplified version of the reference signal.

Abstract: A multiple power mode amplifier includes: N amplifiers connected in series via switches; and a control circuit for controlling the N amplifiers in accordance with the output modes. P amplifiers out of the N amplifiers constitute a driver amplifier, and constitute a negative feedback amplifier including a feedback circuit for negatively feeding back its own output signal to its own input side. N?P amplifiers constitute a final stage amplifier connected in series to the negative feedback amplifier in a disconnectable manner. The control circuit is configured to: in a first output mode, disconnect the final stage amplifier from the negative feedback amplifier, and disable the feedback circuit; and in a second output mode, connect the final stage amplifier in series to the negative feedback amplifier, and enable the feedback circuit.