Abstract: A circuit (1) comprising eight DACs (2a to 2h), the analog outputs of which are applied to the non-inverting inputs (6) of corresponding op-amps (7a to 7h) for gaining up the analog output voltage from the corresponding DAC (2). The op-amps (7) are identical, and are configured in a non-inverting mode with a closed loop gain of two provided by first and second resistors (R1) and (R2). Primary outputs (8) of the op-amps (7) are coupled to output pins (9a to 9h) of the circuit (1). The second resistors (R2) couple primary inverting inputs (12) of the op-amps (7) to a common lo voltage reference rail (14), which is coupled to a true ground reference pin (15) through a coupling wire (16)which exhibit a combined inherent resistance (Rp). The voltage reference on the common voltage reference rail (14) varies with time as the output signals of the pa-amps (7) vary, and would thus result in cross-talk between the DACs (2a to 2h).

Abstract: Level shifting and amplified level shifting circuit topologies are provided that include two or more level shifting or amplified level shifting circuits. The level shifting circuits receive a variable and fixed input and generate a variable and fixed output that are level shifted with respect to the input signals. The amplified level shifting circuits receive a variable and fixed input and generate a variable and fixed output that are level shifted and amplified with respect to the input signals. These circuits may be utilized to form a detection circuit that detects a difference in the output signals.

Abstract: A circuit in accordance with the invention comprises a differential amplifier; and a direct current (DC) source coupled with the differential amplifier. The DC source generates a direct current that is communicated in substantially predetermined portions to multiple inverting input terminals of the differential amplifier. The direct current is applied so as to shift a common-mode voltage of electrical signals that are processed by the differential amplifier. The shift in the common-mode voltage is proportional to the direct current generated by the DC source.

Abstract: A balanced amplifier comprising a pair of voltage-to-current converters including a first input terminal, a second input terminal, a first output terminal and a second output terminal to convert an input voltage applied to the first input terminal into an output current output from each of the first output terminal and the second output terminal, the second input terminal and the second output terminal of one of the converters being connected to the second input terminal and the second output terminal of the other of the converters to cancel common-mode components each other and extract differential-mode components.

Abstract: Broadband driver for signals that are transmitted in different frequency ranges, comprising: (a) a first broadband driver circuit (19) for driving first signals having signal frequencies that lie in a first frequency range; (b) a second broadband driver circuit (24) for driving second signals having signal frequencies that lie in a second frequency range; (c) where at least one of the two broadband driver circuits (19) has a frequency-dependent positive-feedback circuit (44) for impedance synthesis of a frequency-dependent output impedance (Zout) of the broadband driver circuit (19), and where the output impedance (Zout) has a different value in the first frequency range than in the second frequency range.

Abstract: There is disclosed an improved differential amplifier (20) having a feedback loop that generates an amplified output signal (Vout) from an input signal (Vin) supplied by a preceding stage. It comprises an input matching circuit (11) connected to said preceding stage, a buffer (22) and an amplification section (12) connected in series in the direct amplification line, a first amplifier (16), a RC network (17?) and a second amplifier (23) connected in series in a parallel loop between the outputs and the inputs of the amplification section that generate the feedback signal. The role of said buffer and second amplifier associated in a dedicated direct and feedback signal combining block (21) is to respectively isolate the input signal and the feedback signal from the summing nodes (A?,B?) at the amplification section inputs. As a result, the summation of the input signal and the feedback signal is improved, the DC component of the output signal is filtered out in order to significantly reduce the DC offset.

Abstract: An amplifier (AMP) is provided with a pair of choppers (CHPi,CHPo) in order to reduce the DC-offset and the noise produced by the amplifier (AMP). To obtain an optimal noise reduction the pair of choppers (CHPi,CHPo) operate on a high frequency. As a result the DC-offset cancellation is not optimal because a so-called charge injection of the switches in the pair of choppers (CHPi,CHPo) produces a DC-offset. To overcome this problem the amplifier (AMP) is further provided with further offset cancellation means which are for example formed by a further pair of choppers (CHPfi,CHPfo). This further pair of choppers (CHPfi,CHPfo) operates on a relatively low frequency. The combination of the pair of choppers (CHPi,CHPo) and the further pair of choppers (CHPfi,CHPfo) guarantees an optimal DC-offset cancellation as well as an optimal noise cancellation.

Abstract: An integrated current-to-voltage conversion circuit converts a first current to an output voltage representative of the first current. The circuit includes a first contact pad and second and third contact pads capable of being coupled across a first resistor. A first operational amplifier has a first input coupled to the first contact pad for producing a first voltage thereat, a second input for receiving a reference voltage, and a first output coupled to the third contact pad. A second voltage appears at the third contact pad. A second operational amplifier has a second output at which a third voltage appears, a first input coupled to the second output, and a second input coupled to the second contact pad. The output voltage is substantially equal to the difference between the second and third voltages.

Abstract: The present invention provides a switchable gain amplifier comprising a high-pass filter pole. The switchable gain amplifier comprises first and second input nodes for receiving first and second components of a differential input signal. A first input terminal of a first differential amplifier is coupled to the first input node, and a first input terminal of a second differential amplifier is coupled to the second input node. A first variable resistance is coupled between the first input terminal of the first differential amplifier and a second input terminal of the first differential amplifier. A second variable resistance is coupled between the first input terminal of the second differential amplifier and a second input terminal of the second differential amplifier. A differential capacitor is coupled between the second input terminal of the first differential amplifier and the second input terminal of the second differential amplifier.

Abstract: In the hold phase, two negative feedback circuits constituted by the negative feedback capacitors 6p and 6m and two positive feedback circuits constituted by positive feedback capacitors are provided between an input terminal and an output terminal of an operational amplifier. Here, in a sampling phase before a hold phase, charges according an input signal V1p is stored in each of the capacitors, and charges according to an input signal V1p are stored in each of the capacitors. As a result, a gain of the switched capacitor amplifier circuit is derived from (Ca+C)/(Ca?Cx) wherein Ca indicates an electrostatic capacitance of the negative feedback capacitors, and Cx indicates an electrostatic capacitance of the positive feedback capacitors, and thus the gain can be increased without significantly increasing an electrostatic capacitance ratio.

Abstract: A translinear amplifier is disclosed. A loop amplifier drives the bases of the input and output transistor pairs from the differential collector voltage of the input pair. The loop amplifier contains a third differential pair (a gain pair). The tail current of the gain pair is inversely related to the tail current of the input pair, such that loop amplifier gain remains stable when the transconductance of the input pair changes (due, e.g., to input gain changes). In one embodiment, a linear-in-dB interface is provided that adjusts input pair tail current exponentially (and gain pair tail current exponentially and inversely) to linear voltage changes at a gain input.

Abstract: A balanced amplifier comprising a pair of voltage-to-current converters including a first input terminal, a second input terminal, a first output terminal and a second output terminal to convert an input voltage applied to the first input terminal into an output current output from each of the first output terminal and the second output terminal, the second input terminal and the second output terminal of one of the converters being connected to the second input terminal and the second output terminal of the other of the converters to cancel common-mode components each other and extract differential-mode components.

Abstract: The invention provides an amplifier circuit made by digital CMOS processes, the amplifier circuit comprising a main operational amplifier with at least one input and at least one output and a feedback loop including a non-linear gateoxide capacitor, wherein a voltage control means is connected to the main operational amplifier to provide a voltage difference between the output common mode voltage and the input common mode voltage of the main operational amplifier to apply a DC biasing voltage across the non-linear gateoxide capacitor sufficient to operate the non-linear gateoxide capacitor in a bias range where the capacity of the none-linear gateoxide capacitor is almost independent of the applied voltage comprising the bias voltage plus a signal voltage.

Abstract: An operational amplifier arrangement (OAA) includes a differential output stage (OS), input terminals of which are coupled to respective output terminals of a preceding stage (A2, A3), said operational amplifier arrangement (OAA) further includes a quiescent current control circuit (QCCC) coupled between said output stage (OS) and said preceding stage (A2, A3) and adapted to control the quiescent current of said differential output stage (OS) by commonly and simultaneously tuning respective input offset voltages (VoffA2, VoffA3) of said preceding stage (A2, A3), is characterised in that said quiescent current control circuit (QCCC) is adapted to digitally and off-line tune said input offset voltages of said preceding stage.

Abstract: A power amplifier includes a comparator (COMP) to which an input signal is applied, a digital buffer (BUF) coupled via a feedback low-pass filter (LPFB) to a second input terminal (Cin2) of the comparator (COMP). An unstable loop is thereby created with an oscillation frequency related to the bandwidth of the feedback low-pass filter. In the presence of an input signal this self-oscillation frequency linearizes the system resulting in a power amplifier with excellent power efficiency. In a differential version two of these self-oscillating loops are provided. The coupling of the two loops thereby withholds the high-frequency self-oscillation from the load.

Abstract: Systems and methods are provided for selecting an input impedance of a preamplifier device. Multiple feedback paths are provided to an amplifier device of the preamplifier. The feedback paths are selectable to switch feedback paths in and out to configure the preamplifier to the desired input impedance. The desired input impedance is selected to match the input impedance of the input signal system to optimize the performance of the preamplifier.

Abstract: In the hold phase, two negative feedback circuits constituted by the negative feedback capacitors 6p and 6m and two positive feedback circuits constituted by positive feedback capacitors are provided between an input terminal and an output terminal of an operational amplifier. Here, in a sampling phase before a hold phase, charges according an input signal V1p is stored in each of the capacitors, and charges according to an input signal V1p are stored in each of the capacitors. As a result, a gain of the switched capacitor amplifier circuit is derived from (Ca+C)/(Ca?Cx) wherein Ca indicates an electrostatic capacitance of the negative feedback capacitors, and Cx indicates an electrostatic capacitance of the positive feedback capacitors, and thus the gain can be increased without significantly increasing an electrostatic capacitance ratio.

Abstract: An operational amplifier having an adjustable input offset is provided that can improve dynamic performance by allowing processing of the input signal in continuous-time. The amplifier circuit comprises an input source and an operational amplifier configured with an adjustable input offset circuit. The adjustable input offset circuit enables cancellation of the offset error from any input sources prior to being translated or gained up by the operational amplifier, thus improving the dynamic range of the operational amplifier. The adjustable input offset circuit can be configured within a signal path of an auto-zero loop of the operational amplifier, or with a continuous-time implementation.

Abstract: The signal amplifier of this invention includes a noise amplifier that amplifies a difference between a first ground potential and a second ground potential, and an adding amplifier that superposes an analog input signal on an output potential of the noise amplifier, and amplifies a difference between the first ground potential and a potential having the analog input signal and the output potential superposed. Thus, the adding amplifier superposes the noises amplified by the noise amplifier on the analog input signal, and thereafter amplifies the difference between the first ground potential and the potential thus superposed. Thereby, the signal amplifier is able to amplify only the analog input signal, without amplifying the noises of the first ground potential or the second ground potential.

Abstract: A switched capacitor amplifier includes a pair of output capacitors, providing high throughput suitable for pipestaged circuit applications. During operation, the amplifiers may generate an evaluation output once per clock cycle. During a first clock cycle, one of the two output capacitors holds an evaluation potential to be output from the amplifier and the second output capacitor both precharges and evaluates. During a second clock cycle, the roles of the output capacitors reverse and the second output capacitor holds the evaluation potential and the first output capacitor precharges and evaluates. The invention is suitable for use with a variety of amplifier topologies.

Abstract: The amplifier device contains a first amplifier element having a first input and a first output. The first output is fed back via a negative feedback path to the input. The negative feedback path contains a controlled current source which brings about a reduction in the noise and also a real finite input impedance.

Abstract: A nested transimpedance amplifier (TIA) circuit includes a zero-order TIA having an input and an output. A first operational amplifier (opamp) has an input that communicates with the output of the zero-order TIA and an output. A first feedback resistor has one end that communicates with the input of the zero-order TIA and an opposite end that communicates with the output of the first opamp. A capacitor has one end that communicates with the input of the zero-order TIA. The gain-bandwidth product of the nested TIA is increased. Differential mode TIAs also have increased gain-bandwidth products.

Abstract: An input buffer amplifier has a symmetrical centroidal layout. The input buffer amplifier includes two half differential amplifiers that have substantially identical layouts. Each half amplifier receives the input signal in-parallel, and the outputs of the differential half amplifiers are wire-ored together. The input buffer amplifier is symmetrical about both horizontal and vertical lines of symmetry. Furthermore, FET devices forming the half amplifiers are interlaced to create the horizontal line of symmetry. The overall horizontal and vertical symmetry of the input buffer amplifier improves the device matching between differential signal paths. In other words, the devices in the half amplifiers that process the positive and negative components of the differential signal are more closely matched. This reduces differential offsets and common mode offsets that can occur when devices are not matched properly.

Abstract: An operational amplifier circuit is constituted by first and second inverted amplifier circuits (A1, A2) that receive first and second input signals, a third inverted amplifier circuit (A3) that receives an estimated common-mode output signal and an output signal from the first inverted amplifier circuit and outputs first and second output signals, a fourth inverted amplifier circuit (A4) that receives the estimated common-mode output signal and an output signal from the second inverted amplifier circuit and outputs third and fourth output signals, where the estimated common-mode output signal is generated by adding the second output signal and the fourth output signal, and first and second non-inverted amplifier circuits (A5, A6) that receive the estimated common-mode output signal and feed it back to the first and second inverted amplifier circuits.

Abstract: A system and apparatus for reducing offset voltages in folding amplifiers is disclosed. In one form, a folding amplifier for use in an analog-to-digital converter is provided. The folding amplifier includes a first current source operable to be coupled to a first differential pair and a second differential pair. The folding amplifier further includes a switching network coupled between the first current source and the first and second differential pairs and operable to enable coupling the first current source to at least one of the first differential pair and the second differential pair.

Abstract: A differential circuit with linearity correction loop includes a main differential amplifier 30, and a correction amplifier 20 having inputs coupled to the outputs of the main differential amplifier 30 through feedback paths. The output signals from the correction amplifier 20 are combined with the inputs to the main amplifier 30 such that a negative feedback loop is formed around the differential circuit. This feedback loop provides stability with only a minor power increase.

Abstract: An improved power-off, loop-through return-loss characteristic for a current feedback operational amplifier is provided by adding a positive feedback capacitor between the input and output of the operational amplifier. The positive feedback capacitor results in a negative capacitance input impedance for the operational amplifier that cancels stray capacitances at the input.

Abstract: In a reference voltage generating circuit, in a first period, only a first switch is OFF and a maximum peak value Vmax of an input signal In is held at a node A of a first capacitor 1. Next, in a second period, a second and a third switches are opened, and a voltage difference between the maximum peak value Vmax and a minimum peak value Vmin is held at a node C of a capacitor string. At this time, the voltage held in a second capacitor of the capacitor string is added to the voltage held in the first capacitor, and the voltage at a node B is output as a reference voltage Vref. The input signal In is applied to one input terminal of a differential amplifying circuit, and the reference voltage Vref is applied to the other input terminal. When the voltages held at the nodes A and C have stabilized, the reference voltage Vref is generated.

Abstract: In signal sources having a high impedance, typically a capacitive “signal source” such as capacitor-microphone capsules, it is common practice to use amplifier circuits that include means for coupling signals and determining operating points in addition to the actual amplifier having a high-resistance, non-inverting input. For setting the operating points of the signal source and the amplifier, separate bias-voltage sources are provided; these are coupled to the signal source and the non-inverting input, respectively, of the amplifier via a coupling impedance. At least one coupling capacitance is disposed in the signal path between the signal source and the non-inverting input of the amplifier. To attain a considerable noise gain without the disadvantage of very high idle times in this type of amplifier circuit, it is proposed that the coupling impedances be formed from a nonlinear resistance (D1, D2 or D3, D4) and an ohmic resistance (R3 or R4) connected thereto in series.

Abstract: A power amplifier circuit including first and second cascade-assembled operational amplifiers having respective first inputs receiving a reference voltage across a decoupling capacitor, respective outputs of which are connected across a load and are looped back on respective second inputs, the second input of the first amplifier receiving, from a coupling capacitor, an input voltage to be amplified, the amplifier circuit including means for separately charging the coupling and decoupling capacitors, upon circuit power-on, from an off or standby state, and means for inhibiting the amplifiers at least during the separate charging.

Abstract: An amplifying circuit includes a differential amplifier having a positive input end, a negative input end, a positive output end, and a negative output end; a first input impedance coupled between the negative input end and a first input signal; a second input impedance coupled between the positive input end and the first input signal; a third input impedance coupled between the negative input end and a second input signal; a fourth input impedance coupled between the positive input end and the second input signal; a first output impedance coupled between the negative input end and the positive output end; a second output impedance coupled between the negative input end and the negative output end; a third output impedance coupled between the positive input end and the positive output end; and a fourth output impedance coupled between the positive input end and the negative output end.

Abstract: A transimpedance amplifier uses a pseudo-differential configuration to improve dynamic range and to minimize signal distortion in an optical receiver. The optical receiver includes a photodiode that converts a light signal to an electrical current signal, and the transimpedance amplifier converts the electrical current signal to a pair of differential voltage signals for further processing. The electrical current signal is provided to the transimpedance amplifier by connecting a cathode of the photodiode to a first input amplifier via a DC-blocking capacitor and directly connecting an anode of the photodiode to a second input amplifier. The transimpedance amplifier includes a DC correction circuit that generates a correction current in response to an output of the first input amplifier. The correction current is added to an input of the second input amplifier to adjust a DC offset at an output of the second input amplifier.

Abstract: A power amplifier circuit comprising at least one first amplifier having a first input receiving an input voltage through at least one first coupling capacitor and connected to an output of the first amplifier, and having a second input, separate from the first input, receiving a reference voltage supplied by a time constant circuit comprising a decoupling capacitor, at least one first controllable switch connecting the first and second inputs.

Abstract: A high dynamic range amplifier circuit for amplifying pixel signals of an imager device is disclosed. The amplifier circuit uses a read-out scheme based on a charge recycling approach, where a pixel signal is first amplified with a low gain during a first amplification phase T1, and then the amplifier output is immediately recycled and the pixel signal amplified with a higher gain during a second amplification phase T2.

Abstract: Methods and circuitry for implementing monolithic high gain wideband amplifiers. The invention implements an amplifier with a limiter that also performs a signal dividing function. In a specific embodiment, the limiter is designed to make available two in-phase outputs that are then used to drive two gate input lines of a combiner distributed amplifier.

Abstract: The circuit comprises a differential amplifier (10) with two inputs and two outputs and a common mode regulation circuit. Between a regulation terminal (INCM) of the amplifier and the outputs there are connected a first (C1p) and a second (1m) capacitor and first (C3) and second (C4) capacitive means that by means of controlled switches (SW9-SW12) can be alternatively and simultaneousy connected in parallel with, respectively, the first ((C1p) and the second (C1m) capacitor or between a first (VB) and a second (Vref1) reference voltage terminal.

Abstract: A transimpedance amplifier selectively activates DC compensation to optimize a signal-to-noise ratio for an optical receiver. The optical receiver includes a photodiode that converts a light signal to an electrical current signal, and the transimpedance amplifier converts the electrical current signal to a pair of differential voltage signals for further processing. The electrical current signal is provided to the transimpedance amplifier by connecting a cathode of the photodiode to a first input amplifier via a DC blocking capacitor and by directly connecting an anode of the photodiode to a second input amplifier. The transimpedance amplifier includes a DC correction circuit that generates a correction current when an output of the first input amplifier exceeds a predefined threshold. The correction current is added to an input of the second input amplifier to adjust a DC offset at an output of the second input amplifier.

Abstract: A balanced amplifier comprising a pair of voltage-to-current converters including a first input terminal, a second input terminal, a first output terminal and a second output terminal to convert an input voltage applied to the first input terminal into an output current output from each of the first output terminal and the second output terminal, the second input terminal and the second output terminal of one of the converters being connected to the second input terminal and the second output terminal of the other of the converters to cancel common-mode components each other and extract differential-mode components.

Abstract: A balanced amplifier comprising a pair of voltage-to-current converters including a first input terminal, a second input terminal, a first output terminal and a second output terminal to convert an input voltage applied to the first input terminal into an output current output from each of the first output terminal and the second output terminal, the second input terminal and the second output terminal of one of the converters being connected to the second input terminal and the second output terminal of the other of the converters to cancel common-mode components each other and extract differential-mode components.

Abstract: A differential circuit with linearity correction loop includes a main differential amplifier 30, and a correction amplifier 20 having inputs coupled to the outputs of the main differential amplifier 30 through feedback paths. The output signals from the correction amplifier 20 are combined with the inputs to the main amplifier 30 such that a negative feedback loop is formed around the differential circuit. This feedback loop provides stability with only a minor power increase.

Abstract: The present invention is related to glitch reduction of the output of an auto-zero amplifier. The auto-zero amplifier may be used in a voltage regulator, and the glitch reduction in the auto-zero amplifier will result in reduced output ripple. The auto-zero amplifier stores an input offset during an auto-zero phase, so that the input offset can be corrected during an amplification phase. During the amplification phase, the gate-drain voltage of a first transistor is sampled onto a capacitor. During the auto-zero phase, the capacitor is used to maintain the same voltage across the gate-drain voltage of the first transistor that was present during the amplification phase. The capacitor maintains the gate-drain voltage during the auto-zero phase in order to compensate for the large step in voltage that would otherwise occur.

Abstract: Embodiments of the invention describe a method and apparatus for detecting valid differential signals with half the number of differential amplifiers required by conventional methods. By purposely mismatching an otherwise matched differential pair, a self-induced DC offset voltage is created and the additional circuitry required to generate external reference voltages according to conventional methods is eliminated. Embodiments of the invention also have improved noise rejection characteristics and enhanced high-speed capability compared to conventional circuits.

Abstract: Differential input fail safe circuitry is disclosed that detects missing or too low differential signals combined with a frequency lower than a frequency limit where a final safe condition is detected and signaled. The output signal form the fail safe circuitry is held in a given state that is an invalid representation of the differential input signal. A frequency detector, complementary offsetting auxiliary amplifiers with limit frequency roll offs are used to detect the fail safe condition. In addition a delay circuit is used that requires the fail safe condition to exist for some time before the fail safe circuit is active. Initialization circuitry ensures a proper power up conditions where the circuitry is enabled to detect the fail safe conditions and guarantees a reliable fail safe irrespective of the previous state of the signal.

Abstract: A balanced amplifier comprising a pair of voltage-to-current converters including a first input terminal, a second input terminal, a first output terminal and a second output terminal to convert an input voltage applied to the first input terminal into an output current output from each of the first output terminal and the second output terminal, the second input terminal and the second output terminal of one of the converters being connected to the second input terminal and the second output terminal of the other of the converters to cancel common-mode components each other and extract differential-mode components.

Abstract: A switched capacitor amplifier provides high gain and wide bandwidth using dynamic loading. Dynamic loading is used to reduce the capacitive load during a high gain phase (e.g., during a sampling phase) and to increase the capacitive loading during a high feedback factor phase (e.g., during a holding phase). The capacitive load may be provided by an external capacitive load such as a sampling capacitor of a subsequent stage or sampling device. A low feedback factor provides a high voltage gain and the lower capacitive load. A high feedback factor increases the effective bandwidth of the amplifier by compensating for a unit gain bandwidth reduction that is due to high capacitive loading.

Abstract: Provided is a circuit to perform single-ended to differential conversion while providing common-mode voltage control. The circuit includes a converter to convert a single-ended signal to a differential signal and a stabilizing circuit adapted to receive the differential signal. The stabilizing circuit includes a sensor configured to sense a common-mode voltage level of the differential signal and a comparator having an output port coupled to the converter. The comparator is configured to compare the differential signal common-mode voltage level with a reference signal common-mode voltage level and produce an adjusting signal based upon the comparison. The adjusting signal is applied to the converter via the output port and is operative to adjust a subsequent common-mode voltage level of the differential signal.

Abstract: A DC offset compensation circuit, and method thereof are capable of reducing the settling time of an output signal through fast compensation of a DC offset of the output signal although a DC voltage of an input signal varies in a closed loop operational amplifier. The DC offset compensation circuit of a closed loop operational amplifier includes a first closed loop operational amplifier and a second closed loop operational amplifier. The first closed loop operational amplifier amplifies an input signal based on a compensation voltage. The second closed loop operational amplifier amplifies a signal output from the first closed loop operational amplifier based on a reference voltage to generate a final output signal.

Abstract: An amplifying circuit receiving an input voltage and a reference voltage equal to a fraction of the circuit supply voltage, the reference voltage provided by a time constant circuit, including a circuit for, upon power-on, inhibiting the amplifying circuit for as long as the difference between the value of the provided reference voltage and the voltage at the output of the time constant circuit is greater than a determined threshold.

Abstract: A nested transimpedance amplifier (TIA) circuit includes a zero-order TIA having an input and an output. A first operational amplifier (opamp) has an input that communicates with the output of the zero-order TIA and an output. A first feedback resistor has one end that communicates with the input of the zero-order TIA and an opposite end that communicates with the output of the first opamp. A capacitor has one end that communicates with the input of the zero-order TIA. The gain-bandwidth product of the nested TIA is increased. Differential mode TIAs also have increased gain-bandwidth products.

Abstract: A wideband common-mode regulation circuit for coupling a differential amplifier, or more particularly a Low Voltage Differential Signaling driver LVDS, to a load generally constituted by a telecommunication transmission line. The regulation circuit only comprises a first resistive pair (R1, R2) to sense the common-mode voltage at the differential input terminals (INP, INN), a second resistive pair (R3, R4) to force the voltage across the load to a predetermined value, and an active device (OTA, INV) coupled between the junction points of the first and the second resistive pairs. The active device is an Operational Transconductance Amplifier (OTA) or, preferably, an inverter (INV). Owing to reduced number of non-dominant poles in the common-mode open-loop transfer characteristic, this regulation circuit provides common-mode loop stability for wide common-mode loop bandwidth.