Abstract: A semiconductor device includes first to fifth terminals, an amplification circuit including a first input end connectable to the first terminal and the third terminal, a second input end connectable to the second terminal and the fourth terminal, and an output end, and a switching circuit. The switching circuit is configured to switch between a first state in which the first input end is connected to the first terminal and insulated from the third terminal and the second input end is connected to the second terminal and insulated from the fourth terminal, and a second state in which the first input end is connected to the third terminal and insulated from the first terminal and the second input end is connected to the fourth terminal and insulated from the second terminal.

Abstract: A USB chip includes positive and negative data pins, first and second transceiver circuits, a switching circuit, and a control circuit. During a high-speed handshake stage, the control circuit controls the switching circuit to be in a second state to disconnect the positive and negative data pins from a first terminal impedance circuit and actuates the second transceiver circuit to transmit a second voltage signal via the positive and negative data pins alternately. During a high-speed transmission stage, the control circuit controls the switching circuit to be in a first state to connect the positive and negative data pins with the first terminal impedance circuit and actuates the first transceiver circuit to transmit a first voltage signal, which has a first voltage level lower than a voltage level of the second voltage signal, via the positive and negative data pins alternately.

Abstract: A chopper amplifying circuit employing a negative impedance compensation technique, including a differential input end, a first-level chopper switch, a first-level amplifying circuit, a second-level chopper switch, a second-level amplifying circuit, a negative impedance converting circuit, a negative feedback unit, an input capacitor, and a differential output end, is provided. The differential input end is connected to the first-level chopper switch. An output terminal of the first-level chopper switch is connected to the first-level amplifying circuit through the input capacitor. The first-level amplifying circuit is connected to the second-level chopper switch, which is connected to the second-level amplifying circuit. The second-level amplifying circuit is connected to the differential output end, and is also connected to a feedback input end of the first-level amplifying circuit through the negative feedback unit.

Abstract: Charge leakage/injection suppression circuitry within a capacitive programmable gain amplifier provides a low-impedance expulsion path for residual carriers within a feedback-path amplifier-mode switch and equalizes a voltage across a critical-leakage-path component of that amplifier-mode switch, reducing charge injection and leakage into an otherwise isolated amplifier input node to yield a low-noise amplifier output.

Abstract: Chopper amplifiers with low intermodulation distortion (IMD) are provided. To compensate for IMD, at least one distortion compensation channel is included in parallel with chopper amplifier circuitry of a main signal channel. Additionally, output selection switches are included for selecting between the output of the main signal path and the distortional compensation channel(s) over time to maintain the output current continuous. Such IMD compensation can be realized by filling in missing current of the main signal channel using the distortion compensation channel(s), or by using channel outputs only when they have settled current.

Abstract: A drive circuit includes: an input stage configured to receive a first input signal and a second input signal, and to output a first output signal and a common-mode output signal, where the first input signal and the second input signal are complementary signals; an output stage configured to receive the first output signal, and to output a second output signal; and a duty cycle adjusting subcircuit configured to determine the first output signal and the common-mode output signal or a signal obtained by inverting the common-mode output signal as a control signal, and to adjust a duty cycle of the second output signal. The drive circuit determines the common-mode output signal or the signal obtained by inverting the common-mode output signal as the control signal of the duty cycle adjusting subcircuit, and adjusts the duty cycle of the second output signal to tend to a preset value.

Abstract: A sense amplifier, a memory and a method for controlling the sense amplifier are provided. The sense amplifier includes: an amplification module, arranged to read data in a memory cell; and a control module, electrically connected to the amplification module. In a first offset compensation stage of the sense amplifier, the control module is arranged to configure the amplification module to include a first inverter and a second inverter, and each of the first inverter and the second inverter is an inverter an input terminal and an output terminal connected to each other; and in a second offset compensation stage of the sense amplifier, the control module is arranged to configure the amplification module to include a current mirror structure.

Abstract: An operational amplifier includes a first amplifying unit, a second amplifying unit, a current source, a first compensation capacitor, and a second compensation capacitor. The first amplifying unit includes a first input transistor, a second input transistor, a third input transistor, and a fourth input transistor. The second amplifying unit includes a fifth input transistor, a sixth input transistor, a seventh input transistor, and an eighth input transistor. One end of the first compensation capacitor is coupled to a drain of the seventh input transistor, and the other end of the first compensation capacitor is coupled to a gate of the eighth input transistor. One end of the second compensation capacitor is coupled to a drain of the eighth input transistor, and the other end of the second compensation capacitor is coupled to a gate of the seventh input transistor.

Abstract: Described embodiments include an integrated circuit for temperature gradient compensation of a bandgap voltage. A bandgap core circuit has a bandgap feedback input, a bandgap adjustment input and a bandgap reference output. A resistor is coupled between the bandgap adjustment input and a ground terminal. An offset and slope correction circuit has an offset correction output that is coupled to the bandgap adjustment input. A signal at the offset correction output is trimmed at an ambient temperature. A thermal error cancellation (TEC) circuit has a TEC output coupled to the bandgap adjustment input. The TEC circuit includes first and second temperature sensors that are located apart from each other. A signal at the TEC output is responsive to temperatures at the first and second temperature sensors. An amplifier has an amplifier input and an amplifier output. The amplifier input is coupled to the bandgap reference output.

Abstract: In an embodiment a current limiting circuit includes a circuit configured to detect when an input or output current of a DC to DC converter exceeds or falls below a threshold and a controller configured to store a first value representative of a level of an output voltage of the DC to DC converter in response to the input or output current exceeding or falling below a first threshold, store a second value representative of the level of the output voltage in response to the input or output current falling below a further threshold and modify a control signal based on the first and second values, wherein the control signal is modified based on the first and second values so that the control signal brings the output voltage to an intermediate voltage level between the level of the output voltage represented by the first value and the level of the output voltage represented by the second value.

Abstract: The present disclosure relates to a PUF apparatus for generating a persistent, random number. The random number is determined by selecting one or more PUF cells, each of which comprise a matched pair of capacitors that are of identical design, and determining a value that is accurately and reliably indicative of a random manufacturing difference between them, based in which the random number is generated. The random manufacturing differences between the capacitors creates the randomness in the generated random number. Furthermore, because the random manufacturing difference should be relatively stable over time, the generated random number should be persistent.

Abstract: A circuit includes a current mirror stage with a switch, that when made conductive, provides current between the input and the output of the current mirror stage through the switch. When the switch is nonconductive, current is not provided through the switch. The stage includes current mirror circuitry, that when the switch is nonconductive, provides current at the output that is mirrored from current provided to the input of the current mirror stage.

Abstract: An integrated circuit can include an amplifier coupled to receive an analog input signal, an anti-aliasing filter (AAF) coupled to an output of the amplifier, a buffer circuit coupled to an output of the AAF, a sigma-delta modulator configured to generate a digital data stream in response to an output of the buffer, and a plurality of chopping circuits nested within one another, including a first pair of chopping circuits having at least the amplifier disposed therebetween and configured to remove offset in the analog input signal, and a second pair of chopping circuit having at least the first pair of chopping circuits disposed therebetween. The amplifier, AAF, sigma-delta modulator, and chopping circuits can be formed with the same integrated circuit substrate. Corresponding methods and systems are also disclosed.

Abstract: A current sensing topology uses an amplifier with capacitively coupled inputs in feedback to sense the input offset of the amplifier, which can be compensated for during measurement. The amplifier with capacitively coupled inputs in feedback is used to: operate the amplifier in a region where the input common-mode specifications are relaxed, so that the feedback loop gain and/or bandwidth is higher; operate the sensor from the converter input voltage by employing high-PSRR (power supply rejection ratio) regulators to create a local, clean supply voltage, causing less disruption to the power grid in the switch area; sample the difference between the input voltage and the controller supply, and recreate that between the drain voltages of the power and replica switches; and compensate for power delivery network related (PDN-related) changes in the input voltage during current sensing.

Abstract: An amplifier circuit is capable of switching between a unipolar output voltage domain and a bipolar output voltage domain. The amplifier circuit comprises an operational amplifier with a feedback circuit that is configurable using switches. By controlling the switches, the amplifier's feedback circuit can switched between two different arrangements having a positive and a negative signal gain, respectively. The amplifier circuit is designed such that the noise gain is the same in both operating modes, allowing a single noise compensation approach to be used for both operating modes. Since configurability of the circuit is achieved using static switches, the amplifier circuit maintains high accuracy and experiences no appreciable impact on power consumption as a result of implementing the switching.

Abstract: The present disclosure discloses a switched capacitor amplifier apparatus for improving level-shifting. An amplifier includes input terminals and output terminals. Two capacitor circuits correspond to signal input terminals and signal output terminals and each includes a sampling capacitor circuit, a load capacitor and a level-shifting capacitor. The sampling capacitor circuit samples an input signal from one of the signal input terminals to one of the input terminals. An electrical charge neutralizing capacitor is coupled between the output terminals. The load capacitor and the level-shifting capacitor are charged according to an output from one of the output terminals in an estimation period. The level-shifting capacitor charges the load capacitor in a level-shifting period to generate an output signal at one of the signal output terminals.

Abstract: The present disclosure relates to chopper amplifier circuits with inherent chopper ripple suppression. Example implementations can realize a doubly utilized chopper amplifier circuit that is a current-saving circuit with a wake-up function that is capable of providing a self-wake signal in order to change into a fast, low-jitter/low-latency mode, and to provide a wake-up signal for a sleeping microprocessor or a system in response to signal changes.

Abstract: A method for a fast settling ripple reduction loop for high speed precision chopper amplifiers includes amplifying an input signal with a signal path to generate a first output, the signal path comprising chopping the input signal to generate a first chopper output, amplifying the first chopper output with an amplifier to generate an amplifier output and chopping the amplified output to generate a second chopper output. An output ripple of the first output is reduced with a Ripple Reduction Loop comprising chopping the second chopper output to generate a third chopper output, filtering the third chopper output with a filter to generate a Direct Current (DC) offset correction, and combining the DC offset correction with the amplifier output, wherein the third chopper output is driven to the output voltage of the filter and the RRL is disconnected from the low frequency signal path in response to a non-linear event.

Abstract: An amplifier including a P-channel transistor having current terminals coupled between a first node and a second node and having a control terminal coupled to a third node receiving an input voltage, an N-channel transistor having current terminals coupled between a fourth node developing an output voltage and a supply voltage reference and having a control terminal coupled to the second node, a first resistor coupled between the first node and a supply voltage, a second resistor coupled between the first and fourth nodes, and a current sink sinking current from the second node to the supply reference node. The amplifier may be converted to differential form for amplifying a differential input voltage. Current devices may be adjusted for common mode, and may be moved or added to improve headroom or to improve power supply rejection. Chopper circuits may be added to reduce 1/f noise.

Abstract: A slewing mitigation technique is presented where just the right amount of charge is provided at the switching instant to a switch capacitor circuit so that operational transconductance amplifier (OTA) does not need to provide high peak current. This eliminates slewing altogether and allows using OTAs with less static current for the same settling accuracy.

Abstract: An amplifier circuit includes multiple transistors, a set of input routing circuits, and a set of output routing circuits. Each output routing circuit corresponds to an input routing circuit. Each input routing circuit and its corresponding output routing circuit are controlled by one or more control signals. Each input routing circuit is configured to selectively connect each transistor of a transistor pair to a first input terminal of the amplifier circuit, a second input terminal of the amplifier circuit, or a third input terminal of the amplifier based on a value of the one or more control signals. Each output routing circuit is configured to selectively connect each transistor of the transistor pair to a first output terminal of the amplifier circuit, a second output terminal of the amplifier circuit, or a calibration circuit based on the value of the one or more control signals.

Abstract: A near-field communication (NFC) receiver includes first and second input terminals for receiving first and second input signals having a modulated signal portion and a carrier signal portion. The receiver includes a digital-to-analog converter (DAC), a mixer, a track-and-hold (T&H) circuit, an amplifier, and an analog-to-digital converter. The mixer has a first input coupled to receive the first and second input signals and a second input coupled to receive a low frequency current from the DAC. The mixer subtracts the carrier portion from the first and second input signals using the DAC current at a level determined using a DSP in a feedback loop to approximate the carrier. The T&H circuit has an input coupled to receive the combined current and an output to provide a series of output samples. The ADC is coupled to receive the amplified output signal and to provide a digital representation of the amplified output signal.

Abstract: An apparatus for canceling an input offset of a receiver including a differential amplification unit and a differential comparison unit in a distance sensing system includes: an output monitoring unit selectively monitoring differential outputs of the differential comparison unit and the differential amplification unit; a current type digital-analog conversion unit connected to each of an input terminal of the differential comparison unit and the input terminal of the differential amplification unit; and a control unit controlling the current type digital-analog conversion unit to reduce a difference in differential output of the differential comparison unit according to a comparison result for the difference of the monitored differential output of the differential comparison unit and controlling the current type digital-analog conversion unit to reduce the difference in differential output of the differential amplification unit according to the comparison result for the difference of the monitored differenti

Abstract: An interlocking adapter in one aspect of the present disclosure includes a current path, an electric load, a switch, and a controller. The controller turns on and off the switch in synchronization with a change of an alternating-current voltage received from an electric outlet of an electric apparatus in response to reception of an interlocking command signal from a working machine so as to supply a load current from the electric outlet to the electric load. The controller turns on and off the switch at a specified ratio of a time every ½ cycle of the alternating-current voltage.

Abstract: Enhanced operational amplifier trim circuitry and techniques are presented herein. In one implementation, a circuit includes a reference circuit configured to produce a set of reference voltages, and a digital-to-analog conversion (DAC) circuit. The DAC circuit comprises a plurality of transistor pairs, where each pair among the plurality of transistor pairs is configured to provide portions of adjustment currents for an operational amplifier based at least on the set of reference voltages and sizing among transistors of each pair. The circuit also includes drain switching elements coupled to drain terminals of the transistors of each pair and configured to selectively couple one or more of the portions of the adjustment currents to the operational amplifier in accordance with digital trim codes.

Abstract: A first correction voltage generation circuit provides a first positive or negative correction voltage for correcting an input voltage. A second correction voltage generation circuit provides a second correction voltage identical in polarity to the first correction voltage in accordance with the first correction voltage. The second correction voltage is generated to have a temperature coefficient reverse in polarity to a temperature coefficient of the first correction voltage.

Abstract: An offset-cancellation circuit having a first amplification stage with a gain of the first amplification stage and configured to receive an offset voltage of a first amplifier. A storage element is configured to be coupled to and decoupled from the first amplification stage and configured to store a potential difference output by the first amplification stage. The potential difference is determined by the offset voltage of the first amplifier and the gain of the first amplification stage. A second amplification stage is coupled to the storage element and configured to receive the potential difference from the storage element when the storage element is decoupled from the first amplification stage and configured to deliver an offset-cancellation current. The offset-cancellation current is determined by the potential difference and a gain of the second amplification stage.

Abstract: A signal measurement apparatus and signal measurement method are provided. The measurement apparatus includes a compensation signal generating circuit configured to generate a target compensation signal that reduces a carrier frequency component in a voltage signal that is input into an amplifier based on an output signal of the amplifier, and the amplifier amplifies the voltage signal to which the target compensation signal is applied, wherein the compensation signal generating circuit is configured to determine a signal value of a subsequent compensation signal based on a signal value of the output signal of the amplifier amplified by applying a previous compensation signal, when determining the target compensation signal.

Abstract: A common-mode rejection receiver including a first differential amplifier arranged to receive a differential signal including receiving a positive signal of the differential signal at a first non-inverting input port and receiving a negative signal of the differential signal at a first inverting input port, and output a first differentiated signal based on a voltage differential between the positive signal and the negative signal. A clamping circuit is arranged to limit a magnitude of the first differentiated signal to a pre-determined limit. A second differential amplifier is arranged to receive the positive signal at a second inverting input port and receive the negative signal at a second non-inverting input port, and output a second differentiated signal. A matching circuit is arranged to receive the second differentiated signal output and output a matched signal. A summing circuit adds the clamped signal and matched signal and outputs a receiver output signal.

Abstract: A coupling module can be used to communicate high speed signals between an optical transceiver and a processing module of an optical communication device, such as an optical line termination (OLT) or an optical network unit (ONU). The coupling module can adjust the common mode voltage level of a differential signal output by the optical transceiver to the common mode voltage level required by the processing module. In addition, the coupling module splits each of the differential output signals from the optical transceiver and passes the split signals to both a high-pass filter and a low-pass filter that are connected in parallel. An adapter module can be connected to the coupling module such that the coupling module can receive different differential signals from different optical transceivers.

Abstract: A method for inducing brain waves by sound has the following steps: receiving a first channel input signal and a second channel input signal; adjusting a volume gain of the first channel input signal to form a first channel output signal, wherein a format of the volume gain of the first channel output signal is a first wave format; adjusting a volume gain of the second channel input signal to form a second channel output signal, wherein a format of the volume gain of the second channel output signal is a second wave format, wherein there is a phase difference between the first wave format and the second wave format, wherein the formats of the first wave format and the second wave format are the same; outputting the first channel output signal to a first speaker; and outputting the second channel output signal to a second speaker.

Abstract: It is an object of one or more embodiments of the present disclosure to provide a single-inductor dual-output (SIDO), or single-inductor multiple-output (SIMO), Buck switching converter which can supply opposite polarity current to its outputs, through an inductor. It is a further object of one or more embodiments, when one output has an overshoot and the other output is below a reference, to enable discharging the overshoot output to the other output, resulting in a significant charge recycling and considerable increase in power efficiency. Still further, it is an object of one or more embodiments to improve output voltage ripple, as both outputs are being supplied at the same time, compared to prior art SIDO operation, where only one output is supplied for a given phase.

Abstract: The present invention discloses an AC impedance measurement circuit with a calibration function, which is characterized in that only one calibration impedance is needed, associated with a switch circuit. Based on the measurement results of the two calibration modes, an equivalent impedance of the switch circuit, circuit gain and phase offset can be calculated. Based on the above results, the equivalent impedance of the internal circuit is deducted from the measurement result of the measurement mode to accurately calculate an AC conductance and a phase of the AC conductance for impedance to be measured. In addition, by adjusting a phase difference between an input sine wave signal and a sampling clock signal, impedance of the same phase and impedance of the quadrature phase can be obtained, respectively, and the AC impedance and phase angle of the impedance to be measured can be calculated.

Abstract: A semiconductor circuitry includes a first circuitry having a differential transistor pair and a pair of current sources connected in series to the differential transistor pair, a pair of transmission lines connected to the differential transistor pair at the opposite side to the current sources, and a second circuitry, connected to a node between the differential transistor pair and the current sources, and configured to test operations of at least the differential transistor pair and a latter-stage circuity connected to the transmission lines, in the state where the current outputs of the pair of current sources are stopped.

Abstract: A capacitive trans-impedance amplifier comprising a voltage amplifier having an inverting input terminal for connection to an input current source. A feed-back capacitor is coupled between the inverting input terminal and the output terminal to accumulate charges received from the input current source and to generate a feed-back voltage accordingly. A calibration unit includes a calibration capacitor electrically coupled, via a calibration switch, to the inverting input terminal and electrically coupled to the feed-back capacitor. The calibration unit is operable to switch the calibration switch to a calibration state permitting a discharge of a quantity of charge from the calibration capacitor to the feed-back capacitor.

Abstract: A current sense loop includes an attenuator circuit, which has an embedded input chopper circuit, and an amplifier circuit, which has an output chopper circuit. The embedded input chopper has a first chopper input that is coupled to a first attenuator input, a first chopper output that is coupled to a first attenuator output, a second chopper input that is coupled to a second attenuator input, and a second chopper output that is coupled to a second attenuator output. An amplifier has a first input coupled to the first attenuator output and a second input coupled to the second attenuator output. An NFET has a gate coupled to the amplifier output, a source coupled to a ground plane, and a drain coupled to the second attenuator input.

Abstract: An electronic device test system includes a contactor having probe pairs with first and second conductive probes to couple to a respective conductive feature of a packaged electronic device or wafer die region. The system also includes a test circuit having a voltage source to provide a common mode voltage signal; a first buffer with a first input coupled to an output of the voltage source, an output coupled to a first conductive probe of a first probe pair, and a second input coupled to a second conductive probe of the first probe pair; and a second buffer with a first input coupled to the output of the voltage source, an output coupled to a first conductive probe of a second probe pair, and a second input coupled to a second conductive probe of the second probe pair.

Abstract: A circuit including an amplifier having an input and an output. The circuit also includes a current-to-voltage amplifier having an input. The circuit further includes a current mirror coupled between the output of the amplifier and the input of the current-to-voltage amplifier. The current mirror is configured to chop current flowing through the first current mirror.

Abstract: An amplifier arrangement comprises a sensor input and a first and a second amplifier. The first amplifier has a first amplifier output and a first input connected to a first reference potential terminal and a second input connected to the sensor input in a direct fashion and to the first amplifier output via a feedback path having a switched integration capacitor that is charged by the feedback path during a first switching phase and discharged during a second switching phase. The second amplifier has a second amplifier output, a first input connected to a second reference potential terminal and a second input. A first feedback capacitor is connected in-between two pairs of feedback switches. A second feedback capacitor is connected between the second amplifier output and the second input of the second amplifier. An impedance element is coupled between the second amplifier output and the sensor input.

Abstract: In one aspect, an embodiment of this invention comprises an energy storage device balancing apparatus. The energy storage device balancing apparatus comprises a balancing circuit and an alarm circuit. Both the balancing circuit and the alarm circuit are coupled to the energy storage device. The balancing circuit is configured to monitor a voltage of the energy storage cell and dissipate energy from the energy storage cell if the voltage is at or above a first reference voltage. The alarm circuit is configured to generate an alarm when the voltage of the energy storage cell is at or above a second reference voltage and dissipate energy from the energy storage cell when the voltage is at or above the second reference voltage.

Abstract: Chopper amplifiers with tracking of multiple input offsets are disclosed herein. In certain embodiments, a chopper amplifier includes chopper amplifier circuitry including an input chopping circuit, an amplification circuit, and an output chopping circuit electrically connected along a signal path. The amplification circuit includes two or more pairs of input transistors, from which a control circuit chooses a selected pair of input transistors to amplify an input signal. The chopper amplifier further incudes an offset correction circuit that senses the signal path to generate an input offset compensation signal for the amplification circuit. Furthermore, the offset correction circuit separately tracks an input offset of each of the two or more pairs of input transistors.

Abstract: A biocompatible recording system includes a number of input channels for acquiring electronic information from the neural system of a living being. The recording system includes a preamplifier and further amplifier stages. An input of a second amplifier stage is coupled to an output of the preamplifier. A low-pass filter having a capacitance multiplier is connected to the second amplifier stage. The preamplifier of the recording system is designed using P-MOS technology.

Abstract: An impedance measuring apparatus and method is disclosed. The impedance measuring apparatus includes one or more capacitors configured to receive an induced signal determined by an impedance of a measurement target, a controller configured to output a control signal to selectively turn a switch on or off based on whether a voltage value of the induced signal is included in a threshold range, and the switch configured to determine whether to set, to be a reference voltage value, a voltage value of a capacitor voltage signal output from the one or more capacitors based on the control signal.

Abstract: An amplifier device includes an amplifier circuitry, a controller circuitry, and an offset cancellation circuitry. The amplifier circuitry is configured to amplify a first input signal and a second input signal, in order to generate a first output signal and a second output signal. The controller circuitry is configured to generate a first control signal and a second control signal according to the first output signal and the second output signal. The offset cancellation circuitry is configured to provide a negative capacitor to the amplifier circuitry, and to adjust at least one current flowing through a circuit, which provides the negative capacitor, of the offset cancellation circuitry according to the first control signal and the second control signal, in order to cancel an offset of the amplifier circuitry.

Abstract: An integrated circuit, comprising an amplifier comprising a pair of inputs configured to receive a differential signal, a first resistor, a second resistor, wherein the first resistor and the second resistor are coupled in series with each other and coupled to a first input of the pair of inputs, a third resistor, a fourth resistor, wherein the third resistor and the fourth resistor are coupled in series with each other and coupled to a second input of the pair of inputs, and a first capacitor comprising a first end coupled to a first point between the first resistor and the second resistor, and a second end coupled to a second point between the third resistor and the fourth resistor, a second capacitor disposed between the first input and an output of the amplifier; and a third capacitor disposed between the second input and the output.

Abstract: A circuit arrangement comprises a first input node, a first output node, a sampling capacitor means and a first switching means being switchable between a first switching state and a second switching state. The first switching means is coupled to the sampling capacitor means, the first input node and the first output node in such a way that the sampling capacitor means is conductively connected to the first input node and disconnected from the first output node in the first switching state and the sampling capacitor means is disconnected from the first input node and conductively connected to the first output node in the second switching state. A first charge-storing element is coupled via a second switching means to the first input node in such a way that the charge-storing element is charged in the first switching state and discharged in the second switching state, thereby at least partly compensating current flow for charging the sampling capacitor means in the first switching state.

Abstract: A digital-to-analog converter (DAC) device includes a current-steering DAC circuitry and a calibration circuitry. The current-steering DAC circuitry generates a first signal according to multiple least significant bits of an input signal, and generates a second signal according to multiple most significant bits of the input signal. The calibration circuitry performs a non-binary search algorithm to generate a calibration signal in response to a comparison result of the first signal and the second signal, in order to calibrate the current-steering DAC circuitry according to the calibration signal.

Abstract: This disclosure describes techniques for selecting one of a plurality of modes in which to operate an amplifier. The techniques include configuring input routing circuitry, coupled to first and second inputs of the amplifier, based on the selected one of the plurality of modes; selectively applying a resistance to an output of the amplifier, using feedback routing circuitry, based on the selected one of the plurality of modes; and selectively applying one of a plurality of reference voltages, using reference voltage routing circuitry, coupled to the first and the second inputs of the amplifier, based on the selected one of the plurality of modes.

Abstract: Neuromodulation systems in accordance with embodiments of the invention can use a feed-forward common-mode cancellation (CMC) path to attenuate common-mode (CM) artifacts appearing at a voltage input, thus allowing for the simultaneous recording of neural data and stimulation of neurons. In several embodiments of the invention, the feed-forward CMC path is utilized to attenuate the common-mode swings at Vin,CM, which can restore the linear operation of the front-end for differential signals. In several embodiments, the neuromodulation system may utilize an anti-alias filter (AAF) that includes a duty-cycles resistor (DCR) switching at a first frequency f1, followed by a DCR switching at a second frequency f2. The AAF allows for a significantly reduced second frequency f2 that enables the multi-rate DCR to increase the maximum realizable resistance, which is dependent upon the frequency ratio f1/f2.

Abstract: A switched-capacitor converter is provided that includes an intermediate voltage generator having a flying capacitor. A sampling and hold circuit samples a top plate voltage for the flying capacitor and samples a bottom plate voltage for the flying capacitor to form an output voltage for the switched-capacitor converter.