With Periodic Switching Input-output (e.g., For Drift Correction) Patents (Class 330/9)
  • Patent number: 10243520
    Abstract: A fully balanced differential difference amplifier includes a first differential input stage that receives an input voltage and a second differential input stage that receives a common-mode voltage. A first resistive-degeneration group is coupled to the first differential input and a second resistive-degeneration group is coupled to the second differential input. A differential output stage generates an output voltage. A first switch is coupled in parallel to the first resistive-degeneration group and a second switch is coupled in parallel with the second resistive-degeneration group. The first and second switches are driven into the closed state when the voltage input assumes a first value such that said first input stage operates in the linear region, and are driven into the open state when the voltage input assumes a second value, higher than the first value, such that the first input stage operates in a non-linear region.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: March 26, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Andrea Barbieri, Sergio Pernici
  • Patent number: 10116268
    Abstract: The amplifier circuit includes a pair of differential input stages coupled to an output stage where both a selected input stage and an unselected input stage are active with one of either a differential input signal or a reference voltage. A switching network couples a first input differential signal to a first differential input stage and a reference voltage to a second differential input stage when an amplifier input signal is less than a threshold voltage. The switching circuit also couples the second input differential signal to the second differential input stage and the reference voltage to the first differential input stage when the amplifier input signal is greater than the threshold signal.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: October 30, 2018
    Assignee: Analog Devices Global
    Inventors: Sharad Vijaykumar, Gerard Mora-Puchalt
  • Patent number: 10090022
    Abstract: To provide a semiconductor device with a high output voltage. A gate of a first transistor is electrically connected to a first terminal through a first capacitor. A gate of a second transistor is electrically connected to a second terminal through a second capacitor. One of a source and a drain of a third transistor is electrically connected to the gate of the first transistor through a third capacitor. One of a source and a drain of a fourth transistor is electrically connected to the gate of the second transistor through a fourth capacitor. The other of the source and the drain of the third transistor and the other of the source and the drain of the fourth transistor are electrically connected to a high potential power source. A third terminal is electrically connected to one of a source and a drain of the second transistor.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: October 2, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Shionoiri, Tomoaki Atsumi, Kiyoshi Kato, Takanori Matsuzaki
  • Patent number: 10054619
    Abstract: Systems and methods are provided to measure a voltage across a two-state dipole. The systems and methods measure voltages across two measurement paths of operational circuitry at first and second sensor terminals. The operational circuitry is configured to decouple the first and second sensor terminal based on a dipole voltage. The systems and methods further estimate the dipole voltage based on the voltages of the two measurement paths.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: August 21, 2018
    Assignee: General Electric Company
    Inventors: Miguel Garcia Clemente, Philipp Leuner, Thomas Alois Zoels, Bertrand Bastien, Alvaro Jorge Mari Curbelo
  • Patent number: 10033331
    Abstract: An integrated circuit (IC) chip can include an operational amplifier with adjustable operational parameters. The IC chip can also include a trimming module configured to measure an output voltage of the operational amplifier in response to at least one of detecting that the operational amplifier has a positive supply voltage set to a level greater than a predetermined level and detecting a given common mode voltage at inverting and non-inverting inputs of the operational amplifier. The trimming module can also be configured to adjust the operational parameters of the operational amplifier based on the output voltage to trim the operational amplifier.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: July 24, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vadim Valerievich Ivanov, Jerry L. Doorenbos
  • Patent number: 10027285
    Abstract: In a semiconductor device according to related art, it is impossible to sufficiently correct an input offset of an operational amplifier.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: July 17, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Yusuke Tanabe
  • Patent number: 9998698
    Abstract: A hybrid bonded image sensor has a photodiode die with macrocells having at least one photodiode and a bond contact; a supporting circuitry die with multiple supercells, each supercell having at least one macrocell unit bonded to the bond contact of a macrocell of the photodiode die. Each macrocell unit has a reset transistor adapted to reset photodiodes of the photodiode die macrocell. Each supercell has a differential amplifier configurable to receive a noninverting input from a photodiode and an inverting input, the differential amplifier providing an output, each differential amplifier has an amplifier reset transistor coupled to the differential amplifier output and the inverting input; a first capacitor coupled between the differential amplifier output and the inverting input, and a second capacitor coupled between the inverting input and a signal ground. The first and second capacitor of embodiments has controllable capacitance to adjust gain.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: June 12, 2018
    Assignee: OmniVision Technologies, Inc.
    Inventor: Song Xue
  • Patent number: 9991858
    Abstract: A receiver includes a signal receiving part suitable for outputting a signal corresponding to a reception signal that is received through an input terminal, and controlling a DC voltage of a signal to be outputted, according to an offset signal, an amplifying part suitable for amplifying and outputting an output of the signal receiving part, and a feedback control part suitable for controlling the offset signal according to an output of the amplifying part.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: June 5, 2018
    Assignees: SK HYNIX INC., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Sungphil Choi, Mino Kim, Suhwan Kim, Deog-Kyoon Jeong
  • Patent number: 9924096
    Abstract: A hall sensor device includes: an amplifier configured to amplify a detection signal of a hall sensor; and a current supplier configured to provide a compensation current to a feedback line of the amplifier according to an offset of the detection signal, to cancel the offset.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: March 20, 2018
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Yo Sub Moon
  • Patent number: 9902789
    Abstract: The present invention relates to a method for preparing a hybrid supported metallocene catalyst. More specifically, the present invention relates to a method for preparing a hybrid supported metallocene catalyst by using two or more different types of metallocene compounds. One type of the metallocene compounds shows a high polymerization activity even when it is supported, and thus the catalyst has an excellent activity and can be utilized in the polymerization of olefinic polymers having ultra-high molecular weight. Based on the hybrid supported metallocene catalyst obtained according to the preparation method of the present invention, an olefinic polymer having high molecular weight and the desired physical property can be prepared.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: February 27, 2018
    Assignee: LG CHEM, LTD.
    Inventors: Dae Sik Hong, Heon Yong Kwon, Eun Kyoung Song, Yong Ho Lee, Kyung Jin Cho, Ki Soo Lee, Yi Young Choi
  • Patent number: 9893688
    Abstract: A differential amplifier has an inherent offset voltage. In many circuit applications, such as with a voltage to current converter circuit, it is important to nullify that offset voltage. A calibration circuit is provided to configured the differential amplifier to operate as a comparator with a common voltage applied to both inputs. The logic state of the output of the amplifier indicates whether the offset voltage is positive or negative. In response thereto, a trim current with a progressively increasing magnitude is injected into the amplifier and the amplifier output is monitored to detect a change in logic state. The magnitude of the trim current at the point where the logic state changes is the magnitude of trim current needed to nullify the voltage offset.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: February 13, 2018
    Assignee: STMicroelectronics, Inc.
    Inventor: Pavan Nallamothu
  • Patent number: 9735736
    Abstract: Apparatus and methods for reducing input bias current of electronic circuits are provided herein. In certain implementations, an electronic circuit includes a first input terminal, a second input terminal, an input circuit, and a plurality of input switches including at least a first input switch and a second input switch. The first input switch is electrically connected between the first input terminal and a first input of the input circuit, the second input switch is electrically connected between the second input terminal and a second input of the input circuit, and the first and second input switches can be opened and closed using a clock signal. The electronic circuit further includes a charge compensation circuit for compensating for charge injection through the first and second input switches during transitions of the clock signal.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: August 15, 2017
    Assignee: Analog Devices, Inc.
    Inventor: Yoshinori Kusuda
  • Patent number: 9712048
    Abstract: A computer-implementable control algorithm that measures: 1) the reactive power; 2) the power factor; 3) the voltage; and 4) the line frequency. The algorithm calculates the differential compensation capacitance required that is either positive (capacitance to be added), or negative (capacitance to be removed). The new compensation capacitance is calculated from the sum or difference of the differential compensation capacitance and the current compensation capacitance. The algorithm compares the capacitor switching bit pattern for the current compensation capacitance and the capacitor switching bit pattern for the new compensation capacitance, and selects a capacitor switching bit map accordingly. The capacitor switch combination for the new compensation capacitance is switched in incrementally according to the capacitor switching bit map. To reach the selected capacitor switch combination, only one switch is switched at a time to minimize the line transient noise.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: July 18, 2017
    Assignee: Edge Electrons Limited
    Inventor: Neal George Stewart
  • Patent number: 9682237
    Abstract: A successive approximation ADC made of a low voltage configurable differential amplifier and low voltage logic circuits which can convert a high voltage analog input to a digital equivalent. The differential amplifier can be configured as either an op amp or a comparator depending upon the mode of operation. An input capacitor C1 is switchably coupled to an electrode selected for voltage sampling. A switched capacitor array C2 is coupled across the differential amplifier input and output. A SAR coupled to the switched capacitor array provides a digital output corresponding to the sampled analog voltage. During a sampling interval and a charge transfer interval, the differential amplifier is configured as an op amp. During the transfer interval, the voltage on the input capacitor multiplied by the ratio C1/C2 is transferred to the switched capacitor array. During an analog to digital conversion interval, the ADC converts the analog voltage to an equivalent digital output.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: June 20, 2017
    Assignee: ALFRED E. MANN FOUNDATION FOR SCIENTIFIC RESEARCH
    Inventor: Edward K. F. Lee
  • Patent number: 9641142
    Abstract: One example includes a hot-swap control system. The system includes a sense resistor network provides a sense voltage in response to an output current. The system also includes a sense control circuit includes a chopper amplifier system arranged in a servo feedback arrangement to generate a monitoring voltage having an amplitude that is associated with the output current based on the sense voltage. A notch filter chopping stage filters out signal ripple in the chopper amplifier system across a unity-gain bandwidth of the chopper amplifier system, and a capacitive compensation network provides stability-compensation of the chopper amplifier system across the unity-gain bandwidth. A transconductance amplifier configured to compare the monitoring voltage with a predetermined reference voltage to generate a control voltage. The system further includes a power transistor configured to conduct the output current to an output based on the control voltage.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: May 2, 2017
    Assignee: Texas Instruments Incorporated
    Inventor: Sudheer Prasad
  • Patent number: 9634626
    Abstract: An instrumentation amplifier includes: a capacitive feedback closed-loop amplifier, an input capacitor charging module, a feedback capacitor discharging module, a noise separation module and a logic controller. The capacitive feedback closed-loop amplifier includes a fully differential operational amplifier, a first input capacitor, a second input capacitor, a first feedback capacitor and a second feedback capacitor. The input capacitor charging module is configured to charge the first input capacitor and the second input capacitor periodically. The feedback capacitor discharging module is configured to discharge the first feedback capacitor and the second feedback capacitor periodically. The noise separation module is configured to separate a noise from a signal using a chopping modulation technology. The logic controller is connected to the input capacitor charging module, the feedback capacitor discharging module and the noise separation module to control the modules to operate.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: April 25, 2017
    Assignee: Vango Technologies, Inc.
    Inventor: Shupeng Zhong
  • Patent number: 9621116
    Abstract: According to one embodiment, there is provided an active load circuit including a first transistor, a second transistor, a first resistor, a second resistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a line. The third transistor is placed between the first transistor and the first reference node. The fourth transistor is placed between the second transistor and the first reference node. The seventh transistor is placed between the fifth transistor and the first reference node. The eighth transistor is placed between the sixth transistor and the first reference node. A line connecting a fifth node between the fifth transistor and the seventh transistor and a sixth node between the sixth transistor and the eighth transistor.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: April 11, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Rui Ito, Naohiro Matsui
  • Patent number: 9614481
    Abstract: Apparatus and methods for digitally-assisted feedback offset correction are provided herein. In certain configurations, an amplifier includes amplification circuitry for providing amplification to an input signal and chopping circuitry for compensating for an input offset voltage of the amplifier. Additionally, the amplifier further includes a digitally-assisted feedback offset correction circuit, which includes a chopping ripple detection circuit, a feedback-path chopping circuit, a digital correction control circuit, and an offset correction circuit. The chopping ripple detection circuit generates a detected ripple signal based on detecting an output ripple of the amplifier. Additionally, the feedback-path chopping circuit demodulates the detected ripple signal using the amplifier's chopping clock signal.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: April 4, 2017
    Assignee: ANALOG DEVICES, INC.
    Inventor: Evgueni Ivanov
  • Patent number: 9595922
    Abstract: Various apparatuses and methods are described where a signal is amplified using a chopper amplifier arrangement, and ripples caused by said chopper amplifier arrangement are reduced. In some cases, this reduction of ripples is performed by controlling a voltage offset of an amplifier of said chopper amplifier arrangement. In other embodiments, a detection of ripples or a chopping of the chopper amplifier arrangement is at least temporarily disabled.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: March 14, 2017
    Assignee: Infineon Technologies AG
    Inventors: Gerhard Maderbacher, Mario Motz
  • Patent number: 9590575
    Abstract: A differential amplifier stage may include: a first transistor having a gate terminal; a second transistor having a gate terminal; and a voltage limiting circuit coupled to the gate terminals of the first and second transistors, wherein the voltage limiting circuit limits a gate voltage supplied to at least one of the gate terminals of the first and second transistors.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: March 7, 2017
    Assignee: INTEL DEUTSCHLAND GMBH
    Inventors: José Moreira, Stephan Leuschner
  • Patent number: 9584079
    Abstract: There is provided an operational amplifier which is operable as well when an operating voltage decreases without creating a range where a circuit would not operate or reducing circuit gain. High-pass filters 102-105 provide output signals therefrom to bias-set input nodes of differential amplifiers Gm1-Gm4 to a potential within a common-mode range in which the respective differential amplifiers Gm1-Gm4 are operable. In this manner, the respective differential amplifiers Gm1-Gm4 can be operated effectively regardless of the possible decrease in a supply voltage, enabling normal amplifying operation. In addition, reduction in gain due to the reduced operational voltage is avoided. Therefore, it is preferably applicable to the application where digital and analog circuits are loaded together on the same IC chip.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: February 28, 2017
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventor: Shinichi Ouchi
  • Patent number: 9564859
    Abstract: One example includes an OP-AMP circuit system. The system includes a signal amplification path comprising a signal amplification path comprising a signal amplifier and an output stage. The signal amplification path can be configured to amplify an input voltage received at an input to provide an output voltage via the output stage. The system also includes an offset-reduction path coupled to the input of the signal amplification path and to an output of the signal amplifier. The offset-reduction path includes a transconductance amplifier and at least one chopper that are configured to mitigate noise in the signal amplification path and a noise-filtering feedback path configured to provide chopper feedback with respect to an offset voltage associated with the offset-reduction path, the noise-filtering feedback path comprising a feedback path input coupled to the input of the transconductance amplifier via a resistor.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: February 7, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vadim V. Ivanov, Vaibhav Kumar, Munaf H. Shaik
  • Patent number: 9515623
    Abstract: An embodiment of an amplifier includes N (N>1) switch-mode power amplifier (SMPA) branches. Each SMPA branch includes two drive signal inputs and one SMPA branch output. A module coupled to the amplifier samples an input RF signal, and produces combinations of drive signals based on the samples. When an SMPA branch receives a first combination of drive signals, it produces an output signal at a first voltage level. Conversely, when the SMPA branch receives a different second combination of drive signals, it produces the output signal at a different second voltage level. Finally, when the SMPA branch receives a different third combination of drive signals, it produces the output signal at a voltage level of substantially zero. A combiner combines the output signals from all of the SMPA branches to produce a combined output signal that may have, at any given time, one of 2*N+1 quantization states.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: December 6, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jean-Christophe Nanan, Jean-Jacques Bouny, Cedric Cassan, Joseph Staudinger, Hugues Beaulaton
  • Patent number: 9503115
    Abstract: A circuit for implementing a time-interleaved analog-to-digital converter is described. The circuit comprises a sampling clock generator configured to receive a reference clock signal having a first frequency.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: November 22, 2016
    Assignee: XILINX, INC.
    Inventors: Jaewook Shin, Hiva Hedayati
  • Patent number: 9496833
    Abstract: Apparatus and methods for multi-channel autozero and chopper amplifiers are provided herein. In certain configurations, an amplifier includes at least three channels that operate using multiple phases, including at least a non-inverting chop phase, an inverting chop phase, and an autozero phase. The amplifier further includes an autozero and chopping timing control circuit, which at least partially interleaves or staggers timing of the channels' phases. For example, in certain configurations, when one or more of the channels are being autozeroed at a certain time instance, at least some of the remaining channels operate in the non-inverting chop phase or the inverting chop phase.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: November 15, 2016
    Assignee: ANALOG DEVICES, INC.
    Inventor: Yoshinori Kusuda
  • Patent number: 9484870
    Abstract: A device includes an operational-amplifier including an amplifier-part amplifying signals and transmitting amplified signals to a first and a second nodes, and an output-part connected to the first and second nodes and outputting signals from a first and a second outputs. The device includes a first and a second chopper switches and a first and second phase-compensation capacity elements. A first capacitance switch switches between a first connection-state and a second connection-state. In the first connection-state, the first phase-compensation-capacity element is connected between the first node and the first output and the second phase-compensation-capacity element is connected between the second node and the second-output. In the second connection state, the first phase-compensation-capacity element is connected between the second-node and the second output and the second phase-compensation-capacity element is connected between the first node and the first output.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: November 1, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinji Nakatsuka, Shigeo Imai, Yosuke Ogawa
  • Patent number: 9479125
    Abstract: A system and method for adjusting a common mode output voltage in an instrumentation amplifier is provided. In one aspect, the common mode output voltage is increased or decreased with respect to the common mode input voltage to enable high amplification of the signal input to the instrumentation amplifier. Moreover, the common mode output voltage can be driven to (or approximately to) a target voltage value such as, but not limited to, half the supply, even if the common mode input voltage is close to supply or ground rail voltage. Thus, a high amplification of the differential input voltage can be obtained and utilized for various applications requiring rail to rail input.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: October 25, 2016
    Assignee: SEMTECH CORPORATION
    Inventors: Olivier Nys, Francois Krummenacher
  • Patent number: 9467094
    Abstract: Phase-dependent operational amplifiers (“op-amps”) employing phase-based frequency compensation, and related systems and methods are disclosed. A phase-dependent op-amp is provided configured to provide output voltage based on inputs switched by clock signal. The op-amp employs a frequency compensation system having multiple frequency compensation circuits. The frequency compensation circuit corresponding to the clock phase is selected by selection circuit and coupled to the voltage output node. The op-amp charges each frequency compensation circuit during the clock phase to store voltage approximately equal to output voltage. When transitioning to a clock phase, output voltage of op-amp does not have to charge frequency compensation circuit. Voltage of frequency compensation circuit stored during clock phase is approximately equal to output voltage of op-amp for clock phase.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: October 11, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Burt Lee Price, Dhaval Rajeshbhai Shah, Yeshwant Nagaraj Kolla
  • Patent number: 9461595
    Abstract: An apparatus includes voltage-to-current conversion circuitry comprising a first voltage-to-current converter and a second voltage-to-current converter. The apparatus also includes a capacitor coupled to the first voltage-to-current converter and to the second voltage-to-current converter.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: October 4, 2016
    Assignee: QUALCOMM INCOPORATED
    Inventors: Jingxue Lu, Matthew David Sienko, Ankit Srivastava, Manu Mishra
  • Patent number: 9432004
    Abstract: Gain offset and voltage offset compensation for a controllable gain element of a circuit is effected in response to a gain offset value and voltage offset value. A current operating condition of the circuit is sensed and compared to a nominal operating condition. If the current operating condition is outside the nominal operating condition by more than a threshold, a calibration operation to set the gain and voltage offset values is performed. The gain offset value is selected as a function of the sensed current operating condition. With respect to the voltage offset, differential input terminals of the controllable gain element are shunted and the output is measured. The measured output value of the controllable gain element is applied as the voltage offset value. The operating conditions at issue may be one or more of supply voltage and temperature.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: August 30, 2016
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Felix Kim, Mark A. Lysinger, Scott V. Ho
  • Patent number: 9413568
    Abstract: According to at least one example embodiment a two phase calibration approach is employed for calibrating an input/output interface having multiple single-ended receivers. During a first phase, amplifier offset calibration is applied to each of the multiple single-ended receivers. During a second phase, reference voltage calibration is applied to a single-ended receiver of the multiple single-ended receivers to determine a calibration reference voltage value. The calibration reference voltage value is then employed in each of the multiple single-ended receivers during an active phase of the input/output interface.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: August 9, 2016
    Assignee: Cavium, Inc.
    Inventors: Omer O. Yildirim, David Lin, Scott E. Meninger
  • Patent number: 9398891
    Abstract: An embodiment of an auscultation device can be constructed using, at least in part, electronic components to provide improved acquisition, processing, and communication of sound signals. An input device can be used for detecting sounds, and electrical signals representing the sounds can be processed and transmitted via one or more of a plurality of substantially contemporaneously available wired and/or wireless communications interfaces. Bluetooth and/or another form of wireless communication can be employed. Such embodiments can employ, at least in part, one or more of several commercially available wired and/or wireless receiver devices, such as, without limitation, headsets and headphones, mobile phones, PDAs and/or other handheld devices, desktop, laptop, palmtop, and/or tablet computers, speakers and/or other conventional and/or specifically configured computer devices and/or electronic devices.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: July 26, 2016
    Assignee: TIBA MEDICAL, INC.
    Inventor: Merat Bagha
  • Patent number: 9385677
    Abstract: A differential amplifier circuit and method having a feed-in network coupling an input signal to an intermediate signal. An amplifier amplifies the intermediate signal by a gain factor to output an output signal to a load network. A feedback network configured in a negative feedback topology and couples the output signal to the intermediate signal. A gain enhancing network is configured in a positive feedback topology and couples the output signal to the intermediate signal. Preferably, an impedance of the gain enhancing network is approximately equal to an impedance of a parallel connection of the feed-in network and the feedback network times the gain factor minus one.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: July 5, 2016
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 9361485
    Abstract: A transmission device for two electric pulse measurement signals includes a first measurement signal input, a second measurement signal input, a differential measurement signal output and a signal converter. The first measurement signal input serves for receiving a first single-ended measurement signal, the second measurement signal input for receiving a second single-ended measurement signal, wherein the signal converter is implemented, when receiving a first one of the single-ended measurement signals, to convert either the first single-ended measurement signal or the second single-ended measurement signal into a combined differential measurement signal and provide the same at the differential measurement signal output. Here, the differential measurement signal includes a first differential portion which may be allocated to the first single-ended measurement signal and a second differential portion which may be allocated to the second single-ended measurement signal.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: June 7, 2016
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Matthias Voelker, Johann Hauer
  • Patent number: 9351653
    Abstract: A biopotential monitoring device includes a configurable receiver circuit having a plurality of channels for receiving a plurality of biopotential signals from a biological tissue via a plurality of inputs coupled with the electrodes, and each channel substantially removes a DC (direct current) offset from a corresponding one of the biopotential signals and then band-pass amplifies such corresponding biopotential signal at a configurable gain and particular frequency range based on frequency control signals. The device further includes a controller circuit for receiving commands for configuring frequency characteristics of each biopotential signal. The controller automatically generates the frequency control signals based on such commands and outputs such frequency control signals to the configurable receiver circuit. The controller outputs a representation of each biopotential signal to an analyzer device that is configured to analyze such biopotential signal.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: May 31, 2016
    Assignee: Intan Technologies, LLC
    Inventor: Reid R. Harrison
  • Patent number: 9356568
    Abstract: Apparatus and methods for chopper amplifiers are provided herein. In certain configurations, a chopper amplifier includes at least one differential transistor bank including a selection circuit and a plurality of transistors. The selection circuit can select a first portion of the transistors for operation in a first transistor group and a second portion of the transistors for operation in a second transistor group. During calibration, the chopper amplifier's input offset can be observed for different transistor configurations of the differential transistor banks. Although the transistors of a particular bank can be designed to have about the same drive-strength and/or geometry, the chopper amplifier can have a different input offset in different transistor configurations due to manufacturing mismatch between transistors, such as process variation.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: May 31, 2016
    Assignee: ANALOG DEVICES, INC.
    Inventors: Jie Zhou, Arthur J. Kalb, Mark D. Reisiger
  • Patent number: 9319039
    Abstract: In some embodiments, a differential amplifier with duty cycle correction is provided.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: April 19, 2016
    Assignee: Intel Corporation
    Inventors: Eduard Roytman, Mahalingam Nagarajan, Pradeep R. Vempada
  • Patent number: 9312825
    Abstract: An amplifier input stage comprising first and second p-type transistors, wherein sources of the first and second p-type transistors are connected to a first node, a drain of the first p-type transistor is connected to a first output of the amplifier input stage, a drain of the second p-type transistor is connected to a second output of the amplifier input stage, a gate of the first p-type transistor is configured to receive a first signal of an input stage differential input signal and a gate of the second p-type transistor is configured to receive a second signal of the input stage differential input signal; first and second n-type transistors, wherein sources of the first and second n-type transistors are connected to a second node, a drain of the first n-type transistor is connected to a third output of the amplifier input stage, a drain of the second n-type transistor is connected to a fourth output of the amplifier input stage, a gate of the first n-type transistor is configured to receive the first sign
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: April 12, 2016
    Assignee: Analog Devices Global
    Inventor: Roberto S. Maurino
  • Patent number: 9312898
    Abstract: An apparatus for handling a received signal comprises a reception device, a mixer unit and a compensating unit. The reception unit can receive a received signal. The received signal has at least one signal component at a first frequency. Furthermore, the mixer unit can combine the received signal and a compensating signal using at least one active element in order to obtain a compensated received signal. In addition, the mixer unit can produce a mixer output signal on the basis of the compensated received signal and a local oscillator signal. In this case, the mixer output signal has a signal component, corresponding to the at least one signal component of the received signal, at a second frequency. The first frequency is higher than the second frequency.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: April 12, 2016
    Assignee: Infineon Technologies AG
    Inventor: Christoph Wagner
  • Patent number: 9294037
    Abstract: Apparatus and methods for autozero amplifiers are provided herein. In certain configurations, an autozero amplifier includes at least three transconductance stages and an autozero timing control circuit configured to control an autozero sequence of the transconductance stages. The autozero timing control circuit can stagger autozeroing of the transconductance stages, such that a relatively small amount of the amplifier's amplification circuitry is connected to or disconnected from the amplifier's signal path at any given time. For example, in certain configurations, when one of the transconductance stages in autozeroed over a particular time interval, the remaining transconductance stages can operate in parallel to provide amplification during that time interval.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: March 22, 2016
    Assignee: Analog Devices Global
    Inventors: Roberto S. Maurino, Venkata Aruna Srikanth Nittala, Abhilasha Kawle, Sanjay Rajasekhar
  • Patent number: 9294049
    Abstract: Fast-settling capacitive-coupled amplifiers are disclosed. The amplifiers use two Capacitive Coupled paths embedded in a Multipath Hybrid Nested Miller Compensation topology. One path is a direct high frequency path and the other path is a slower stabilization path. This combination results in a flat frequency response to and through the chopper frequency, and a fast settling response. Various exemplary embodiments are disclosed, including operational amplifier and instrumentation amplifier configurations.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: March 22, 2016
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Johan Hendrik Huijsing, Qinwen Fan, Kofi Afolabi Anthony Makinwa, Daihong Fu, Jun Wu, Lixia Zhou
  • Patent number: 9264080
    Abstract: In an embodiment, an apparatus includes a component of a receiver path to receive and process an incoming signal. At least one element of the component is controllable based on a DC output of the component, to compensate for a second order intermodulation product of the apparatus. As one example, the component is a differential amplifier including a first transistor and a second transistor.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: February 16, 2016
    Assignee: Silicon Laboratories Inc.
    Inventor: Mark May
  • Patent number: 9257950
    Abstract: A charge preamplifier for converting an electric charge generated in a charge source sensor into a voltage signal, including: a phase inverting amplifier including an input related to the charge source sensor, and an output for providing the voltage signal; a storage capacitor connected between the input and the output of the phase inverting amplifier; a reset system connected to the input of the phase inverting amplifier, for providing to the storage capacitor a discharging current as a function of a control signal, and a control element including: a first input connected to the output of the phase inverting amplifier, for withdrawing the voltage signal, a second input subjected to a reference voltage, a set of components configured and arranged to generate a control signal proportional to the deviation between the voltage signal and the reference voltage, the proportionality coefficient being lower than one in a high frequency band, an output connected to the reset system to provide thereto the control sign
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: February 9, 2016
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Francis Lugiez, Olivier Gevin
  • Patent number: 9252726
    Abstract: An operational amplifier has two paths, a high frequency path and a low frequency path. In addition, it has three main sections of stages. A stage converts input voltage to an amplified output voltage, a stage converting an input voltage in to an output current and a final stage where the outputs of the two previous sections are supplied as inputs. Among them, the final stage acts as a voltage follower to a signal applied to its plus (+) input and as a transimpedance amplifier for a signal applied to its minus input (?). In this configuration, a path for low frequencies and a path for high frequencies are created in a single operational amplifier.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: February 2, 2016
    Inventor: Takashi Narita
  • Patent number: 9252830
    Abstract: A communications device may include a first transmit path having a first band pass filter operating at a first frequency band having a first bandwidth, and a second transmit path having a second band pass filter operating at a second frequency band having a second bandwidth. The second frequency band may be adjacent the first frequency band and the second bandwidth may be less than the first bandwidth. The communications device may include a third receive path operating at a third frequency band having a third bandwidth, and a fourth receive path operating at a fourth frequency band having a fourth bandwidth. The fourth frequency band may be adjacent the third frequency band, and the fourth bandwidth may be less than the third bandwidth.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: February 2, 2016
    Assignee: BlackBerry Limited
    Inventors: Brian Bremer, Jyothsna Kunduru
  • Patent number: 9246446
    Abstract: A chopper amplifier includes a chopper modulator to modulate a certain detection signal and a bias voltage by a certain control signal and output a chopper modulation signal, a first differential amplifier to differentially amplify the chopper modulation signal from the chopper modulator and output a differential modulation signal, a chopper demodulator to demodulate the differential modulation signal from the first differential amplifier by the control signal and output a demodulation signal, a second differential amplifier to extract a detection signal component from the demodulation signal, and a plurality of filters connected at an input terminal of the second differential amplifier and having different cutoff frequencies from each other relative to the demodulation signal.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: January 26, 2016
    Assignee: RICOH COMPANY, LTD.
    Inventor: Takeshi Nagahisa
  • Patent number: 9219451
    Abstract: Provided is an operational amplifier circuit capable of operating with lower current consumption. An amplifier stage, a FIR filter, and a sample and hold circuit are connected in series, thus enabling reduction of an input offset voltage and amplification of an input signal voltage without using an integral circuit. Current consumption of the operational amplifier circuit is reduced because the integral circuit is not used.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: December 22, 2015
    Assignee: SEIKO INSTRUMENTS INC.
    Inventor: Tsutomu Tomioka
  • Patent number: 9207696
    Abstract: Multi-stage amplifiers, such as linear regulators, configured to provide a constant output voltage subject to load transients, are described. The multi-stage amplifier includes a first amplification stage which activates or deactivates a first output stage in response to an input voltage at an input node. The first output stage is configured to source a current at an output node of the multi-stage amplifier from a high potential, when activated. Furthermore, the multi-stage amplifier includes a second amplification stage configured to activate or to deactivate a second output stage in response to the input voltage at the input node. The second output stage is configured to sink a current at the output node of the multi-stage amplifier to a low potential, when activated. The first amplification stage and the second amplification stage are configured to activate the first output stage and the Second output stage in a mutually exclusive manner.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: December 8, 2015
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Frank Kronmueller, Ambreesh Bhattad
  • Patent number: 9203351
    Abstract: A system for cancelling offset includes a gain circuit. The gain circuit may include a transistor circuit connected to a pair of input nodes and configured to convert an input signal to an output signal so that the output signal has a gain compared with the input signal. The gain circuit also may include a pair of output nodes configured to receive the output signal from the transistor circuit. The gain circuit is configured to cause a voltage change at one of the output nodes relative to another output node, in response to the gain circuit receiving a feedback offset correction signal. This effectively cancels at least a portion of an offset in the output signal.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 1, 2015
    Assignee: MegaChips Corporation
    Inventors: Takahiro Itagaki, Sarath Chandrasekhar Venkatesh Kumar, Anand Gopalan, Shankarram Athreya
  • Patent number: 9203352
    Abstract: A circuit includes a first amplifier circuit and a second amplifier circuit. The second amplifier circuit includes an input coupled to an output of the first amplifier circuit. A pass gate circuit is coupled between first and second inputs of the first amplifier circuit. The pass gate circuit is on during calibration of the second amplifier circuit to short together signals at the first and the second inputs of the first amplifier circuit. The pass gate circuit is off during a normal mode of the first and the second amplifier circuits.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: December 1, 2015
    Assignee: Altera Corporation
    Inventors: Tim Tri Hoang, Rabindranath Balasubramanian