With Periodic Switching Input-output (e.g., For Drift Correction) Patents (Class 330/9)
  • Patent number: 9160116
    Abstract: The present invention discloses a connector, including: a first interface, a second interface, and a signal boost circuit, where at least one of the first interface and the second interface includes a power supply contact head, and the power supply contact head is configured to power the signal boost circuit; and a casing, where the signal boost circuit is arranged inside the casing and concatenated between the first interface and the second interface, and the signal boost circuit performs signal amplification processing on a differential signal received by the first interface and outputs the signal over the second interface, and the first interface and the second interface are arranged on different surfaces outside the casing. Further, the present invention discloses an electronic device.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: October 13, 2015
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Congtu Xiao, Zhigang Zhao
  • Patent number: 9148098
    Abstract: A differential amplifier circuit includes a differential amplification unit suitable for amplifying difference between signals of an input terminal and a complementary input terminal, receiving the same voltage level through the input terminal and the complementary input terminal at a measurement period, and receiving an input signal and a complementary input signal through the input terminal and the complementary input terminal, respectively, at an operation period, an offset control unit suitable for generating offset information using an output of the differential amplification unit at the measurement period, and an offset compensation unit suitable for compensating for an offset of the differential amplification unit in response to the offset information.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: September 29, 2015
    Assignee: SK Hynix Inc.
    Inventor: Hyung-Soo Kim
  • Patent number: 9136808
    Abstract: A signal processing apparatus and method are disclosed. A common mode signal extraction unit is configured to extract a common mode signal from input signals inputted to a differential amplifier. A common mode signal adjustment unit is configured to adjust a gain and a phase of the common mode signal and to output the adjusted common mode signal to the differential amplifier. An optimal set determination unit is configured to determine an optimal gain and phase to be applied to the common mode signal based on an output signal from the differential amplifier.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: September 15, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: JongPal Kim
  • Patent number: 9130518
    Abstract: A circuit including an amplifier, a transistor, and first, second and third resistances. The amplifier includes an input and an output. The amplifier receives an input signal. A cycle of the input signal includes first and second pulses. The input signal is asymmetrical such that the first pulse has a different peak magnitude than the second pulse. The transistor is connected to the input and the output. The first, second, and third resistances are each connected to the input of the amplifier. The second resistance receives a first input voltage. The third resistance receives a second input voltage. The input signal is based on the first resistance and the first and second input voltages. The amplifier corrects some asymmetry of the input signal to provide an output signal. An amount of asymmetry of the output signal is based on (i) the input signal, and (ii) a state of the transistor.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: September 8, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Steve Fang, Qiang Tang, Myung Jae Yoo
  • Patent number: 9130519
    Abstract: A method and apparatus for combined linear, low-noise buffer and sampler for ADC (analog to digital converter) have been disclosed. In one implementation components contributing to sampling errors are included in a feedback path.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 8, 2015
    Assignee: Apple Inc.
    Inventors: Mansour Keramat, Ali Meaamar
  • Patent number: 9118305
    Abstract: In one example implementation, the present disclosure provides a direct current (DC) restoration circuit for restoring the DC component of a synchronization signal provided over an alternating current (AC) coupled link from a transmitting circuit to a receiving circuit. During a period of inactivity in the synchronization signal, the synchronization signal may experience a drift towards the common mode, and may affect the ability for the synchronization signal to properly trigger the receiving circuit. The DC restoration circuit is configured to hold the synchronization signal steady during the period of inactivity, and allow the AC component of the synchronization signal pass through to the receiving circuit during the period of activity to alleviate the problem of baseline drift in the synchronization signal.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: August 25, 2015
    Assignee: ANALOG DEVICES, INC.
    Inventors: Brad P. Jeffries, Peter Derounian
  • Patent number: 9110121
    Abstract: A spinning current Hall sensor configured to provide a sequence of input signals in response to a bias current being applied to a sequence of terminals of Hall sensing elements of the Hall sensor, the terminals of the Halls sensing elements configured to be interconnected in a sequence of configurations between a bias current supply and ground, with the bias current supply being connected to and applying the bias current to a different one of the terminals of each configuration. A chopping circuit demodulates the sequence of input signals to provide a corresponding sequence of demodulated positive and negative signals, with a residual offset calibration signal for the spinning current Hall sensor being based on the sequence of demodulated positive and negative signals.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: August 18, 2015
    Assignee: Infineon Technologies AG
    Inventor: Mario Motz
  • Patent number: 9077301
    Abstract: A circuit can include operational amplifier having a first input, a second input, and an output, first and second resistors in series between the output of the op-amp and a ground, and multiple switches configurable to toggle the circuit between a positive phase and a negative phase.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: July 7, 2015
    Assignee: KEITHLEY INSTRUMENTS, INC.
    Inventor: Wayne C. Goeke
  • Patent number: 9071208
    Abstract: A signal amplification circuit includes an input terminal; a first chopper modulation circuit; a first amplifier having an amplification circuit and a chopper demodulation circuit, a capacitance feedback circuit having a second chopper modulation circuit, a first switch constituting a voltage follower circuit with the amplification circuit; a second switch; a second amplifier to convert the differential output signal from the second output terminal into a single-end signal; and a filter to pass at least a predetermined frequency component of the chopping frequency from the single-end signal from the second amplifier to output an output signal of the signal amplification circuit.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: June 30, 2015
    Assignee: RICOH COMPANY, LTD.
    Inventor: Takeshi Nagahisa
  • Patent number: 9071209
    Abstract: Disclosed are systems, apparatus, and methods for sensing currents conducted via an electrode. In various embodiments, an apparatus may include an operational amplifier including a first input terminal, a second input terminal, and an output terminal. The first input terminal may be configured to electrically couple with the electrode. The apparatus may further include a feedback circuit coupling the output terminal of the operational amplifier to the first input terminal. The feedback circuit may comprise a plurality of transistor devices configured to generate a feedback current based on a voltage value of the output terminal. The plurality of transistors may be further configured to provide the feedback current to the first input terminal. The apparatus may also include a voltage source coupled to the second input terminal and configured to maintain a substantially constant voltage at the second input terminal.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: June 30, 2015
    Assignee: Intan Technologies, LLC
    Inventor: Reid R. Harrison
  • Publication number: 20150137884
    Abstract: An amplifier circuit is disclosed comprising: an input terminal configured to receive a radio frequency input signal; an output terminal configured to provide a radio frequency output signal; a first transistor having a first collector, a first emitter, and a first base; a second transistor having a second collector, a second emitter, and a second base; a bypass switch; and a controller. The first base is connected to the input terminal and the second emitter. The first collector is connected to a circuit voltage supply and the output terminal The first emitter is connected to ground and to the second base. The second collector is connected to a collector voltage supply. The bypass switch is connected between the first base and the output terminal.
    Type: Application
    Filed: November 13, 2014
    Publication date: May 21, 2015
    Inventors: Kathiravan Kishnamurthi, Yumin Lu
  • Patent number: 9035696
    Abstract: An amplifier includes a first input terminal, a second input terminal, a TIA, and a compensation circuit. The TIA includes a first transistor, a second transistor, a first current source connected to the first input terminal and an emitter of the first transistor, a second current source connected to the second input terminal and an emitter of the second transistor, a first load resistor connected to a collector of the first transistor, and a second load resistor connected to a collector of the second transistor. A bias voltage is supplied to bases of the first and second transistors, the compensation circuit adjusts a first load current and a second load current based on voltage signals, and the TIA outputs the voltage signals based on collector voltages of the first and second transistors.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: May 19, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Yoshiyuki Sugimoto
  • Patent number: 9036211
    Abstract: A light emitting apparatus including: a plurality of light emitting elements; a drive circuit including a transistor and a capacitor having one end connected to a gate of the transistor; and a signal supply circuit for receiving a digital gradation signal and outputting an analog voltage signal to the drive circuit, including a computation circuit configured to correct the input digital gradation signal to generate a corrected digital gradation signal, in which the drive circuit is configured to conduct an auto-zero operation which reduce the gate-source voltage of the transistor to a threshold voltage by flowing the drain current to the capacitor, and the computation circuit is configured to generate the corrected digital gradation signal by multiplying a correction coefficient to the input digital gradation signal subtracted by a particular signal common to the plurality of light emitting elements.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: May 19, 2015
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Takanori Yamashita, Masami Iseki, Kouji Ikeda, Shuhei Takahashi
  • Publication number: 20150130536
    Abstract: A mixer comprising a ladder having at least two resistances arranged in series and an input configured to receive an input signal and apply it across the ladder, said ladder including an output arrangement comprising at least three branches, a first branch branching from a first end of the ladder, a second branch branching from between the at least two resistances and a third branch branching from a second end of the ladder, opposite the first end, each branch including a switch for controlling a connection between its branch and an output.
    Type: Application
    Filed: October 28, 2014
    Publication date: May 14, 2015
    Inventor: Robert Hendrikus Margaretha van Veldhoven
  • Patent number: 9030150
    Abstract: A method and circuit arrangement for controlling the motor current in an electric motor, in particular a stepper motor, by a chopper method is provided. In the method/circuit arrangement, the motor is operated with a coil current that follows a target coil current substantially more accurately at least at the zero crossing of the coil current. The method/circuit arrangement provides a good symmetry of the sinusoidal wave shape of the coil current with respect to the zero crossing of the coil current. The method is achieved in particular by the active control of the coil current both in the direction of a predefined target coil current and opposite the direction of the predefined target coil current with respect to upper or lower desired current values and a lowering or increasing of the upper or lower desired current values.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: May 12, 2015
    Assignee: Trinamic Motion Control GmbH & Co. KG
    Inventor: Bernhard Dwersteg
  • Patent number: 9000824
    Abstract: An offset cancel circuit includes a first amplifying section, a second amplifying section, a third resistor connected between a non-inverting input terminal of the first amplifying section and a non-inverting input terminal of the second amplifying section, and a current source. In the offset cancel circuit, the current source causes a constant current to flow through the third resistor to cancel an offset voltage from output signals of first and second amplifying sections, the constant current corresponding to the offset voltage contained in first and second output signals output from a bridge resistance type sensor.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: April 7, 2015
    Assignee: Yamaha Corporation
    Inventors: Masato Miyazaki, Toshio Maejima
  • Patent number: 8975963
    Abstract: A circuit includes a first amplifier configured to amplify an input signal to generate an output signal. An offset sensor is configured to sense DC offset based on the output signal, where the offset sensor includes a second amplifier configured to generate an offset reduction signal for the first amplifier based on the sensed DC offset. A T-network in the circuit includes at least three resistors coupled to provide a feedback connection between the input signal and the output signal for the first amplifier and to receive the offset reduction signal to mitigate DC offset in the first amplifier. Since this method reduces the low-frequency component of the signal, it also shapes and reduces the flicker noise.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 10, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Ajit Sharma, Kemal S. Demirci
  • Publication number: 20150054576
    Abstract: Apparatus and methods for chopper amplifiers are provided herein. In certain configurations, a chopper amplifier includes at least one differential transistor bank including a selection circuit and a plurality of transistors. The selection circuit can select a first portion of the transistors for operation in a first transistor group and a second portion of the transistors for operation in a second transistor group. During calibration, the chopper amplifier's input offset can be observed for different transistor configurations of the differential transistor banks. Although the transistors of a particular bank can be designed to have about the same drive-strength and/or geometry, the chopper amplifier can have a different input offset in different transistor configurations due to manufacturing mismatch between transistors, such as process variation.
    Type: Application
    Filed: July 17, 2014
    Publication date: February 26, 2015
    Inventors: Jie Zhou, Arthur J. Kalb, Mark D. Reisiger
  • Patent number: 8963631
    Abstract: A signal amplifying circuit of a communication device is disclosed including: an amplifier comprising a first input terminal, a second input terminal, and an output terminal, wherein the input terminal is coupled with a fixed voltage level; a feedback circuit coupled with the second input terminal and the output terminal of the amplifier; a digital-to-analog converter (DAC); a signal processing circuit; a switch for selectively coupling the second input terminal of the amplifier with the DAC or the signal processing circuit; and a control unit coupled with the switch for controlling the operations of the switch.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: February 24, 2015
    Assignee: Realtek Semiconductor Inc.
    Inventor: Shan-Chih Tsou
  • Patent number: 8963637
    Abstract: A semiconductor device capable of achieving high speed performance in addition to correction of differential offset and a communication device provided with the semiconductor device are provided. For example, there are provided: a variable gain type differential amplifier circuit VGA1 which receives a gain setting signal ASET, which amplifies differential input signals INP and INN by a gain indicated by the gain setting signal, and which outputs differential output signals OUTP? and OTUN?; and an offset correcting circuit unit OFCBK1 which cancels an offset voltage (VOF and VOFO) generated in the VGA1. Here, the OFCBK1 cancels an output offset voltage VOFO (which results in an input offset voltage VOF) by receiving the ASET, generating a correction voltage changed in accordance with the gain, and adding the correction voltage to the OUTP? and OUTN?.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: February 24, 2015
    Assignee: Hitachi, Ltd
    Inventors: Hideki Koba, Keiki Watanabe, Kouji Fukuda
  • Patent number: 8952751
    Abstract: A method of operating an amplifier circuit having a pre-charge phase and a sample/conversion phase includes, during a pre-charge phase, charging first and second capacitors to first and second bias voltages. The first capacitor is coupled to a first input of an amplifier circuit, which has a second input and an output. The second capacitor is coupled to the second input. During a sample/conversion phase, the first input of the amplifier circuit is coupled to an input signal through the first capacitor to level-shift the input signal according to the first bias voltage and the output of the amplifier is coupled to the second input through the second capacitor to level shift a feedback signal according to the second bias voltage.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: February 10, 2015
    Assignee: Silicon Laboratories Inc.
    Inventors: Axel Thomsen, Gang Yuan
  • Publication number: 20150038870
    Abstract: An integrated circuit chip and method for EEG monitoring. In one embodiment, the integrated circuit chip includes an Analog Front End cell in communication with an electrode and a Classification Processor wherein a signal received from the electrode is processed by the Classification Engine cell and designated as seizure or non-seizure. In another embodiment, the Analog Front End cell includes an amplifier cell in communication with an electrode; and an ASPU cell in communication with the amplifier cell. In yet another embodiment, the Classification Processor includes a DBE Channel Controller cell; a Feature Extraction Engine Processor cell, and a Classification Engine cell in communication with the Feature Extraction Engine Processor cells and the DBE Channel Controller cell.
    Type: Application
    Filed: February 15, 2013
    Publication date: February 5, 2015
    Inventors: Jerald Yoo, Anantha P. Chandrakasan, Long Yan, Dina Reda El-Damak, Ali Hossam Shoeb, Muhammad Awais Bin Altaf
  • Patent number: 8941438
    Abstract: An apparatus for limiting the bandwidth of an amplifier provides for the design of an input impedance, a feedback impedance, and a load impedance such that the load impedance is proportional to the sum of the input impedance and feedback impedance. A sampling circuit has a load impedance including a resistor and capacitor in series to reduce the effective amplifier transconductance, which decreases bandwidth without increasing noise density or making this circuit more difficult to drive than a conventional circuit.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: January 27, 2015
    Assignee: Analog Devices, Inc.
    Inventors: Ronald A. Kapusta, Youn-Jae Kook
  • Patent number: 8941439
    Abstract: One embodiment relates to an apparatus configured to cancel charge injected on a node of a differential pair of nodes. A dummy circuit element can inject charge on an inverted node to cancel charge injected on a non-inverted node by a switch when the switch is switched off. In addition, another dummy circuit element can inject charge on the non-inverted node to cancel charge injected on the inverted node by another switch when the other switch is switched off. These dummy circuits elements can be cross-coupled.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: January 27, 2015
    Assignee: Analog Devices, Inc.
    Inventors: Scott G. Bardsley, Peter Derounian, Franklin M. Murden
  • Patent number: 8933749
    Abstract: In one embodiment, the present disclosure includes a circuit comprising an amplifier having an input and an output, an offset detection circuit to detect an offset of the amplifier at the output of the amplifier, and an offset generation circuit having an input coupled to the offset detection circuit and an output coupled to the input of the amplifier to generate an offset at the input of the amplifier during an operational phase of the amplifier based on the detected offset. The generated offset cancels a least a portion of the offset of the amplifier. In one implementation, the amplifier is a sense amplifier in a memory.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: January 13, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Winston Lee, Peter Lee
  • Patent number: 8928406
    Abstract: A new inverter-based fully-differential amplifier is provided including one or more common-mode feedback transistors coupled to each inverter, which transistors operate in the liner region. Accordingly, due to the fully-differential nature of the new inverter-based fully-differential amplifier, the amplifier provides an improved Power Supply Rejection Ratio (PSRR), provides a reduced sensitivity to supply voltage and process or part variations, and does not require an auto-zeroing technique to be utilized, which ultimately saves power, all while utilizing the low-voltage and low-power advantages of an inverter-based design.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: January 6, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Xavier Albinet
  • Patent number: 8928398
    Abstract: The even order harmonic distortion in a differential circuit is reduced or eliminated by treating the amplitude and phase mismatch sources that cause the distortion as impedance mismatches, and utilizing switched resistor circuitry that adjusts the load resistance to reduce the effects of the amplitude mismatch sources, and switched capacitor circuitry that adds shunt capacitance to reduce the effects of the phase mismatch sources.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: January 6, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Bumha Lee, Yongseon Koh
  • Patent number: 8922274
    Abstract: A bioamplifier that includes a high pass filter, open-loop amplifier, and low pass filter in an area efficient design that can be used in implantable neural interfaces. The high pass filter can be implemented by using a switch-capacitance resistor coupled with parasitic capacitance of the electrode. The amplifier can be chopper stabilized and can include a high gain, current-ratio first stage followed by one or more dimension-ratio stages. The low pass filter utilizes the output impedance of the open-loop amplifier to form an embedded gm-C low pass filter.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: December 30, 2014
    Assignee: The Regents of The University of Michigan
    Inventors: Euisik Yoon, Sun-Il Chang
  • Patent number: 8922275
    Abstract: A common mode bias circuit may include a weak common mode bias generator and a common mode bias capacitance. During a first state of the common mode bias circuit, the weak common mode bias generator may be coupled to the common mode bias capacitance and may impart to them a predefined common mode signal level. During a second state of the common mode bias circuit, the common mode bias capacitance may be coupled to differential inputs of an amplifier in a manner that establishes an input common mode level for the amplifier.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: December 30, 2014
    Assignee: Linear Technology Corporation
    Inventor: Dave Thomas
  • Patent number: 8922276
    Abstract: In aspects of the invention, at normal operation, an operational amplifier circuit has feedback applied from the output thereof to the input thereof so that currents equal to each other flow in differential pair transistors, respectively. While, in order that currents equal to each other may flow in the differential pair transistors, respectively, for compensating the difference in threshold voltages in the differential pair transistors, a voltage lower by a certain voltage difference than the voltage applied to the gate terminal of the transistor must be applied to the gate terminal of the transistor. From this, the switching of switches, when a virtual short circuit occurs, can make the output voltage of the operational amplifier circuit become a signal in which positive and negative rectangular ripples, with the values thereof being proportional to the value of the certain voltage difference, are superimposed on a true value.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: December 30, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Motomitsu Iwamoto
  • Publication number: 20140368267
    Abstract: The present disclosure relate to a sensor system having a low offset error. In some embodiments, the sensor system comprises a sensor configured to generate a sensor signal, which is provided to a main signal path having a first chopping correction circuit and a second chopping correction circuit. The first and second chopping correction circuit chop the sensor signal at first and second frequencies to reduce offset errors, but in doing so generate first and second chopping ripple errors. A first digital offset feedback loop generates a first compensation signal, which is fed back into the main signal path to mitigate the first chopping ripple error. A second digital offset feedback loop generates a second compensation signal, which is fed back into the main signal path to mitigate the second chopping ripple error.
    Type: Application
    Filed: September 4, 2014
    Publication date: December 18, 2014
    Applicant: Infineon Technologies AG
    Inventors: Mario Motz, Manfred Bresch
  • Patent number: 8907721
    Abstract: An audio amplification circuit is provided having an amplifier that receives an input signal, an output, and a digital control input for receiving a control value in a number n of bits; a comparator having a first input that receives the amplifier's output signal image, a second input that receives a reference potential, and an output; and a thermometer counter having a selection input coupled to the comparator output, and an output delivering an n-bit digital value to the amplifier control input. The amplifier comprises a differential input stage having a first and a second differential branch, each traversed by a bias current, the current in the first branch being modifiable by n basic current sources which each deliver either a current identical for all current sources, or no current, as a function of one respective bit of the digital control value received at the control input.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: December 9, 2014
    Assignees: ST-Ericsson SA, ST-Ericsson (Grenoble) SAS
    Inventors: Rémy Cellier, François Amiard
  • Patent number: 8907724
    Abstract: The embodiments of the present invention disclose a variable gain amplifier and relate to the field of electronic circuits. The linear-in-dB relationship between an output current and a control voltage of the variable gain amplifier is relatively ideal. The variable gain amplifier includes a fitted differential module group and an offset voltage output module, where the fitted differential module group is configured to output, under the control of a driving voltage and offset voltages, an output current of the variable gain amplifier according to a reference current; and the fitted differential module group includes n fitted differential modules, the n fitted differential modules are cascaded in turn, and n is any positive integer larger than 1.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: December 9, 2014
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jin Rao, Quan Liu, Yun Zhu, Huajiang Wang
  • Publication number: 20140340145
    Abstract: A signal processing circuit includes a chopper amplifier that has a differential amplifier circuit that amplifies differential input signals Vsp(t) and Vsm(t), and an adder circuit that generates an addition signal Vfil(t) by addition of the chopper output signal Vsub(t) that the chopper amplifier generates. Differential signals inputted into the differential amplifier circuit are interchanged for every first phase period and second phase period, and the adder circuit generates the addition signal by addition of the chopper output signal in the first phase period and in the second phase period.
    Type: Application
    Filed: April 16, 2014
    Publication date: November 20, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshihiro FUNATO, Toshio KUMAMOTO, Tomoaki YOSHIZAWA, Kazuaki KUROOKA
  • Patent number: 8872568
    Abstract: A method for setting an offset gain of analog output module configured to convert a digital signal outputted from an MPU (Micro Processing Unit) to an analog signal and to output the converted analog signal is proposed, the method including outputting, by the MPU, a digital signal value to the analog output module, calculating an offset gain by measuring, by the analog output module, an analog signal value outputted by receipt and conversion of the digital signal value, and entering the measured analog signal value to an offset gain inverse function preset by the MPU, and setting the offset gain of the analog output module as the calculated offset gain.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: October 28, 2014
    Assignee: LSIS Co., Ltd.
    Inventor: Jae Il Kwon
  • Publication number: 20140312967
    Abstract: A chopper amplifier includes a chopper modulator to modulate a certain detection signal and a bias voltage by a certain control signal and output a chopper modulation signal, a first differential amplifier to differentially amplify the chopper modulation signal from the chopper modulator and output a differential modulation signal, a chopper demodulator to demodulate the differential modulation signal from the first differential amplifier by the control signal and output a demodulation signal, a second differential amplifier to extract a detection signal component from the demodulation signal, and a plurality of filters connected at an input terminal of the second differential amplifier and having different cutoff frequencies from each other relative to the demodulation signal.
    Type: Application
    Filed: April 9, 2014
    Publication date: October 23, 2014
    Applicant: RICOH COMPANY, LTD.
    Inventor: Takeshi Nagahisa
  • Patent number: 8847677
    Abstract: According to one embodiment, an amplification circuit can be switched between amplifying and calibration modes. During calibration, a preamplifier amplifies a differential input signal and generates a differential output signal. The amplifier circuit includes an input switch unit which sets a differential input signal as the reference voltage signal of the same voltage level at the time of calibration, a PWM conversion unit which carries out Pulse-Width-Modulation of the differential output signal, and generates a differential PWM signal based on the result of comparing the differential output signal with the reference signal, a calibration unit which generates an offset adjustment signal according to the phase difference of differential PWM signals, and an electric amplifier which carries out electric power amplification of the differential PWM signal and generates the differential final output signal.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: September 30, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshikazu Nagashima
  • Patent number: 8841972
    Abstract: An electronic device, a fiber-optic communication system comprising the electronic device and a method of operating the electronic device are provided. The electronic device comprises a transimpedance-type amplifier having a transimpedance stage comprising an amplifier which is coupled in series with an input node. A feedback resistor is coupled in series between an output node of the amplifier and an inverting input node of the amplifier to provide a virtual ground node which is coupled to the input node, the inverting input node of the amplifier and to the feedback resistor. A current source is coupled to the virtual ground node so as to compensate for an offset current in an input signal which is coupled to the input node of the electronic device. Further, the electronic device comprises a control stage which is configured to control the current source as a function of a current through the feedback transistor.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: September 23, 2014
    Assignee: Texas Instruments Deutschland GmbH
    Inventor: Gerd Schuppener
  • Patent number: 8829988
    Abstract: The present disclosure relate to a sensor system having a low offset error. In some embodiments, the sensor system comprises a sensor configured to generate a sensor signal, which is provided to a main signal path having a first chopping correction circuit and a second chopping correction circuit. The first and second chopping correction circuit chop the sensor signal at first and second frequencies to reduce offset errors, but in doing so generate first and second chopping ripple errors. A first digital offset feedback loop generates a first compensation signal, which is fed back into the main signal path to mitigate the first chopping ripple error. A second digital offset feedback loop generates a second compensation signal, which is fed back into the main signal path to mitigate the second chopping ripple error.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 9, 2014
    Assignee: Infineon Technologies AG
    Inventors: Mario Motz, Manfred Bresch
  • Patent number: 8829989
    Abstract: This invention provides a multi-stage amplifier incorporating DC offset cancellation. The amplifier has a plurality of series-connected gain stages each of which comprises a differential amplifier unit generating a pair of differential outputs from a pair of differential inputs. In particular, a trailing stage in the plurality of gain stages comprises a digital DC offset cancellation module configured to compensate for a DC offset of the trailing stage's differential amplifier unit. The digital DC offset cancellation module comprises a comparator coupled to the pair of differential outputs of the trailing stage's differential amplifier unit for receiving such differential outputs as inputs for the comparator. Preferably, the comparator has an inherent DC offset that is substantially small. It is preferable that a non-trailing stage of the amplifier comprises an analog DC offset cancellation module for compensating for a DC offset of the non-trailing stage.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: September 9, 2014
    Assignee: Hong Kong Applied Science and Technology Research Institute Company Limited
    Inventors: Huimin Guo, Kai Cheung Chung, Gang Qian
  • Patent number: 8829985
    Abstract: According to one embodiment, a time difference amplifier circuit includes the first amplifier including first positive and negative inputs and first positive and negative outputs, the second amplifier including second positive and negative inputs and second positive and negative outputs, first to fourth wirings, a selection circuit including the first selection element connecting the first or fourth wirings to the second positive input, and the second selection element connecting the second or third wirings to the second negative input, and a control circuit connecting the amplifiers by the first and second wirings or by the third and fourth wirings.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: September 9, 2014
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Kiichi Niitsu, Naohiro Harigai, Masato Sakurai, Haruo Kobayashi
  • Publication number: 20140232456
    Abstract: Fast-settling capacitive-coupled amplifiers are disclosed. The amplifiers use two Capacitive Coupled paths embedded in a Multipath Hybrid Nested Miller Compensation topology. One path is a direct high frequency path and the other path is a slower stabilization path. This combination results in a flat frequency response to and through the chopper frequency, and a fast settling response. Various exemplary embodiments are disclosed, including operational amplifier and instrumentation amplifier configurations.
    Type: Application
    Filed: February 14, 2014
    Publication date: August 21, 2014
    Applicant: MAXIM INTEGRATED PRODUCTS, INC.
    Inventors: Johan Hendrik Huijsing, Qinwen Fan, Kofi Afolabi Anthony Makinwa, Daihong Fu, Jun Wu, Lixia Zhou
  • Patent number: 8810311
    Abstract: An amplifier having an inverting input and a non-inverting input; a capacitor coupled to inverting input of the amplifier; an input voltage conveyance control circuit, having a first switch and a second switch, the first switch coupled to the capacitor, and the second switch coupled to the non-inverting input of the amplifier; a reference voltage conveyance control circuit having a third switch and a fourth switch, a shared node coupled between third switch and fourth switch, the fourth switch coupled to the non-inverting input of the amplifier; a fifth switch coupled to an output of the amplifier; a leakage control circuit having a sixth switch and seventh switch, the sixth switch coupled between the inverting amplifier input and the fifth switch, the seventh switch coupled to the sixth switch and the capacitor; and a first resistor coupled from the output of the amplifier to the first switch.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: August 19, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Vadim Valerievich Ivanov, Brian Phillip Lum-Shue-Chan, Karthik Kadirvel
  • Patent number: 8803604
    Abstract: A control circuit is for generating upper and lower voltages that define a range of a data voltage for controlling a driving transistor of an electroluminescent component coupled to a supply line through the driving transistor. The control circuit may include a first input terminal configured to have a common voltage, and a pair of amplifiers coupled together at the first input terminal and configured to generate the upper voltage and the lower voltage to correspond to a difference between the common voltage and, respectively, first and second analog intermediate voltages representing respective threshold values of the upper voltage and of the lower voltage. The control circuit may include an auxiliary amplifier configured to adjust the upper voltage and the lower voltage based upon fluctuations of an input voltage, and generate the common voltage to correspond to the difference between the input voltage and a reference voltage.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: August 12, 2014
    Assignee: STMicroelectronics S.R.L.
    Inventors: Giovanni Conti, Domenico Cristaudo, Stefano Corradi
  • Patent number: 8803600
    Abstract: An output buffer circuit capable of enhancing stability includes an operational amplifier, a capacitive load and an output control unit. The operational amplifier has a positive input terminal, a negative input terminal and an output terminal, and generates an output voltage to the output terminal according to an input voltage received by the positive input terminal. The output control unit is coupled between the output terminal of the operational amplifier and the capacitive load, and is utilized for controlling electrical connection between the output terminal of the operational amplifier and the capacitive load to form a signal output path and for adjusting impedance of the signal output path when the signal output path is formed. The output control unit comprises a plurality of output switches for individually turning on or off the electrical connection between the output terminal and the capacitive load of the operational amplifier.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: August 12, 2014
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Xie-Ren Hsu, Ji-Ting Chen, Yao-Hung Kuo
  • Publication number: 20140210547
    Abstract: Provided is an operational amplifier circuit having a high tolerance for clock phase difference fluctuations. An FIR filter is used to add an input signal of the FIR filter to a signal obtained by delaying the input signal of the FIR filter. In this manner, chopper noise can be removed. Thus, the operational amplifier circuit may have a high tolerance for clock phase difference fluctuations regardless of the phase difference between clocks for controlling a chopper circuit and the FIR filter.
    Type: Application
    Filed: January 29, 2014
    Publication date: July 31, 2014
    Applicant: Seiko Instruments Inc.
    Inventor: Tsutomu TOMIOKA
  • Patent number: 8791754
    Abstract: A programmable gain amplifier (“PGA”) may include a differential amplifier, a pair of input capacitors, a pair of feedback capacitors provided in feedback configuration about the amplifier, a first chop circuit, provided at an input of the PGA and an output of the PGA and a second chop circuit provided at an output of the PGA. The PGA also may include circuit systems to sample voltages across the input capacitors in a sampling phase. The sampled voltages may correspond to a difference between a common mode voltage of input signals to the PGA and a common mode voltage of the differential amplifier. The sampled voltage, thus, defines a common mode voltage at the amplifier's inputs during other phases of operation, when the chop circuits are operational.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: July 29, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Colin G. Lyden, Roberto S. Maurino, Damien J. McCartney
  • Patent number: 8791753
    Abstract: Embodiments of a capacitance sensing system including an integrating amplifier and methods for operating the same to provide a higher slew rate and bandwidth are described. In one embodiment, the integrating amplifier comprises an input stage including an inverting input coupled to an electrode of a capacitor to sense a capacitance and a non-inverting input coupled to a reference potential, and an output stage including a compensating capacitor coupled to an output. The compensating capacitor comprises two smaller capacitors coupled in parallel and a switching element configured to open when the integrating amplifier is operated in a RESET mode decoupling one of the two smaller capacitors from the output to decrease capacitance of the compensating capacitor.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: July 29, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventors: Saravanan Murugesan, Paul Walsh, Gerard Baldwin, Kaveh Hosseini
  • Patent number: 8786363
    Abstract: Apparatus and methods for electronic amplification are provided. In one embodiment, a method of electronic amplification includes amplifying a differential input voltage signal to generate a feed-forward signal, chopping the feed-forward signal at a chopping frequency to generate a chopped feed-forward signal, notch filtering the chopped feed-forward signal at the chopping frequency to generate a notched signal, generating an input offset correction signal based at least partly on the notched signal, and amplifying the differential input voltage signal using a signal amplification block to generate an output signal. Amplifying the differential input voltage signal using the signal amplification block includes chopping the input signal at the chopping frequency to generate a chopped input signal and combining the chopped input signal and the offset correction signal to reduce input offset error of the signal amplification block.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: July 22, 2014
    Assignee: Analog Devices, Inc.
    Inventor: Fazil Ahmad
  • Patent number: 8773198
    Abstract: An auto-zero amplifier is disclosed, having an amplifying circuit, a switch, and a difference signal generating circuit. The amplifying circuit receives a first input signal for generating a first output signal, and receives a second input signal for generating a second output signal. The switch is coupled between the amplifying circuit and a capacitor. The switch is conducted for charging or discharging the capacitor to a voltage with the first output signal, and the switch is not conducted for keeping the capacitor at the voltage. The difference signal generating circuit is coupled with the amplifying circuit and the capacitor for generating a difference signal of the first output signal and the second output signal, a multiple of the difference signal, a part of the difference signal, and/or a digital output value for the difference signal.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: July 8, 2014
    Assignee: Richtek Technology Corporation
    Inventors: Shiueshr Jiang, An-Tung Chen, Jo-Yu Wang, Jen-Hung Chi