Abstract: A hall sensor device includes: an amplifier configured to amplify a detection signal of a hall sensor; and a current supplier configured to provide a compensation current to a feedback line of the amplifier according to an offset of the detection signal, to cancel the offset.

Abstract: The present invention relates to a method for preparing a hybrid supported metallocene catalyst. More specifically, the present invention relates to a method for preparing a hybrid supported metallocene catalyst by using two or more different types of metallocene compounds. One type of the metallocene compounds shows a high polymerization activity even when it is supported, and thus the catalyst has an excellent activity and can be utilized in the polymerization of olefinic polymers having ultra-high molecular weight. Based on the hybrid supported metallocene catalyst obtained according to the preparation method of the present invention, an olefinic polymer having high molecular weight and the desired physical property can be prepared.

Abstract: A differential amplifier has an inherent offset voltage. In many circuit applications, such as with a voltage to current converter circuit, it is important to nullify that offset voltage. A calibration circuit is provided to configured the differential amplifier to operate as a comparator with a common voltage applied to both inputs. The logic state of the output of the amplifier indicates whether the offset voltage is positive or negative. In response thereto, a trim current with a progressively increasing magnitude is injected into the amplifier and the amplifier output is monitored to detect a change in logic state. The magnitude of the trim current at the point where the logic state changes is the magnitude of trim current needed to nullify the voltage offset.

Abstract: Apparatus and methods for reducing input bias current of electronic circuits are provided herein. In certain implementations, an electronic circuit includes a first input terminal, a second input terminal, an input circuit, and a plurality of input switches including at least a first input switch and a second input switch. The first input switch is electrically connected between the first input terminal and a first input of the input circuit, the second input switch is electrically connected between the second input terminal and a second input of the input circuit, and the first and second input switches can be opened and closed using a clock signal. The electronic circuit further includes a charge compensation circuit for compensating for charge injection through the first and second input switches during transitions of the clock signal.

Abstract: A computer-implementable control algorithm that measures: 1) the reactive power; 2) the power factor; 3) the voltage; and 4) the line frequency. The algorithm calculates the differential compensation capacitance required that is either positive (capacitance to be added), or negative (capacitance to be removed). The new compensation capacitance is calculated from the sum or difference of the differential compensation capacitance and the current compensation capacitance. The algorithm compares the capacitor switching bit pattern for the current compensation capacitance and the capacitor switching bit pattern for the new compensation capacitance, and selects a capacitor switching bit map accordingly. The capacitor switch combination for the new compensation capacitance is switched in incrementally according to the capacitor switching bit map. To reach the selected capacitor switch combination, only one switch is switched at a time to minimize the line transient noise.

Abstract: A successive approximation ADC made of a low voltage configurable differential amplifier and low voltage logic circuits which can convert a high voltage analog input to a digital equivalent. The differential amplifier can be configured as either an op amp or a comparator depending upon the mode of operation. An input capacitor C1 is switchably coupled to an electrode selected for voltage sampling. A switched capacitor array C2 is coupled across the differential amplifier input and output. A SAR coupled to the switched capacitor array provides a digital output corresponding to the sampled analog voltage. During a sampling interval and a charge transfer interval, the differential amplifier is configured as an op amp. During the transfer interval, the voltage on the input capacitor multiplied by the ratio C1/C2 is transferred to the switched capacitor array. During an analog to digital conversion interval, the ADC converts the analog voltage to an equivalent digital output.

Abstract: One example includes a hot-swap control system. The system includes a sense resistor network provides a sense voltage in response to an output current. The system also includes a sense control circuit includes a chopper amplifier system arranged in a servo feedback arrangement to generate a monitoring voltage having an amplitude that is associated with the output current based on the sense voltage. A notch filter chopping stage filters out signal ripple in the chopper amplifier system across a unity-gain bandwidth of the chopper amplifier system, and a capacitive compensation network provides stability-compensation of the chopper amplifier system across the unity-gain bandwidth. A transconductance amplifier configured to compare the monitoring voltage with a predetermined reference voltage to generate a control voltage. The system further includes a power transistor configured to conduct the output current to an output based on the control voltage.

Abstract: An instrumentation amplifier includes: a capacitive feedback closed-loop amplifier, an input capacitor charging module, a feedback capacitor discharging module, a noise separation module and a logic controller. The capacitive feedback closed-loop amplifier includes a fully differential operational amplifier, a first input capacitor, a second input capacitor, a first feedback capacitor and a second feedback capacitor. The input capacitor charging module is configured to charge the first input capacitor and the second input capacitor periodically. The feedback capacitor discharging module is configured to discharge the first feedback capacitor and the second feedback capacitor periodically. The noise separation module is configured to separate a noise from a signal using a chopping modulation technology. The logic controller is connected to the input capacitor charging module, the feedback capacitor discharging module and the noise separation module to control the modules to operate.

Abstract: According to one embodiment, there is provided an active load circuit including a first transistor, a second transistor, a first resistor, a second resistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a line. The third transistor is placed between the first transistor and the first reference node. The fourth transistor is placed between the second transistor and the first reference node. The seventh transistor is placed between the fifth transistor and the first reference node. The eighth transistor is placed between the sixth transistor and the first reference node. A line connecting a fifth node between the fifth transistor and the seventh transistor and a sixth node between the sixth transistor and the eighth transistor.

Abstract: Apparatus and methods for digitally-assisted feedback offset correction are provided herein. In certain configurations, an amplifier includes amplification circuitry for providing amplification to an input signal and chopping circuitry for compensating for an input offset voltage of the amplifier. Additionally, the amplifier further includes a digitally-assisted feedback offset correction circuit, which includes a chopping ripple detection circuit, a feedback-path chopping circuit, a digital correction control circuit, and an offset correction circuit. The chopping ripple detection circuit generates a detected ripple signal based on detecting an output ripple of the amplifier. Additionally, the feedback-path chopping circuit demodulates the detected ripple signal using the amplifier's chopping clock signal.

Abstract: Various apparatuses and methods are described where a signal is amplified using a chopper amplifier arrangement, and ripples caused by said chopper amplifier arrangement are reduced. In some cases, this reduction of ripples is performed by controlling a voltage offset of an amplifier of said chopper amplifier arrangement. In other embodiments, a detection of ripples or a chopping of the chopper amplifier arrangement is at least temporarily disabled.

Abstract: A differential amplifier stage may include: a first transistor having a gate terminal; a second transistor having a gate terminal; and a voltage limiting circuit coupled to the gate terminals of the first and second transistors, wherein the voltage limiting circuit limits a gate voltage supplied to at least one of the gate terminals of the first and second transistors.

Abstract: There is provided an operational amplifier which is operable as well when an operating voltage decreases without creating a range where a circuit would not operate or reducing circuit gain. High-pass filters 102-105 provide output signals therefrom to bias-set input nodes of differential amplifiers Gm1-Gm4 to a potential within a common-mode range in which the respective differential amplifiers Gm1-Gm4 are operable. In this manner, the respective differential amplifiers Gm1-Gm4 can be operated effectively regardless of the possible decrease in a supply voltage, enabling normal amplifying operation. In addition, reduction in gain due to the reduced operational voltage is avoided. Therefore, it is preferably applicable to the application where digital and analog circuits are loaded together on the same IC chip.

Abstract: One example includes an OP-AMP circuit system. The system includes a signal amplification path comprising a signal amplification path comprising a signal amplifier and an output stage. The signal amplification path can be configured to amplify an input voltage received at an input to provide an output voltage via the output stage. The system also includes an offset-reduction path coupled to the input of the signal amplification path and to an output of the signal amplifier. The offset-reduction path includes a transconductance amplifier and at least one chopper that are configured to mitigate noise in the signal amplification path and a noise-filtering feedback path configured to provide chopper feedback with respect to an offset voltage associated with the offset-reduction path, the noise-filtering feedback path comprising a feedback path input coupled to the input of the transconductance amplifier via a resistor.

Abstract: An embodiment of an amplifier includes N (N>1) switch-mode power amplifier (SMPA) branches. Each SMPA branch includes two drive signal inputs and one SMPA branch output. A module coupled to the amplifier samples an input RF signal, and produces combinations of drive signals based on the samples. When an SMPA branch receives a first combination of drive signals, it produces an output signal at a first voltage level. Conversely, when the SMPA branch receives a different second combination of drive signals, it produces the output signal at a different second voltage level. Finally, when the SMPA branch receives a different third combination of drive signals, it produces the output signal at a voltage level of substantially zero. A combiner combines the output signals from all of the SMPA branches to produce a combined output signal that may have, at any given time, one of 2*N+1 quantization states.

Abstract: A circuit for implementing a time-interleaved analog-to-digital converter is described. The circuit comprises a sampling clock generator configured to receive a reference clock signal having a first frequency.

Abstract: Apparatus and methods for multi-channel autozero and chopper amplifiers are provided herein. In certain configurations, an amplifier includes at least three channels that operate using multiple phases, including at least a non-inverting chop phase, an inverting chop phase, and an autozero phase. The amplifier further includes an autozero and chopping timing control circuit, which at least partially interleaves or staggers timing of the channels' phases. For example, in certain configurations, when one or more of the channels are being autozeroed at a certain time instance, at least some of the remaining channels operate in the non-inverting chop phase or the inverting chop phase.

Abstract: A device includes an operational-amplifier including an amplifier-part amplifying signals and transmitting amplified signals to a first and a second nodes, and an output-part connected to the first and second nodes and outputting signals from a first and a second outputs. The device includes a first and a second chopper switches and a first and second phase-compensation capacity elements. A first capacitance switch switches between a first connection-state and a second connection-state. In the first connection-state, the first phase-compensation-capacity element is connected between the first node and the first output and the second phase-compensation-capacity element is connected between the second node and the second-output. In the second connection state, the first phase-compensation-capacity element is connected between the second-node and the second output and the second phase-compensation-capacity element is connected between the first node and the first output.

Abstract: A system and method for adjusting a common mode output voltage in an instrumentation amplifier is provided. In one aspect, the common mode output voltage is increased or decreased with respect to the common mode input voltage to enable high amplification of the signal input to the instrumentation amplifier. Moreover, the common mode output voltage can be driven to (or approximately to) a target voltage value such as, but not limited to, half the supply, even if the common mode input voltage is close to supply or ground rail voltage. Thus, a high amplification of the differential input voltage can be obtained and utilized for various applications requiring rail to rail input.

Abstract: Phase-dependent operational amplifiers (“op-amps”) employing phase-based frequency compensation, and related systems and methods are disclosed. A phase-dependent op-amp is provided configured to provide output voltage based on inputs switched by clock signal. The op-amp employs a frequency compensation system having multiple frequency compensation circuits. The frequency compensation circuit corresponding to the clock phase is selected by selection circuit and coupled to the voltage output node. The op-amp charges each frequency compensation circuit during the clock phase to store voltage approximately equal to output voltage. When transitioning to a clock phase, output voltage of op-amp does not have to charge frequency compensation circuit. Voltage of frequency compensation circuit stored during clock phase is approximately equal to output voltage of op-amp for clock phase.

Abstract: An apparatus includes voltage-to-current conversion circuitry comprising a first voltage-to-current converter and a second voltage-to-current converter. The apparatus also includes a capacitor coupled to the first voltage-to-current converter and to the second voltage-to-current converter.

Abstract: Gain offset and voltage offset compensation for a controllable gain element of a circuit is effected in response to a gain offset value and voltage offset value. A current operating condition of the circuit is sensed and compared to a nominal operating condition. If the current operating condition is outside the nominal operating condition by more than a threshold, a calibration operation to set the gain and voltage offset values is performed. The gain offset value is selected as a function of the sensed current operating condition. With respect to the voltage offset, differential input terminals of the controllable gain element are shunted and the output is measured. The measured output value of the controllable gain element is applied as the voltage offset value. The operating conditions at issue may be one or more of supply voltage and temperature.

Abstract: According to at least one example embodiment a two phase calibration approach is employed for calibrating an input/output interface having multiple single-ended receivers. During a first phase, amplifier offset calibration is applied to each of the multiple single-ended receivers. During a second phase, reference voltage calibration is applied to a single-ended receiver of the multiple single-ended receivers to determine a calibration reference voltage value. The calibration reference voltage value is then employed in each of the multiple single-ended receivers during an active phase of the input/output interface.

Abstract: An embodiment of an auscultation device can be constructed using, at least in part, electronic components to provide improved acquisition, processing, and communication of sound signals. An input device can be used for detecting sounds, and electrical signals representing the sounds can be processed and transmitted via one or more of a plurality of substantially contemporaneously available wired and/or wireless communications interfaces. Bluetooth and/or another form of wireless communication can be employed. Such embodiments can employ, at least in part, one or more of several commercially available wired and/or wireless receiver devices, such as, without limitation, headsets and headphones, mobile phones, PDAs and/or other handheld devices, desktop, laptop, palmtop, and/or tablet computers, speakers and/or other conventional and/or specifically configured computer devices and/or electronic devices.

Abstract: A differential amplifier circuit and method having a feed-in network coupling an input signal to an intermediate signal. An amplifier amplifies the intermediate signal by a gain factor to output an output signal to a load network. A feedback network configured in a negative feedback topology and couples the output signal to the intermediate signal. A gain enhancing network is configured in a positive feedback topology and couples the output signal to the intermediate signal. Preferably, an impedance of the gain enhancing network is approximately equal to an impedance of a parallel connection of the feed-in network and the feedback network times the gain factor minus one.

Abstract: A transmission device for two electric pulse measurement signals includes a first measurement signal input, a second measurement signal input, a differential measurement signal output and a signal converter. The first measurement signal input serves for receiving a first single-ended measurement signal, the second measurement signal input for receiving a second single-ended measurement signal, wherein the signal converter is implemented, when receiving a first one of the single-ended measurement signals, to convert either the first single-ended measurement signal or the second single-ended measurement signal into a combined differential measurement signal and provide the same at the differential measurement signal output. Here, the differential measurement signal includes a first differential portion which may be allocated to the first single-ended measurement signal and a second differential portion which may be allocated to the second single-ended measurement signal.

Abstract: Apparatus and methods for chopper amplifiers are provided herein. In certain configurations, a chopper amplifier includes at least one differential transistor bank including a selection circuit and a plurality of transistors. The selection circuit can select a first portion of the transistors for operation in a first transistor group and a second portion of the transistors for operation in a second transistor group. During calibration, the chopper amplifier's input offset can be observed for different transistor configurations of the differential transistor banks. Although the transistors of a particular bank can be designed to have about the same drive-strength and/or geometry, the chopper amplifier can have a different input offset in different transistor configurations due to manufacturing mismatch between transistors, such as process variation.

Abstract: A biopotential monitoring device includes a configurable receiver circuit having a plurality of channels for receiving a plurality of biopotential signals from a biological tissue via a plurality of inputs coupled with the electrodes, and each channel substantially removes a DC (direct current) offset from a corresponding one of the biopotential signals and then band-pass amplifies such corresponding biopotential signal at a configurable gain and particular frequency range based on frequency control signals. The device further includes a controller circuit for receiving commands for configuring frequency characteristics of each biopotential signal. The controller automatically generates the frequency control signals based on such commands and outputs such frequency control signals to the configurable receiver circuit. The controller outputs a representation of each biopotential signal to an analyzer device that is configured to analyze such biopotential signal.

Abstract: In some embodiments, a differential amplifier with duty cycle correction is provided.

Abstract: An apparatus for handling a received signal comprises a reception device, a mixer unit and a compensating unit. The reception unit can receive a received signal. The received signal has at least one signal component at a first frequency. Furthermore, the mixer unit can combine the received signal and a compensating signal using at least one active element in order to obtain a compensated received signal. In addition, the mixer unit can produce a mixer output signal on the basis of the compensated received signal and a local oscillator signal. In this case, the mixer output signal has a signal component, corresponding to the at least one signal component of the received signal, at a second frequency. The first frequency is higher than the second frequency.

Abstract: An amplifier input stage comprising first and second p-type transistors, wherein sources of the first and second p-type transistors are connected to a first node, a drain of the first p-type transistor is connected to a first output of the amplifier input stage, a drain of the second p-type transistor is connected to a second output of the amplifier input stage, a gate of the first p-type transistor is configured to receive a first signal of an input stage differential input signal and a gate of the second p-type transistor is configured to receive a second signal of the input stage differential input signal; first and second n-type transistors, wherein sources of the first and second n-type transistors are connected to a second node, a drain of the first n-type transistor is connected to a third output of the amplifier input stage, a drain of the second n-type transistor is connected to a fourth output of the amplifier input stage, a gate of the first n-type transistor is configured to receive the first sign

Abstract: Apparatus and methods for autozero amplifiers are provided herein. In certain configurations, an autozero amplifier includes at least three transconductance stages and an autozero timing control circuit configured to control an autozero sequence of the transconductance stages. The autozero timing control circuit can stagger autozeroing of the transconductance stages, such that a relatively small amount of the amplifier's amplification circuitry is connected to or disconnected from the amplifier's signal path at any given time. For example, in certain configurations, when one of the transconductance stages in autozeroed over a particular time interval, the remaining transconductance stages can operate in parallel to provide amplification during that time interval.

Abstract: Fast-settling capacitive-coupled amplifiers are disclosed. The amplifiers use two Capacitive Coupled paths embedded in a Multipath Hybrid Nested Miller Compensation topology. One path is a direct high frequency path and the other path is a slower stabilization path. This combination results in a flat frequency response to and through the chopper frequency, and a fast settling response. Various exemplary embodiments are disclosed, including operational amplifier and instrumentation amplifier configurations.

Abstract: In an embodiment, an apparatus includes a component of a receiver path to receive and process an incoming signal. At least one element of the component is controllable based on a DC output of the component, to compensate for a second order intermodulation product of the apparatus. As one example, the component is a differential amplifier including a first transistor and a second transistor.

Abstract: A charge preamplifier for converting an electric charge generated in a charge source sensor into a voltage signal, including: a phase inverting amplifier including an input related to the charge source sensor, and an output for providing the voltage signal; a storage capacitor connected between the input and the output of the phase inverting amplifier; a reset system connected to the input of the phase inverting amplifier, for providing to the storage capacitor a discharging current as a function of a control signal, and a control element including: a first input connected to the output of the phase inverting amplifier, for withdrawing the voltage signal, a second input subjected to a reference voltage, a set of components configured and arranged to generate a control signal proportional to the deviation between the voltage signal and the reference voltage, the proportionality coefficient being lower than one in a high frequency band, an output connected to the reset system to provide thereto the control sign

Abstract: A communications device may include a first transmit path having a first band pass filter operating at a first frequency band having a first bandwidth, and a second transmit path having a second band pass filter operating at a second frequency band having a second bandwidth. The second frequency band may be adjacent the first frequency band and the second bandwidth may be less than the first bandwidth. The communications device may include a third receive path operating at a third frequency band having a third bandwidth, and a fourth receive path operating at a fourth frequency band having a fourth bandwidth. The fourth frequency band may be adjacent the third frequency band, and the fourth bandwidth may be less than the third bandwidth.

Abstract: An operational amplifier has two paths, a high frequency path and a low frequency path. In addition, it has three main sections of stages. A stage converts input voltage to an amplified output voltage, a stage converting an input voltage in to an output current and a final stage where the outputs of the two previous sections are supplied as inputs. Among them, the final stage acts as a voltage follower to a signal applied to its plus (+) input and as a transimpedance amplifier for a signal applied to its minus input (?). In this configuration, a path for low frequencies and a path for high frequencies are created in a single operational amplifier.

Abstract: A chopper amplifier includes a chopper modulator to modulate a certain detection signal and a bias voltage by a certain control signal and output a chopper modulation signal, a first differential amplifier to differentially amplify the chopper modulation signal from the chopper modulator and output a differential modulation signal, a chopper demodulator to demodulate the differential modulation signal from the first differential amplifier by the control signal and output a demodulation signal, a second differential amplifier to extract a detection signal component from the demodulation signal, and a plurality of filters connected at an input terminal of the second differential amplifier and having different cutoff frequencies from each other relative to the demodulation signal.

Abstract: Provided is an operational amplifier circuit capable of operating with lower current consumption. An amplifier stage, a FIR filter, and a sample and hold circuit are connected in series, thus enabling reduction of an input offset voltage and amplification of an input signal voltage without using an integral circuit. Current consumption of the operational amplifier circuit is reduced because the integral circuit is not used.

Abstract: Multi-stage amplifiers, such as linear regulators, configured to provide a constant output voltage subject to load transients, are described. The multi-stage amplifier includes a first amplification stage which activates or deactivates a first output stage in response to an input voltage at an input node. The first output stage is configured to source a current at an output node of the multi-stage amplifier from a high potential, when activated. Furthermore, the multi-stage amplifier includes a second amplification stage configured to activate or to deactivate a second output stage in response to the input voltage at the input node. The second output stage is configured to sink a current at the output node of the multi-stage amplifier to a low potential, when activated. The first amplification stage and the second amplification stage are configured to activate the first output stage and the Second output stage in a mutually exclusive manner.

Abstract: A system for cancelling offset includes a gain circuit. The gain circuit may include a transistor circuit connected to a pair of input nodes and configured to convert an input signal to an output signal so that the output signal has a gain compared with the input signal. The gain circuit also may include a pair of output nodes configured to receive the output signal from the transistor circuit. The gain circuit is configured to cause a voltage change at one of the output nodes relative to another output node, in response to the gain circuit receiving a feedback offset correction signal. This effectively cancels at least a portion of an offset in the output signal.

Abstract: The present disclosure relate to a sensor system having a low offset error. In some embodiments, the sensor system comprises a sensor configured to generate a sensor signal, which is provided to a main signal path having a first chopping correction circuit and a second chopping correction circuit. The first and second chopping correction circuit chop the sensor signal at first and second frequencies to reduce offset errors, but in doing so generate first and second chopping ripple errors. A first digital offset feedback loop generates a first compensation signal, which is fed back into the main signal path to mitigate the first chopping ripple error. A second digital offset feedback loop generates a second compensation signal, which is fed back into the main signal path to mitigate the second chopping ripple error.

Abstract: A circuit includes a first amplifier circuit and a second amplifier circuit. The second amplifier circuit includes an input coupled to an output of the first amplifier circuit. A pass gate circuit is coupled between first and second inputs of the first amplifier circuit. The pass gate circuit is on during calibration of the second amplifier circuit to short together signals at the first and the second inputs of the first amplifier circuit. The pass gate circuit is off during a normal mode of the first and the second amplifier circuits.

Abstract: An analog-to-digital conversion system and method includes, for example, a comparator for sampling an analogy quantity during a sampling period and for performing a series of bit-wise conversions on the sampled analog sample during a conversion period, where each bit-wise conversion occurs during a respective bit-wise conversion cycle in which successive bits of a sample are successively determined during a respective bit conversion cycle and in which a predetermined number of bit-wise conversions are to be performed. A clock generator is arranged for generating a clock signal for clocking the converter during the conversion period, wherein each bit conversion cycle includes a reset period having a first length and an amplification period having a second length, wherein one of the first and second lengths is dynamically selected.

Abstract: A signal transmission circuit includes an isolation circuit, first and second grounded gate circuits, first and second MOS transistors, and a comparator. The isolation circuit such as a thin-film transformer outputs complementary first and second output signals, based on an input signal. The first and second grounded gate circuits receive and amplify the first and second output signals, respectively. The first and second MOS transistors are connected between a power supply node and the first and second grounded gate circuits, respectively, for adjusting the first and second output signals. The comparator compares output from the first grounded gate circuit with output from the second grounded gate circuit.

Abstract: An electrosurgical system is provided. The electrosurgical system includes an electrosurgical generator adapted to supply electrosurgical energy to tissue. A power source operably couples to the electrosurgical generator and is configured to deliver power to one or more types of loads connected to the electrosurgical generator. The electrosurgical generator includes a controller including a microprocessor coupled to the electrosurgical generator and configured to control the output of the electrosurgical generator. A fiber optic connection circuit is in operative communication with the controller and includes one or more types of logic devices and one or more types of fiber optic channels. The fiber optic connection circuit is configured to mitigate leakage current associated with at least one of a plurality of components operatively associated with the electrosurgical generator by providing isolation.

Abstract: A Programmable-Gain Amplifier (PGA) has a digital value that programmably adjusts the gain of the analog amplifier. A variable capacitor has several switched sub-capacitors that are enabled by the digital value. Enabled sub-capacitors are switched between a sampled input and a virtual ground on one terminal, and connect to a summing node on the other terminal. The summing node connects to the inverting input of an op amp either through a switch or through a double-sampling capacitor that stores an offset. A feedback capacitor is in parallel with a sampling capacitor during a second clock phase when direct-charge transfer occurs, reducing power consumption of the amplifier. The feedback capacitor samples the sampled input during the first clock phase. The PGA gain is proportional to the sum of capacitances of enabled sub-capacitors. The gain can be adjusted for sensor inputs to an Analog Front-End (AFE), such as for an electro-cardiogram (ECG).

Abstract: An image sensor array that has a buffer amplifier, having a capacitor which receives photogenerated energy from a photodetector, and stores the photo generated energy in a capacitor of the buffer amplifier. A reset across the buffer amplifier is applied at a time which is sufficient to allow the amplifier to settle transiently prior to applying the clamp voltage. There is also a source follower that is enabled to operate at a time just before snapshot operation, and then turned off when the snapshot is over, to save on power.

Abstract: Provided is an operational amplifier circuit having a high tolerance for clock phase difference fluctuations. An FIR filter is used to add an input signal of the FIR filter to a signal obtained by delaying the input signal of the FIR filter. In this manner, chopper noise can be removed. Thus, the operational amplifier circuit may have a high tolerance for clock phase difference fluctuations regardless of the phase difference between clocks for controlling a chopper circuit and the FIR filter.

Abstract: A signal processing circuit includes a chopper amplifier that has a differential amplifier circuit that amplifies differential input signals Vsp(t) and Vsm(t), and an adder circuit that generates an addition signal Vfil(t) by addition of the chopper output signal Vsub(t) that the chopper amplifier generates. Differential signals inputted into the differential amplifier circuit are interchanged for every first phase period and second phase period, and the adder circuit generates the addition signal by addition of the chopper output signal in the first phase period and in the second phase period.