Abstract: A DC to DC converter includes a current detecting circuit having a level shift circuit, which includes a resistor and a current source. A first low-pass filter is led out from a node via a signal line and includes a resistor and a capacitor. A first switch is provided after the level shift circuit, a second switch is provided after the low-pass filter, a second low-pass filter, which includes a resistor and a capacitor, an operational amplifier, a third switch is provided between an output terminal and an inverted input terminal of the operational amplifier, and a capacitor is provided between the inverted input terminal of the operational amplifier and GND. An output current is detected with high accuracy without lowering the efficiency by detection resistance.

Abstract: A circuit arrangement is disclosed herein comprising an amplifier circuit having inputs configured to receive an input signal, and an output configured to provide an output signal. The circuit arrangement further comprises a first operational amplifier. The first operational amplifier includes inputs coupled to the inputs of the amplifier circuit, an output coupled to the output of the amplifier circuit, and a first compensation input. The compensation input is configured to feed an offset compensation signal to the first operational amplifier. The circuit arrangement further comprises a first compensation circuit configured to provide the offset compensation signal. The first compensation circuit is coupled to the inputs of the first operational amplifier. The circuit arrangement further comprises a deactivation circuit which is designed to temporarily deactivate the first compensation circuit.

Abstract: A differential transimpedance amplifier circuit for correlated differential amplification. The amplifier circuit increase electronic signal-to-noise ratios in charge detection circuits designed for the detection of very small quantities of electrical charge and/or very weak electromagnetic waves. A differential, integrating capacitive transimpedance amplifier integrated circuit comprising capacitor feedback loops performs time-correlated subtraction of noise.

Abstract: An operational amplifier is dynamically accelerated depending on its internal state. Acceleration is disabled when the internal state indicates a risk of instability. When the internal state of the operational amplifier indicates no risk of instability, the acceleration is turned on to speed up the circuit operation.

Abstract: Balanced offset compensation is provided for a differential amplifier circuit. Two sets of three switches are employed between respective inputs and outputs of the differential amplifier to shunt the outputs to the input terminals during auto-zeroing phase. By opening and closing different combinations of the switches during auto-zeroing and operation phases, differential degradation due to unbalanced leakage currents is substantially reduced.

Abstract: This disclosure describes a chopper stabilized instrumentation amplifier. The amplifier is configured to achieve stable measurements at low frequency with very low power consumption. The instrumentation amplifier uses a differential architecture and a mixer amplifier to substantially eliminate noise and offset from an output signal produced by the amplifier. Dynamic limitations, i.e., glitching, that result from chopper stabilization at low power are substantially eliminated through a combination of chopping at low impedance nodes within the mixer amplifier and feedback. The signal path of the amplifier operates as a continuous time system, providing minimal aliasing of noise or external signals entering the signal pathway at the chop frequency or its harmonics. The amplifier can be used in a low power system, such as an implantable medical device, to provide a stable, low-noise output signal.

Abstract: The present disclosure relates generally to systems and methods for direct current (DC) correction in wireless devices. In one example, a method includes setting a cutoff frequency of a filter at a first frequency, where a signal entering the filter is attenuated based on the cutoff frequency. If a qualified change is detected in a DC component of the signal, the cutoff frequency is set at a second frequency that attenuates more of the signal than the first frequency for a defined time period. The cutoff frequency may then be set to the first frequency after the defined time period.

Abstract: Methods and systems for fast calibration to cancel phase feedthrough are disclosed and may comprise individually activating each of n binary-weighted cells utilizing a control signal in a power amplifier driver (PAD) and measuring the output signal, or offset, in response to a null signal applied to an input of each binary-weighted cell. This offset may be fed back, summed, and adjusted until the measured PAD output may be minimized. This calibrated offset may cancel phase feedthrough of the PAD, and the calibrated offset for each binary-weighted cell may be stored in a lookup table. The control signal may also be utilized for controlling the output power of the PAD by activating appropriate binary-weighted cells. For each of the 2n output powers, a calibrated offset is calculated utilizing a weighted sum of the stored offsets for the activated binary-weighted cells.

Abstract: According to one embodiment, a system for constant bandwidth DC offset correction in an amplifier includes a number of amplifier stages having an input and an output coupled together in series. The system for constant bandwidth DC offset correction further includes a number of DC offset correction feedback loops which include a variable gain transconductor coupled to an integration capacitor further coupled to a fixed gain transconductor. Each of the DC offset correction feedback loops are coupled to the input and output of each of the number of amplifier stages. The transconductance of the variable gain transconductor in each of the number of DC correction feedback loops is varied in relation to a gain of the number of amplifier stages, such that the DC offset correction feedback loops provide DC offset correction while maintaining a constant bandwidth.

Abstract: This disclosure describes a chopper stabilized instrumentation amplifier. The amplifier is configured to achieve stable measurements at low frequency with very low power consumption. The instrumentation amplifier uses a differential architecture and a mixer amplifier to substantially eliminate noise and offset from an output signal produced by the amplifier. Dynamic limitations, i.e., glitching, that result from chopper stabilization at low power are substantially eliminated through a combination of chopping at low impedance nodes within the mixer amplifier and feedback. The signal path of the amplifier operates as a continuous time system, providing minimal aliasing of noise or external signals entering the signal pathway at the chop frequency or its harmonics. The amplifier can be used in a low power system, such as an implantable medical device, to provide a stable, low-noise output signal.

Abstract: Two nulling amplifiers are used with an auto-zeroed differential amplifier. While one nulling amplifier is compensating the main amplifier, the other nulling amplifier is being zeroed for both differential mode (DM) and common mode (CM) offsets. By using two nulling amplifiers, one always connected to the main amplifier, a relatively constant open-loop gain is maintained for the main amplifier. A further improvement is make-before-break timing overlap of the switch operations between the two nulling amplifiers and the main amplifier. This ensures that the main amplifier is continuously driven by one or both null amplifiers, thereby maintaining a low impedance at the main amplifier auxiliary port. Both DM and CM offset sampling and precharging of each of the two nulling amplifiers is performed so as to substantially reduce switching glitches in the output of the main amplifier.

Abstract: Aspects of the invention provide a system for a mixed analog-digital automatic gain control. The received analog signal is amplified by the analog amplifier and then converted to a digital value by an ADC. A clamp reference level of the converted signal is removed prior to applying a digital gain to a digital multiplied. Once the digital gain is applied, the clamp reference level is restored to the digital signal. A loop filter determines the system time response from the error between an amplitude parameter of the received signal and an AGC reference level. A gain separation circuit generates the system gain and separates it into a digital gain and an analog gain in a way to maximize the use of the analog amplifier. The analog gain is applied to the analog amplifier and the digital gain is applied to the digital multiplier.

Abstract: An amplifier system receives an input signal and generating therefrom an amplified output signal. The amplifier system is recited as comprising an input stage and an amplifier stage. The input stage is configured to receive the input signal and provide a level-shifted signal that has an average signal level that is shifted in regards a level shift value. The amplifier stage is configured to receive the level-shifted input signal from the input stage and generate therefrom the amplified output signal. The level shift value being selected to minimize a DC offset in the amplified output signal at least when the amplifier system is initially powered on. Since the amplified output signal has a minimal or zero DC offset, the amplifier system avoids generation of undesirable noises when it is initially powered on.

Abstract: A clamping circuit for restoring the DC level of video input signals. The clamping circuit comprises a coupling capacitor, a latch, a logic element, a charge switch, and a constant current source. The latch is coupled to the coupling capacitor to receive a video input signal therethrough and comprises a bias current source for generating first and second output signals in response to the AC-coupled signal and a reference voltage. The logic element receives the first and second output signals, generating a charging control signal to the charge switch. The charge switch, responsive to the charging control signal, is turned on to direct the current of the bias current source to the coupling capacitor, raising the level of the AC-coupled signal. Meanwhile, the constant current source continuously discharges the coupling capacitor slowly.

Abstract: A DC offset cancellation block is provided for canceling a DC offset in a signal path. The signal path may include an input and an output. The DC offset cancellation block may include an active integrator coupled between the input and the output to provide a negative feedback to the signal path. The active integrator may include an operational-amplifier (op-amp), a capacitive component with a capacitance C, and a resistive component with a resistance R, and the capacitive component may be coupled to the op-amp via a closed feedback loop. The DC offset cancellation block may also include a first amplifier with a gain of GA coupled with the capacitive component in the closed feedback loop such that a RC time constant of the active integrator is changed from RC to RCGA.

Abstract: Techniques and circuitry are provided for programmably controlling signal offsets in integrated circuitry. In one embodiment, an integrated circuit includes a signal offset cancellation circuit that is programmably selected to control the offset of signals on either one input/output or another input/output of an amplifier circuit. In one embodiment, a logic circuit is used to selectively couple a bank of current sources to one input/output or another input/output of a differential amplifier through a switching circuit. The bank of current sources may employed to control the signal offset on either input/output, or may be decoupled from all of the inputs/outputs when signal offset cancellation is not required.

Abstract: In a balanced output circuit, an input signal inputted thereto is provided as a first output signal thereof on one hand, and on the other hand the input signal is inputted to an inverting amplification circuit and is compared with a comparison voltage before the signal is outputted as a second output signal. Based on the comparison of the first and second output signals, the comparison voltage is controlled by a charging voltage of a capacitor such that the DC voltage of the second output signal is equalized to that of the first output signal. Thus, the DC offset voltage between the first output signal (non-inverted output signal) and the second output signal (inverted output signal) can be properly annihilated by a simple circuit.

Abstract: An operational amplifier that cancels offset voltage while enabling its gain to be set to any value. The operational amplifier includes a first switch for short-circuiting the gates of two transistors in a first differential input unit. A capacitor is connected to the gates of two transistors in a second differential input unit, which is connected in parallel to the first differential input unit. The capacitor holds offset voltage derived from output voltage generated by an operational amplifier circuit. The capacitor generates a potential difference between the gates of the transistors in the second differential input unit to cancel the offset voltage.

Abstract: A switched capacitor CMOS amplifier uses a first stage non-inverting CMOS amplifier driving a second stage inverting CMOS amplifier. The first stage amplifier is provided with positive feedback to substantially increase the gain of the first stage amplifier. In the described examples, the positive feedback is provided either by connecting a capacitor from the output to the input of the first stage amplifier or by connecting a shunt transistor in parallel with an input transistor and driving the transistor from the output of the first stage amplifier. The substantially increased gain resulting from the positive feedback allows the gain of the switched capacitor amplifier to be set by the ratio of the capacitance of an input capacitor to the capacitance of a feedback capacitor. The amplifier also includes switching transistors for periodically discharging the input capacitor and the feedback capacitor.

Abstract: A method and an apparatus are described for an offset correction in a high gain amplifier. An embodiment of an amplifier circuit includes an amplifier to convert a current signal into a voltage signal, where the amplifier generates an offset voltage in the voltage signal. The amplifier circuit also includes a sampling component coupled with the amplifier, with the sampling component subtracting a first sample of the voltage signal from a second sample of the voltage signal to produce a difference value. The amplifier circuit further includes a gain component coupled with the sampling component to amplify the difference between the first sample and the second sample.

Abstract: The performance of precision analog integrated electronic circuits is directly related to the degree of matching between electrical circuit elements. Any residual mismatch of circuit elements after manufacturing must be calibrated out using numerous techniques such as adjusting potentiometers, trimming capacitors, modifying binary-weighted resistor strings, etc. Prior art matching techniques entail the use of large area circuit elements or a large number of elements arranged in a prescribed manner on the surface of a silicon die to minimize the residual calibration. The present invention utilizes a multiplicity of circuit elements that are interconnected in distinct groups to achieve a higher degree of element matching and the ensuing benefits thereof. The elements are interconnected to yield a prescribed minimum mismatch error.

Abstract: Equal common mode voltage is present at the input terminals of an operational amplifier with amplifies the residue signal in a stage of an ADC in two phases while reducing the noise introduced into the amplified signal. A reference capacitor is coupled between an input terminal of the operational amplifier and a reference voltage in a first phase, and between the input terminal and a the reference voltage but with opposite polarity in the second phase.

Abstract: Certain embodiments of the present invention relate to techniques for tuning or measuring operational features of amplifiers, such as the transconductance of operational transconductance amplifiers (OTAs) and the gain of variable gain amplifiers (VGAs). Each technique employs (at least) two phases that involve the application of different input voltages. The results of the multiple phases are then combined to generate a final result that negates or reduces the effects of real-world properties such as finite output impedances and offset voltages.

Abstract: A circuit having multiple overlapped feedback loops for DC offset cancellation is provided with applying in one of multistage amplifier, multistage filter, and the combination thereof. The circuit includes a plurality of negative feedback variable bandwidth switches coupled to each stage of the above mentioned multistage devices, the output of the last stage is coupled to an input of a low-pass filter loop. The circuit includes a plurality of variable gain amplifiers, output of each variable gain amplifier is coupled to the series contact of each stage respectively, and input of each variable gain amplifier is thereof coupled to an output of the low-pass filter loop. Therefore, the circuit achieves to cancel the DC offset for multistage overlapped feedback path with less area and low power consumption.

Abstract: A system, circuit, and method of canceling DC offset errors in cascaded amplifiers comprises arranging a plurality of any of analog voltage and analog current amplifier stages in any of cascaded and parallel configurations; operatively connecting a feedback comparator and digital logic in a feedback path around a given amplifier, wherein the digital logic comprises a finite state machine implementing an adaptive search algorithm comprising fixed switching and modulated switching; operatively connecting a switch at a differential input of the amplifier to short both input terminals of the amplifier; performing fixed switching on binary weighted elements generating discrete analog steps used to vary any of DC offset voltage and current at the input of the amplifier; and performing modulated switching on at least one lower least significant bit (LSB) of all bits used to vary the any of the DC offset voltage and current.

Abstract: A switched-capacitor amplifier circuit including first and second pairs of sampling capacitors for sampling a pair of input signals includes a voltage regulator coupled to receive a first reference voltage and generate a first regulated output voltage related to the first reference voltage and independent of a first power supply voltage; a clock signal generator generating first and second clock signals referenced to the first power supply voltage and third and fourth clock signals referenced to the first regulated output voltage; and a first set of switches coupling the bottom plates of the sampling capacitors to the amplifier, the first set of switches being controlled by the third and fourth clock signals. The circuit may further include a second set of switches coupling the top plates of the sampling capacitors to the input signals, the second set of switches being controlled by the first and second clock signals.

Abstract: The chopper stabilized amplifier circuit includes: an amplifier; a first current mirror coupled to an output of the amplifier through a first switch; a second current mirror coupled to the output of the amplifier through a second switch, wherein the first switch is operated out of phase with the second switch; and a summing node for combining currents from the first and second current mirrors.

Abstract: An operational amplifier for canceling an offset and continuously generating an output signal. The operational amplifier includes a first operational amplification unit and a second operational amplification unit each having at least one electrical characteristic that is substantially the same as one another. One of the operational amplification units performs a canceling operation (holding operation and compensation operation) of the offset voltage while the other operational amplification unit performs a non-canceling operation and generates the output voltage by amplifying an input voltage. Both operational amplification units alternately perform the canceling operation and the non-canceling operation.

Abstract: An input offset voltage corrector used in an operational amplifier includes a switch unit, a register unit, an offset voltage correction unit and a micro control unit. The micro control unit sets the register unit to control the switch unit to switch the input offset voltage corrector to different operating modes. If an input offset voltage corrector is set to the offset voltage correcting mode, the offset voltage correction unit will adjust the input offset voltage of the operational amplifier to output an exact signal. Furthermore, the input offset voltage corrector can adjust the input offset voltage anytime according to the operating conditions to maintain the best characteristic of the operational amplifier.

Abstract: Offset canceling amplifier circuit in which a high accuracy of output with a suppressed output offset is achieved and a variation in a slew rate is also suppressed, and a display device having the amplifier circuit. A first differential pair (M5, M6) connected between a first current source (M9) and a common load circuit (M1, M2) and a second differential pair (M3, M4) connected between a second current source (M8) between the common load circuit (M1, M2) are provided. A switch (SW1) connected between one input of the first differential pair (M5, M6) and an input terminal (1), a switch (SW2) connected between the one input of the differential pair (M5, M6) and an output terminal (2), a switch (SW3) connected between one input of the second differential pair (M3, M4) and the output terminal (2), and a capacitance element (C1) connected to the one input of the second differential pair (M3, M4) are provided.

Abstract: The present invention comprises switched capacitor amplifiers including positive feedback on semiconductor devices, wafers, and systems incorporating same and methods for amplifying signals using positive feedback, while maintaining a stable gain and producing an improved signal-to-noise ratio. One embodiment includes a switched capacitor amplifier comprising a CMOS amplifier, a feed-in switched capacitor, and a feedback switched capacitor. The feed-in switched capacitor couples an input signal to the non-inverting input of the CMOS amplifier. Similarly, the feedback switched capacitor couples the amplifier output to the non-inverting input to create a positive feedback loop. A capacitance of the feedback switched capacitor relative to a capacitance of the feed-in switched capacitor comprises a feedback proportion.

Abstract: A system, circuit, and method of canceling DC offset errors in cascaded amplifiers comprises arranging a plurality of any of analog voltage and analog current amplifier stages in any of cascaded and parallel configurations; operatively connecting a feedback comparator and digital logic in a feedback path around a given amplifier, wherein the digital logic comprises a finite state machine implementing an adaptive search algorithm comprising fixed switching and modulated switching; operatively connecting a switch at a differential input of the amplifier to short both input terminals of the amplifier; performing fixed switching on binary weighted elements generating discrete analog steps used to vary any of DC offset voltage and current at the input of the amplifier; and performing modulated switching on at least one lower least significant bit (LSB) of all bits used to vary the any of the DC offset voltage and current.

Abstract: An embodiment to mirror current having a pair of current mirroring transistors and a pair of cascode transistors coupled to the current mirror transistors, and furthermore having an amplifier to provide an offset voltage between the drain of a cascode transistor and the gate of a current mirror transistor, where the drain of the current mirror transistor is connected to the source of the cascode transistor, and where the amplifier buffers the gate of the current mirror transistor from the drain of the cascode transistor. Other embodiments are described and claimed.

Abstract: An operational amplifier capable of offset cancel in a shorter period, as well as a line driver capable of shortening one horizontal period and a liquid crystal display device are provided. In the operational amplifier of the invention, a time necessary for feed back control can be shortened than usual by a constitution that an output voltage VO in one horizontal period H1 which is one horizontal period before is defined as a reference voltage in an offset cancel preparatory period HC2, thereby changing the output voltage VO(2) only by the offset voltage VO(2) by the feed back control. In the line driver of the invention, the operational amplifier not used for the output of display data D1 to D6 conducts offset cancel operation and it is successively shifted on every one horizontal period. Since it is no more necessary to incorporate the offset cancel preparatory period in the output period, one horizontal period can be shortened further.

Abstract: In a chopper amplifier circuit operable at a low voltage utilizing a switched operational amplifier, a chopper modulator chopper-modulates an input signal according to a predetermined control signal, and outputs a chopper-modulated signal. An amplifier circuit constituted by the switched operational amplifier amplifies the chopper-modulated signal outputted from the chopper modulator, and outputs an amplified chopper-modulated signal. A chopper-demodulator of the switched operational amplifier chopper-demodulates the amplified chopper-modulated signal outputted from the amplifier circuit according to the control signal, and outputs a demodulated output signal as a chopper-amplified output signal from an output terminal. A chopper modulator chopper-modulates a demodulated signal outputted from the chopper demodulator according to the control signal, and outputs a chopper-modulated signal to an input terminal of the amplifier circuit.

Abstract: A limiting amplifier with an input stage with dc offset cancellation, identical gain stages, an output buffer and a feedback filter. The input stage receives a differential input signal and outputs a first intermediate differential signal. The gain stages are cascaded to amplify the first intermediate differential signal and generate a second intermediate differential signal, amplified by the output buffer to produce an output signal. The feedback filter provides a dc offset voltage of the output signal to the input stage for the dc offset cancellation. The input stage comprises a resistor network coupled between a pair of input nodes and a power line and comprising a common resistor, a pair of load resistors and a shunt resistor. The load resistors share a common terminal connected to the common resistor that is connected to the power line. The shunt resistor has two terminals respectively connected to the load resistors.

Abstract: Circuitry for use in a differential amplifier includes an input stage having a first differential amplifier and an offset compensation stage that includes at least one controllable current source. The offset compensation stage is connected to a bias input of the first differential amplifier. The circuitry includes an output stage having a second differential amplifier, where the output stage is after an output of the input stage, and a programmable resistor network for controlling an amplification of the input stage. The programmable resistor network controls the amplification in accordance with a feedback from the first differential amplifier.

Abstract: An amplifier circuit comprises a first amplifier having an input and an output. A second amplifier has an input that communicates with an output of the first amplifier. A third amplifier has an input that communicates with an input of the first amplifier. A fourth amplifier has an input that communicates with an output of the third amplifier and an output that communicates with the input of the second amplifier. A switched capacitance circuit selectively couples a capacitance to at least one of the input of the third amplifier and the output of third amplifier.

Abstract: Two nulling amplifiers are used with an auto-zeroed differential amplifier. While one nulling amplifier is compensating the main amplifier, the other nulling amplifier is being zeroed for both differential mode (DM) and common mode (CM) offsets. By using two nulling amplifiers, one always connected to the main amplifier, a relatively constant open-loop gain is maintained for the main amplifier. A further improvement is make-before-break timing overlap of the switch operations between the two nulling amplifiers and the main amplifier. This ensures that the main amplifier is continuously driven by one or both null amplifiers, thereby maintaining a low impedance at the main amplifier auxiliary port. Both DM and CM offset sampling and precharging of each of the two nulling amplifiers is performed so as to substantially reduce switching glitches in the output of the main amplifier.

Abstract: An offset voltage correction circuit for a differential amplifier comprising NMOS transistors serving as a pair of differential transistors, and PMOS transistors serving as a pair of load transistors connected between outputs of the pair of differential transistors and a power source. The offset voltage correction circuit is equipped with a voltage generator for generating, between a source of any one of the pair of load transistors and the power source, a constant voltage for correcting an offset voltage of the differential amplifier.

Abstract: Techniques and circuitry are provided for programmatically controlling signal offsets in integrated circuitry. In one embodiment, a buffer circuit having an offset cancellation circuit receives a signal and transmits the signal to programmable logic circuit. The programmable logic uses programmable resources and/or one or more algorithms to measure integrated circuit operations and/or operational errors associated with the offset. The control signal is fed back to an input of the offset cancellation circuit. In one embodiment, the offset cancellation circuit adjusts the offset of the signal in response to the magnitude of the offset cancellation signal received until changes associated with the offset and/or the magnitude of the operational errors are no longer attributable to the offset.

Abstract: An amplifying circuit includes an input chopping circuit, an amplifier, and an output chopping circuit. The input chopping circuit is operably coupled to chop an input signal at a chopping rate to produce a chopped input signal. The amplifier has a first input transistor section, a second input transistor section, and a transistor load section. The first and second input transistor sections are operably coupled to receive the chopped input signal, wherein the first input transistor section amplifies the chopped input signal when the chopped input signal is in first signal level range, the second input transistor section amplifies the chopped input signal when the chopped input signal is in a second signal level range, and the first and second input transistor sections amplify the chopped input signal when the chopped input signal is in a third signal level range, wherein the transistor load section is coupled to the first and second input transistors sections to produce an amplified chopped signal.

Abstract: A ping-pong amplifier with reduced glitching is described. The ping-pong amplifier includes a nulling amplifier coupled to a switching network. The switching network is used to auto-zero a ping amplifier within a ping-pong amplifier. The nulling amplifier drives the output of a ping amplifier to a proper output voltage level during auto-zeroing of the ping amplifier. By being at a proper output voltage level, glitches associated with transitioning between a ping amplifier and a pong amplifier are reduced or eliminated.

Abstract: A programmable gain amplifier includes an OP amplifier, N decayed capacitor(s), (N+1) adjusting capacitor modules, switches, a switch control module, and a feedback switch. First terminals of adjusting capacitors of the capacitor modules are connected together. One capacitor module is connected to an input terminal of the OP amplifier, and neighboring two of the capacitor modules are connected together through one of the decayed capacitor(s). Each switch controlled by the switch control module has a common terminal connected to a second terminal of the capacitor so as to couple the capacitor to an input signal, a reference voltage, or an output terminal of the OP amplifier. The feedback switch is connected between the output terminal and the first input terminal, and turns on in a first phase. The adjusting capacitor can be connected to the output terminal to serve as the feedback capacitance through control of the switches in a second phase, which does not overlap with the first phase.

Abstract: An amplifier circuit includes an input chopping circuit for chopping first and second input signals, a transconductance stage for amplifying an output of the chopping circuit and applying it to the input of a folded cascode stage, to the input of an un-chopping circuit, and to the input of a chopper-stabilized gain boost amplifier. The output of the un-chopping circuit drives sources of cascode transistors of the folded cascode stage. The gain boost amplifier includes another transconductance stage having another un-chopping circuit coupled to the gate of one of the cascode transistors of the folded cascode stage. The drains of cascode transistors of the folded cascode stage drive a class AB output stage. The amplifier provides both highly linear operation and low 1/f noise.

Abstract: An amplifier arrangement and a method for compensating for an offset in an amplifier is provided. A respective switch for connecting together the inputs in a compensation operating mode and for interrupting the feedback path in this operating mode is provided in an amplifier. A control device detects an output signal and drives a controllable current source, which can be coupled to one of the two inputs of the amplifier, in such a manner that a compensation current which minimizes the offset is provided. The arrangement and method can be used, for example, in transmission arrangements.

Abstract: An amplification system capable of reducing DC offset in a baseband signal, which has first and second differential output terminals, first and second low pass filters, and first and second amplifiers. The first low pass filter filters a first input signal to thus generate a first filtered signal. The first amplifier amplifies the first input signal and the first filtered signal to thus generate a first amplified signal. The second low pass filter filters a second input signal to thus generate a second filtered signal. The second amplifier amplifies the second input signal and the second filtered signal to thus generate a second amplified signal. The system couples the first and second amplified signals at the first and the second differential output terminals to thus reduce the DC offset of a differential voltage signal output by the first and second differential output terminals.

Abstract: An amplifier (10) includes a first stage (4) including differentially coupled first (Q1) and second (Q2) input transistors and a controlled active load circuit (6). A second stage (8) includes differentially coupled third (Q5) and fourth (Q6) input transistors and a load circuit (Q7,8). A first output (2A) of the first stage (4) is coupled to a first input of the second stage (8), a second output (2B) of the first stage (4) being coupled to a second input of the second stage (8). A common mode feedback amplifier (12) has an input coupled to receive a common mode signal (3) from the second stage (8) for producing an amplified common mode signal (9) on a control input of the controlled active load circuit (6) to provide fast settling of an output (Vout) of the second stage without substantially increasing amplifier noise.

Abstract: There is a need for providing a variable amplifier circuit suited for a semiconductor integrated circuit and a high-performance camera preprocessing LSI using the variable amplifier circuit. At first timing, a first input capacitor acquires a first signal. An amplifier circuit amplifies a second signal acquired to the second input capacitor according to a gain corresponding to a capacity ratio between the second input capacitor and a feedback capacitor composed of a variable capacitor device. At second timing, the second input capacitor acquires a second signal. The amplifier circuit amplifies the first signal according to a gain corresponding to a capacity ratio between the first input capacitor and the feedback capacitor. A variable gain amplifier circuit interleavingly amplifies the first signal and the second signal in synchronization with the first timing and the second timing.

Abstract: Chopper amplifiers and methods of amplification are provided. A circuit includes an adjustable modulation resistance network, an amplifier, and an adjustable feedback resistance network. The adjustable modulation resistance network receives and modulates an input signal to produce a modulated signal including varying an input resistance, which includes a switch resistance. The amplifier has an input and an output. The adjustable feedback resistance network varies a feedback resistance, which includes a switch resistance. In addition, a suppression circuit is also included that can produce the feedback signal for preventing the direct current offset signal from substantially affecting the output signal.