With Periodic Switching Input-output (e.g., For Drift Correction) Patents (Class 330/9)
  • Publication number: 20090278597
    Abstract: An operational amplifier (1B) amplifies an input signal (Vin) to produce an output signal (Vout), and includes a 3-stage amplifier (1C) including a first amplifier stage (2) receiving the input signal, a second amplifier stage (3) driven by the first amplifier stage (2), and a third amplifier stage (4) driven by the second amplifier stage to produce the output signal. A slew detection current (Idetect) is generated when the input signal (Vin) exceeds a certain magnitude, and is converted to a control signal (41) that operates a switch (MN0) to short-circuit output conductors of the first amplifier stage to prevent signal charge from building up on capacitances associated with the output of the first amplifier stage during slewing. The three stage amplifier can be a chopper-stabilized, notch-filtered amplifier.
    Type: Application
    Filed: May 7, 2008
    Publication date: November 12, 2009
    Inventors: Joy Y. Zhang, Viola Schaffer
  • Publication number: 20090273395
    Abstract: A preamplifier includes cascade-connected amplifying circuits, and at least one of the cascade-connected amplifying circuits includes a differential switch pair circuit, a comparator and current sources. The differential switch pair circuit has a pair of differential inputs and a pair of differential outputs. The comparator outputs a comparison signal by comparing the differential outputs. The current sources are respectively and selectively coupled to one of the differential outputs based on the comparison signal to adjust voltages of the differential outputs. A method for calibrating offset voltages in a preamplifier is also disclosed herein.
    Type: Application
    Filed: May 5, 2008
    Publication date: November 5, 2009
    Inventor: Chih-Haur Huang
  • Publication number: 20090267687
    Abstract: A chopper-stabilized amplifier has switching networks arranged to support a high frequency clocking signal and to provide a high common mode rejection and a high rejection of an offset component of an input signal. A magnetic field sensor includes a Hall effect element coupled to a modulation circuit. The modulation circuit provides a signal to the chopper-stabilized amplifier. The chopper-stabilized amplifier provides an output signal to a low pass filter, which provides an output signal from the magnetic field sensor.
    Type: Application
    Filed: April 29, 2008
    Publication date: October 29, 2009
    Inventors: Hernan D. Romero, Gerardo Monreal
  • Patent number: 7605647
    Abstract: A chopper-stabilized amplifier has switching networks arranged to support a high frequency clocking signal and to provide a high common mode rejection and a high rejection of an offset component of an input signal. A magnetic field sensor includes a Hall effect element coupled to a modulation circuit. The modulation circuit provides a signal to the chopper-stabilized amplifier. The chopper-stabilized amplifier provides an output signal to a low pass filter, which provides an output signal from the magnetic field sensor.
    Type: Grant
    Filed: April 29, 2008
    Date of Patent: October 20, 2009
    Assignee: Allegro Microsystems, Inc.
    Inventors: Hernan D. Romero, Gerardo Monreal
  • Patent number: 7605646
    Abstract: An instrumentation amplifier includes first (11A) and second (12A) input amplifiers having outputs (15A,B) coupled to an output amplifier (13). A first auto-zero stage (20) in the first input amplifier is auto-zeroed to a first voltage level (VREFL), a first input signal (Vin+) is amplified by a second auto-zero stage (24) in the first input amplifier, and the amplified first input signal is coupled to the output amplifier, during a first phase (A). A third auto-zero stage (44) in the second input amplifier is auto-zeroed to a second voltage level (VREFH), a second input signal (Vin?) is amplified by a fourth auto-zero stage (40) in the second input amplifier, and the amplified second input signal is coupled to the output amplifier, during a second phase (B). The second auto-zero stage is auto-zeroed to the first voltage level, the first input signal is amplified by the first auto-zero stage (20), and the amplified first input signal is coupled to the output amplifier, during a third phase (C).
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: October 20, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Dimitar T. Trifonov, Tony R. Larson, Jerry L. Doorenbos
  • Patent number: 7602237
    Abstract: In an amplifying circuit, a first and a second switches are provided between an input terminal and output terminal of coupling capacitor and amplifier, and these switches are set in OFF state in a power-down state, and the second switch is turned on for a specified period when changed over to ordinary operation, and the capacitor is charged to a bias voltage corresponding to direct-current operating point, and then the second switch is turned off, and the first switch is turned on, and the mode is shifted to the ordinary operating state. Therefore, in a power-down state, a popping noise can be suppressed without resort to a charger for preliminarily charging the capacitor in a power-down state, and increase of current consumption due to charger is eliminated.
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: October 13, 2009
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Nobuyuki Shimizu
  • Patent number: 7598801
    Abstract: A voltage regulator and a voltage regulating method thereof and a voltage generator using the voltage regulator are disclosed by the present invention. The voltage regulator of the present invention uses a first switching unit and a second switching unit to respectively provide an operational transconductance amplifier (OTA) with different closed-loop feedback paths during a first period and a second period. In this way, an auto-zeroing unit is able to exactly store an input offset voltage presented between the inverting input terminal and the non-inverting input terminal of the OTA.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: October 6, 2009
    Assignee: Novatek Microelectronics Corp.
    Inventors: Chih-Jen Yen, Chih-Yuan Hsieh
  • Patent number: 7595648
    Abstract: A read device of a capacitive sensor includes: a signal source supplying an electrical read signal for driving the capacitive sensor; and a discrete-time sense circuit for generating an electrical output signal, correlated to variations of capacitance of the capacitive sensor, in response to variations of the electrical read signal. The device moreover includes: a modulator stage for generating a modulated electrical read signal on the basis of the electrical read signal and supplying the modulated electrical read signal to the capacitive sensor; a demodulator stage, connected to the sense circuit, for demodulating the electrical output signal and generating a demodulated electrical output signal; and a low-pass filtering stage for generating a filtered electrical output signal, on the basis of the modulated electrical output signal.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: September 29, 2009
    Assignee: STMicroelectronics S.r.l.
    Inventors: Tommaso Ungaretti, Ernesto Lasalandra
  • Publication number: 20090231029
    Abstract: A circuit with an input acquisition loop and an output acquisition loop is used to compensate for the input offset voltage and bias current errors of an operational amplifier.
    Type: Application
    Filed: May 28, 2008
    Publication date: September 17, 2009
    Applicant: EXAR CORPORATION
    Inventor: Richard W. Randlett
  • Patent number: 7589587
    Abstract: In a feedback amplifier circuit, a first switching device executes an auto-zero operation by inputting a signal outputted from an amplifier to an input terminal of the amplifier during an auto-zero operation interval prior to an amplification interval. A first capacitor accumulates and holds an offset voltage at the output terminal of the amplifier during the auto-zero operation interval, and cancels an offset voltage at the input terminal of the amplifier by an accumulated and held offset voltage during an amplification interval subsequent to the auto-zero operation interval. A second switching device grounds the feedback point of the feedback circuit during the auto-zero operation interval. A second capacitor blocks a DC voltage, and accumulates and holds an offset voltage at an output terminal of the amplifier, and cancels an offset voltage at an input terminal of the amplifier by the accumulated and held offset voltage during an amplification interval.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: September 15, 2009
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Takeshi Yoshida, Yoshihiro Masui, Atsushi Iwata, Kunihiko Gotoh
  • Patent number: 7586368
    Abstract: A chopper-stabilized amplifier (1B) having a first output (25) includes an input chopper (9) for chopping an input signal and applying it to the input of a first amplifier (2) and an output chopper (10) for chopping an output signal of the first amplifier and applying it to the input of a switched capacitor notch filter (30-1).
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: September 8, 2009
    Assignee: Texas Instruments Incorproated
    Inventor: Dimitar T. Trifonov
  • Patent number: 7583166
    Abstract: The present invention provides an apparatus for enhancing Q factor of an inductor. The apparatus includes a negative resistance generator coupled to the inductor for providing a negative resistance, and a bias circuit coupled to the negative resistance generator for biasing the negative resistance generator.
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: September 1, 2009
    Assignee: Realtek Semiconductor Corp.
    Inventors: Ying-Yao Lin, Ying-Hsi Lin
  • Publication number: 20090212856
    Abstract: An amplifier having DC offset compensation includes at least one input node and a pair of differential output nodes, a biasing circuit coupled to the input node; and a plurality of current sources.
    Type: Application
    Filed: May 8, 2009
    Publication date: August 27, 2009
    Applicant: AGERE SYSTEMS INC.
    Inventors: Jinghong Chen, Gregory W. Sheets, Joseph Anidjar, Robert J. Kapuschinsky, Lane A. Smith
  • Patent number: 7579885
    Abstract: A high dynamic range amplifier circuit for amplifying pixel signals of an imager device is disclosed. The amplifier circuit uses a read-out scheme based on a charge recycling approach, where a pixel signal is first amplified with a low gain during a first amplification phase T1, and then the amplifier output is immediately recycled and the pixel signal amplified with a higher gain during a second amplification phase T2.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: August 25, 2009
    Assignee: Aptina Imaging Corporation
    Inventor: Giuseppe Rossi
  • Patent number: 7576603
    Abstract: Operational amplifier circuitry drives a device which may be run with a combination of output signals fewer in number than the output signals delivered from plural output circuits. Each output circuit adjusts the gain of an input signal supplied to its operational amplifier. An output selector selects and outputs output signals from the output circuits necessary for driving the device. A decision circuit compares an output signal not selected with a reference signal to adjust the gain of the output circuits to thereby cancel the offset of the operational amplifier. The operational amplifier has sets of feedback elements different in number between the sets formed by capacitances. Switching is made from one set to another until the decision circuit makes an acceptable decision. Offset may thus be canceled during the operational amplification even in case capacitive or resistance element is connected in circuit outside the operational amplifier.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: August 18, 2009
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Koji Higuchi
  • Patent number: 7576602
    Abstract: The present invention provides a circuit that utilizes OP-sharing technique. The circuit includes an amplifier, a first application circuit, a second application circuit, and a reset circuit. The first application circuit drives the amplifier during at least a first working period. The second application circuit drives the amplifier during at least a second working period. The reset circuit resets the amplifier during at least a third working period. The third working period is between the first working period and the second working period.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: August 18, 2009
    Assignee: Realtak Semiconductor Corp.
    Inventor: Cheng-Jui Chen
  • Patent number: 7573327
    Abstract: An embodiment of the present invention is directed to an instrumentation amplifier. The amplifier includes a first amplification sub-circuit, which includes an input stage for sensing a differential input and generating an intermediate current based thereon, a feedback stage, and an auto-zeroing circuit. The feedback stage is operable to generate a feedback current based on an output voltage of the amplifier. The auto-zeroing circuit is operable to generate a nulling current, which compensates for errors in the intermediate and feedback currents resulting from input offsets in the input and feedback stages. The amplifier further includes a second amplification sub-circuit, an output stage, and a switching circuit. The switching circuit switches the amplifier between first and second configurations. In the first configuration, the first amplification sub-circuit provides a first amplification path for the amplifier.
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: August 11, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Michiel Pertijs, George Reitsma
  • Patent number: 7573334
    Abstract: Embodiments of the invention comprise methods, apparatuses and systems for a dynamic bias control circuit configured to dynamically bias an amplifier. The dynamic bias control circuitry includes four branches. Each of the four branches includes a transistor operably coupled in series between a current source and a reference voltage. Each branch also includes a storage element having a first terminal and a second terminal and configured for selectively coupling the first terminal to the reference voltage, selectively coupling the first terminal to a node located between the current source and a drain of the transistor, selectively coupling the second terminal to the node, and selectively coupling the second terminal to an output.
    Type: Grant
    Filed: September 19, 2007
    Date of Patent: August 11, 2009
    Assignee: Aptina Imaging Corporation
    Inventor: Ramy Salama Tantawy
  • Publication number: 20090195306
    Abstract: A switched-capacitor circuit includes a plurality of cascaded differential-input, single-ended-output amplifiers. A negative feedback path, from an output terminal of a last of the cascaded amplifiers to an input terminal of a first of the cascaded amplifiers, is configured to exclude, and not be shorted out by, any switches.
    Type: Application
    Filed: August 20, 2008
    Publication date: August 6, 2009
    Applicant: ANALOG DEVICES, INC.
    Inventors: Iliana Fujimori CHEN, Christopher W. MANGELSDORF
  • Publication number: 20090195305
    Abstract: Methods and systems for implementing an analog switch controller to improve linearity of analog switches are described.
    Type: Application
    Filed: February 6, 2008
    Publication date: August 6, 2009
    Applicant: Infineon Technologies AG
    Inventors: Fabio Ballarin, Martin Clara, Thomas Ferianz
  • Publication number: 20090195315
    Abstract: A sample-and-hold amplifier is provided. The sample-and-hold amplifier comprises a sample-and-hold circuit and a buffer circuit. The sample-and-hold circuit receives an input signal and transmits the input signal to a first node according to a control signal. The buffer circuit is coupled between a supply voltage source and a ground and controlled by the first node to provide an output signal at an output node. The buffer circuit comprises a native MOS transistor coupled to the output node.
    Type: Application
    Filed: January 22, 2009
    Publication date: August 6, 2009
    Applicant: MEDIATEK INC.
    Inventor: Yu-Kai Chou
  • Patent number: 7567121
    Abstract: A current-mode instrumentation amplifier (IA) error reduction circuit and method employs a current-mode IA topology and an auto-zero circuit. The IA receives a differential voltage (VINP?VINN) and produces differential DC currents (IDC1, IDC2) in response, which are summed to produce the amplifier's output current. Ideally, when VINP=VINN, IDC1 and IDC2 will be equal; however, due to mismatches an error component Ierror will be present such that IDC1=IDC2±Ierror. The auto-zero circuit is employed to reduce the magnitude of Ierror. In operation, in an ‘auto-zero mode’, VINP and VINN are connected together and the auto-zero circuit operates to make IDC1=IDC2; a voltage needed to effect this is stored. Then, in ‘normal mode’, VINP and VINN are disconnected from each other and the IA is placed in the signal path, with the stored voltage acting to keep the magnitude of Ierror low.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: July 28, 2009
    Assignee: Analog Devices, Inc.
    Inventors: Thomas L. Botker, Benjamin A. Douts
  • Patent number: 7564310
    Abstract: An amplifier for improving an electrostatic discharge (ESD) characteristic includes an operational amplifier, a first resistor circuit, a first fuse box, a second resistor circuit, and a second fuse box. The operational amplifier includes a first input terminal receiving a first input signal, a second input terminal receiving a second input signal, and an output terminal outputting an output signal. The first resistor circuit is connected between the second input terminal and a first node to prevent ESD from being input to the second input terminal. The first fuse box is connected between the first node and the output terminal of the operational amplifier. The second resistor circuit is connected between the second input terminal and a second node to prevent ESD from being input to the second input terminal. The second fuse box is connected between the second node and a terminal for receiving a ground voltage.
    Type: Grant
    Filed: June 18, 2007
    Date of Patent: July 21, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kim Yo-Jong
  • Patent number: 7560969
    Abstract: A receiver of a high speed digital interface includes at least one differential amplifier, a pair of resistive elements, a current source and a pair of transistors. The differential amplifier receives a small differential signal at a pair of input terminals and outputs an amplified differential signal. Each of the resistive elements has one end coupled to one of the input terminals of the differential amplifier and the other end receiving a reference voltage. The pair of transistors has drains respectively coupled to the input terminals of the differential amplifier, sources commonly coupled to the current source and gates receiving a differential feedback signal derived from the amplified differential signal.
    Type: Grant
    Filed: September 10, 2007
    Date of Patent: July 14, 2009
    Assignee: Himax Technologies Limited
    Inventor: Yuan-Kai Chu
  • Patent number: 7557649
    Abstract: In a DC offset cancellation circuit, an operational amplifier is provided with an inverse terminal, a non-inverse terminal and an output terminal. A first resistor is connected to the non-inverse terminal. A second resistor connected between the inverse terminal and the output terminal. A DC offset cancellation resistor is connected between the inverse terminal and the non-inverse terminal. Also, in each of first and second DC offset cancellation circuits of the programmable gain amplifier, an operational amplifier is provided with an inverse terminal, a non-inverse terminal and an output terminal. A first resistor is connected to the non-inverse terminal. A second resistor is connected between the inverse terminal and the output terminal. A DC offset cancellation circuit is connected between the inverse terminal and the non-inverse terminal. Here, the first and second DC offset cancellation circuits are connected with each other in series.
    Type: Grant
    Filed: March 12, 2007
    Date of Patent: July 7, 2009
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Sang Gyu Park, Chang Soo Yang, Kwang Du Lee
  • Patent number: 7557650
    Abstract: A generator capable of supplying one or more output signals with a modulated cyclic ratio includes one or more formatting circuits each processing one input signal and one or more class D amplifiers powered with a power supply voltage and being driven by a corresponding one of the formatting circuits. Each formatting circuit has a counter-reaction loop and uses a reference voltage for which the average value is equal to half the power supply voltage. The corresponding output signal is thus corrected for any variations in the power supply voltage.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: July 7, 2009
    Assignee: STMicroelectronics S.A.
    Inventors: Olivier Giraud, Roger Petigny, Philippe Marguery
  • Patent number: 7557648
    Abstract: An operational amplifier according to an embodiment of the present invention includes: an operational amplifier stage executing differential-amplification of an input voltage and a reference voltage; a source-grounded amplifier stage outputting the differential-amplified signal; a phase compensation capacitance compensating for a phase of an output signal; and a charge/discharge control circuit controlling charge/discharge of the phase compensation capacitance.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: July 7, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Kuniyuki Okuyama
  • Publication number: 20090167430
    Abstract: A switched-capacitor amplifier arrangement and a method to amplify a signal are presented. A forward path has at least one switched capacitor (10) controlled by a clock signal, thus providing an amplification phase (1) of the forward path and an additional clock phase (2). A damping means (22) is connected to the forward path, the damping means being designed for attenuation of the signal peak at the beginning (2p) of the amplification phase. This avoids an undesired feed forward effect at the beginning of the.
    Type: Application
    Filed: October 26, 2006
    Publication date: July 2, 2009
    Applicant: Austriamicrosystems AG
    Inventor: Vivek Sharma
  • Patent number: 7554389
    Abstract: A differential amplifier comprises first, second, and third input terminals (1, 2, and 3), output terminal (4), first and second differential pairs (531 and 532) (533 and 534) driven by a corresponding current source and having output pairs commonly connected to load circuits (537 and 538), and an amplifier stage (539) having input end connected to at least one of the common connection points of the load circuits and output pairs of the first and second differential pairs and output end connected to output terminal. Input pair of second differential pair receives a signal from third input terminal and a feedback signal from output terminal.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: June 30, 2009
    Assignee: NEC Corporation
    Inventors: Hiroshi Tsuchi, Masao Iriguchi
  • Publication number: 20090153241
    Abstract: A chopper-stabilized amplifier (1B) having a first output (25) includes an input chopper (9) for chopping an input signal and applying it to the input of a first amplifier (2) and an output chopper (10) for chopping an output signal of the first amplifier and applying it to the input of a switched capacitor notch filter (30-1).
    Type: Application
    Filed: December 13, 2007
    Publication date: June 18, 2009
    Inventor: Dimitar T. Trifonov
  • Publication number: 20090140802
    Abstract: The present invention is directed to reduce offset error voltage in a signal source impedance of analog input signal voltage supplied to an input terminal due to input offset voltage of an operational amplifier in a sampling circuit or a multiplexer coupled to an input terminal of an A/D converter. A semiconductor integrated circuit has an A/D converter and a sampling circuit. The sampling circuit samples an analog input signal in first and second sample modes. The A/D converter converts the sampled analog signal to a digital signal in a conversion mode. By switching of an internal circuit of an operational amplifier between the first and second sample modes, the functions of a non-inverting input terminal (+) and an inverting input terminal (?) realized by first and second input terminals are switched. Synchronously with the switching, supply of an analog signal to the non-inverting input terminal by input switches is also switched.
    Type: Application
    Filed: November 25, 2008
    Publication date: June 4, 2009
    Inventors: Akira KITAGAWA, Akihiro Kitagawa
  • Patent number: 7538605
    Abstract: An amplifier device capable of reducing offset voltage includes an offset-voltage cancellation device, an input stage circuit, an output stage circuit, a pseudo output stage circuit, a switch circuit, and an output end. The switch circuit is coupled to the input stage circuit, the output stage circuit, and the pseudo output stage circuit, and is utilized for transmitting an amplified signal provided by the input stage circuit to the output stage circuit and transmitting a first feedback voltage provided by the output stage circuit to the input stage circuit or transmitting the amplified signal provided by the input stage circuit to the pseudo output stage circuit and transmitting a second feedback voltage provided by the pseudo output stage circuit to the input stage circuit according to an operating mode.
    Type: Grant
    Filed: July 1, 2007
    Date of Patent: May 26, 2009
    Assignee: NOVATEK Microelectronics Corp.
    Inventor: Chih-Jen Yen
  • Patent number: 7538606
    Abstract: According to one embodiment, a system for constant bandwidth DC offset correction in an amplifier includes a number of amplifier stages having an input and an output coupled together in series. The system for constant bandwidth DC offset correction further includes a number of DC offset correction feedback loops which include a variable gain transconductor coupled to an integration capacitor further coupled to a fixed gain transconductor. Each of the DC offset correction feedback loops are coupled to the input and output of each of the number of amplifier stages. The transconductance of the variable gain transconductor in each of the number of DC correction feedback loops is varied in relation to a gain of the number of amplifier stages, such that the DC offset correction feedback loops provide DC offset correction while maintaining a constant bandwidth.
    Type: Grant
    Filed: April 25, 2008
    Date of Patent: May 26, 2009
    Assignee: Skyworks Solutions, Inc.
    Inventor: David S. Ripley
  • Patent number: 7538604
    Abstract: A circuit including a first sensitive node, a first component connected between the first sensitive node and a first terminal of a first switch, said first switch controlled by a first control signal variable between a supply voltage level and a second voltage level, and a second switch including a first terminal connected to the first terminal of said first switch, and a second terminal connected to a clean voltage supply, said second switch controlled to connect the first node of said first switch to said clean voltage supply when said first switch is in a non-conducting state.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: May 26, 2009
    Assignees: STMicroelectronics S.A., STMicroelectronics Design and Application s.r.o.
    Inventors: Hynek Saman, Peter Murin, Martin Boksa, Pavel Panus
  • Patent number: 7538595
    Abstract: The present invention provides a $ for canceling DC offset, comprising: a first circuit accumulating a first square value of a plurality of signal values in a time period; a second circuit calculation a second square value of an accumulation of said signal values in said time period, wherein said square value is divided by a quantity of said signal values in said time period to generate a DC offset value; and a third circuit, connected to said first circuit and second circuit, calculating a difference between said first square value and said DC offset value.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: May 26, 2009
    Assignee: Alcor Micro, Corp.
    Inventors: Chi-Tung Chang, Chuen-Heng Wang, Yu-Ling Chen
  • Publication number: 20090128232
    Abstract: A switch-capacitor (“SC”) amplifier includes a two-stage operational amplifier (“OP-AMP”), an input SC network, and a feedback SC network. The two-stage OP-AMP includes a first OP-AMP stage having an output coupled to an input of a second OP-AMP stage. The input SC network is coupled to an input of the first OP-AMP stage. The feedback SC network is configured to selectively couple the output of the first OP-AMP stage to the input of the first OP-AMP stage during a first phase of operation of the scamplifier and to couple an output of the second OP-AMP stage to the input of the first OP-AMP stage during a second phase of operation of the SC amplifier.
    Type: Application
    Filed: November 16, 2007
    Publication date: May 21, 2009
    Applicant: Omnivision Technologies, Inc.
    Inventors: Liping Deng, Tiejun Dai, Haidong Guo, Chieh-Chien Lin, Yu-Shen Yang
  • Patent number: 7535295
    Abstract: Chopper stabilized amplifiers combining low clock noise and linear frequency characteristics. The chopper stabilized amplifiers are used in offset correction circuitry, with the output of the chopper stabilized amplifiers being integrated by an integrator. The integrator operates on alternate cycles, with a sample and hold circuit sampling the integrator output when the integrator is not integrating, with the output of the sample and hold being coupled to the main amplification path to cancel offset after at least some amplification is achieved. Autozeroing of amplifiers in the offset correction circuitry is also disclosed. The invention is applicable to operational amplifiers and instrumentation amplifiers.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: May 19, 2009
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Johan Hendrik Huijsing, Kofi Anthony A. Makinwa, Johan Frederik Witte
  • Patent number: 7535302
    Abstract: To reduce the apparent effect of offset voltage by making the offset voltage spatially scattered.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: May 19, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Kouichi Nishimura, Atsushi Shimatani
  • Patent number: 7535294
    Abstract: An offset cancellation amplifier where during a first period of a data output period, an output voltage and a reference voltage are supplied to the gates of a first differential pair, and the output voltage is accumulated in first and second capacitors while an input voltage is supplied in common to the gates of a second differential pair. During a second period, the output voltage is accumulated in the first capacitor, while the reference voltage is accumulated in the second capacitor. During a third period, the gates of the first differential pair cease to be supplied with the output voltage and with the reference voltage, respectively, and are supplied with the voltages accumulated in the first and second capacitors, respectively. The gates of the second differential pair are supplied with the output voltage and with the input voltage, respectively.
    Type: Grant
    Filed: February 22, 2007
    Date of Patent: May 19, 2009
    Assignee: NEC Corporation
    Inventor: Masao Iriguchi
  • Patent number: 7535293
    Abstract: A preamplifier circuit includes a differential amplifying unit, an offset detection unit and a reference signal generation unit. The differential amplifying unit compares an input signal pair with a reference signal pair to generate an output signal pair. The offset detection unit detects an offset of the output signal pair received from the differential amplifying unit to generate a calibration signal in an offset calibration mode. The reference signal generation unit adjusts the reference signal pair based on the calibration signal, and the reference signal pair is fed-back to the differential amplifying unit.
    Type: Grant
    Filed: February 27, 2007
    Date of Patent: May 19, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Young-Chan Jang
  • Patent number: 7532065
    Abstract: An amplifier having DC offset compensation includes at least one input node and a pair of differential output nodes, a biasing circuit coupled to the input node; and a plurality of current sources.
    Type: Grant
    Filed: May 24, 2006
    Date of Patent: May 12, 2009
    Assignee: Agere Systems Inc.
    Inventors: Jinghong Chen, Gregory W. Sheets, Joseph Anidjar, Robert J. Kapuschinsky, Lane A. Smith
  • Publication number: 20090115507
    Abstract: A method and apparatus for reducing settling time of a switched capacitor amplifier. The method includes disconnecting first and second capacitors from an amplifier. When the first and second capacitors are disconnected from the amplifier, they are charged by respective first and second input signals. The apparatus includes a plurality of sampling capacitors, each configured to sample a respective one of a plurality of signals during a sampling phase, an amplifier, and a plurality of decoupling switches configured to isolate the sampling capacitors from the amplifier during the sampling phase and to connect the plurality of sampling capacitors to the amplifier during the amplifying phase.
    Type: Application
    Filed: November 2, 2007
    Publication date: May 7, 2009
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Taehee Cho
  • Patent number: 7528654
    Abstract: An analog transconductance amplifier includes an input stage including a first transistor and a second transistor connected in series to the first transistor. The first and second transistors are connected between positive and negative voltages and are respectively controlled by an input voltage and a first control voltage for generating a normalized drive voltage. An amplification stage includes a first conduction path including an amplification transistor controlled by the normalized drive voltage. A first load transistor is connected in series to the amplification transistor and is controlled by a second control voltage. A second conduction path includes at least one second load transistor controlled by a third control voltage. A current mirror forces through the second conduction path a replica of current flowing through the first conduction path. An output stage transistor delivers an output current, and is controlled by a voltage on the second load transistor.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: May 5, 2009
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Giovanni Sicurella, Manuela La Rosa, Donata Rosaria Nicolosi
  • Publication number: 20090108929
    Abstract: Apparatuses and methods for providing offset compensation include a primary amplifier which includes a first output, a second output, a first load input, and a second load input, a first feedback loop connected to the primary amplifier and which includes a first switch located between the first output of the primary amplifier and the first load input, and a first sampling capacitor coupled to the first switch between the first switch and the first load input and a second feedback loop connected to the primary amplifier and which includes a second switch located between the second output of the primary amplifier and the second load input, and a second sampling capacitor coupled to the second switch between the second switch and the second load input.
    Type: Application
    Filed: October 30, 2007
    Publication date: April 30, 2009
    Inventor: Hai Yan
  • Patent number: 7525375
    Abstract: A method is disclosed for correcting transfer errors of an analog amplifier that occur following a jump in the amplifier input signal caused by switching. A measuring device includes at least one sensor as well as a signal-processing unit connected to the sensor and analog amplifier. The signal-processing unit includes at least one modulator and/or a multiplexer, an analog amplifier and at least one processing stage following the analog amplifier in the circuit chain. The processing stage, dependent on the point in time when the switching jump occurs, is separated from the latter during a predetermined timeout phase duration by means of a switch that is arranged between the analog amplifier and the processing stage and is controlled by a timeout controller, and/or dependent on the point in time when the switching jump occurs, said processing stage is blocked by a timeout controller during a predetermined timeout phase duration.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: April 28, 2009
    Assignee: Mettler-Toledo AG
    Inventors: Cyrill Bucher, Daniel Reber, Philip R. Ouellette
  • Publication number: 20090102558
    Abstract: An operational amplifier includes a first differential stage, a second differential stage, a second cascade amplifier stage, an output unit, a first switching control unit and a second switching control unit. When an external signal for stopping operation is input, the first switching control unit shuts off a connection between a non-inverting input terminal and a control electrode of one input transistor at each first and second differential stage, and shuts off a connection between an inverting input terminal and a control electrode of another input transistor at the first and second differential stages, and the second switching control unit connects the negative-side power supply voltage terminal to each control gate of the input transistors at the first and second differential stages and to the substrate gates of the input transistors at the first differential stage.
    Type: Application
    Filed: October 15, 2008
    Publication date: April 23, 2009
    Inventor: KOICHIRO ADACHI
  • Patent number: 7521994
    Abstract: A CMOS output stage operates in A/B push-pull mode and is driven with a control potential (ud) from a preamplifier stage via a control line (st). The control line (st) feeds the gate terminals of a complementary transistor pair (kt), the first transistor (n1) of which is used as first push-pull output transistor and the second transistor (p1) of which is connected to the gate terminal of a second push-pull output transistor (pa) via a current balancing arrangement. The source terminal of the first and of the second transistor (n1, p1) is connected to a first and, respectively, to a second fixed potential (u1, u2), the second fixed potential (u2) being stabilised in a low-impedance manner by an active compensation circuit (K).
    Type: Grant
    Filed: September 20, 2007
    Date of Patent: April 21, 2009
    Assignee: MICRONAS GmbH
    Inventors: Ulrich Theus, Juergen Kessel
  • Patent number: 7518440
    Abstract: A dual path chopper-stabilized amplifier (100) includes first (11) and second (11A) chopping/notch-filtering paths, each including an input chopper (9,9A), a transconductance amplifier (2,2A), and a notch filter (15,15A). Chopping and notch filtering in the first path are controlled by first (CHOPCLK) and second (FILTERCLK) clock signals, respectively. Chopping and notch filtering in the second path are controlled by the second (FILTERCLK) and first (CHOPCLK) clock signals, respectively. Outputs of the first (15) and second (15A) switched capacitor notch filters are combined to provide an amplifier output signal (23A,B) that updates a capacitance (C4) at 4 times the frequency of the filter clock signal, to thereby improve amplifier stability without increasing clock frequency.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: April 14, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Dimitar T. Trifonov
  • Patent number: 7518443
    Abstract: An amplifier circuit with current noise reduction employs first and second variable impedance devices between a signal source and an amplifier. A modulation frequency generator establishes a modulation frequency fmod to alter the first and second impedance values out of phase from one another at the modulation frequency so that the sum of the first and second impedance values at the input of the amplifier is relatively constant. The modulation at frequency fmod shifts the signal to side bands about the modulation frequency. The output from the amplifier is passed to a bandpass filter centered on the modulation frequency in order to remove all frequencies outside the bandwidth of interest. The signal itself is recovered by demodulating the output of the bandpass filter using a synchronization signal that is derived from the modulation signal.
    Type: Grant
    Filed: September 9, 2005
    Date of Patent: April 14, 2009
    Assignee: Quantum Applied Science & Research, Inc.
    Inventor: Robert Matthews
  • Patent number: 7518439
    Abstract: An amplifier circuit uses capacitor as voltage sources so that the amplifier can achieve high precision gain without either ratioed capacitors or absolute value of capacitors or resistors. In one embodiment, the amplifier circuit includes two or more capacitors that are each charged up to the input voltage during the sample phase. Then, during the hold phase, the switching network operates to connect the two or more capacitors in series between the input and output terminals of an operational amplifier, thereby generating an output voltage being N times the input voltage, N being the total number of capacitors connected in series. The amplifier circuit of the present invention is capable of achieving very high precision gain with very high slew rate. In particular, the amplifier circuit achieves very accurate integer gain (1×, 2×, 3×, and so on). Fractional gains can also be obtained with the use of a ratioed capacitor.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: April 14, 2009
    Assignee: National Semiconductor Corporation
    Inventor: Edison Fong