Abstract: An amplifier front-end comprises an input node for receiving a common-mode voltage Vcm, a differential transistor pair having first and second inputs and outputs, a capacitor, a reference voltage Vref, an error correction circuit, and a switching network. The switching network charges the capacitor to Vref; couples the capacitor to the differential pair's first input and couples Vref to the pair's second input such that the voltage at both inputs is ˜Vref; and couples the input node to the capacitor's other terminal such that the voltage at the first input is level-shifted to ˜(Vcm+Vref). The error correction circuit—typically an auto-zero circuit—is coupled to the differential pair's outputs and arranged to reduce charge injection error and kT/C noise components that would otherwise be present in the outputs due to the level shift.

Abstract: A chopper stabilized amplifier has differential inputs, an output, and a low frequency path and a high frequency path from the differential inputs to the output. Chopping occurs, at a chopping frequency, of a differential signal at differential inputs and outputs of an amplifier stage of the low frequency path to thereby produce a chopped differential signal that has a DC offset of the amplifier stage frequency shifted up to the chopping frequency. A continuous time filter embedded between a pair of further amplifier stages of the low frequency path is used to attenuate chopper frequency ripple resulting from the chopping at the chopping frequency. Additionally, a buffer is used to allow feedback through a compensation capacitor for the low frequency path, yet prevent chopper frequency ripple from feeding forward through the compensation capacitor to the output of the amplifier.

Abstract: An embodiment is directed to an instrumentation amplifier. The instrumentation amplifier includes an output stage for generating an output voltage, a low-frequency path coupled with the output stage, and a high-frequency path coupled with the output stage. The high-frequency path dominates the low-frequency path at frequencies above a particular frequency, and the low-frequency path dominates the high-frequency path at frequencies below the particular frequency. The low-frequency path includes an input stage for sensing a differential input and generating an intermediate current based thereon, a feedback stage coupled with the input and output stages, the feedback stage for generating a feedback current based on the output voltage, and an auto-zeroing circuit coupled with the input, feedback, and output stages, the auto-zeroing circuit for generating a nulling current.

Abstract: A method and system for applying multiple voltage droop detection and instruction throttling instances with customized thresholds across semiconductor chips. Environmental parameters are detected for various locations on a chip, and timing margins are determined for each location on the chip. An acceptable voltage droop for each location is determined based on the environmental parameters and the timing margins for the corresponding location. A droop threshold is then determined for each location based on the corresponding acceptable voltage droop determined for the corresponding location.

Abstract: A single-ended operational amplifier includes an output stage, a first transconductance amplifier and a second transconductance amplifier. In an offset cancellation mode, two inputs of the first transconductance amplifier are supplied with a reference voltage to sink two currents from two inputs of the output stage respectively, the output stage generates a third current according to the difference between the two currents to charge a capacitor, and the second transconductance amplifier generates two currents according to the voltage in the capacitor to make currents in the two inputs of the output stage equal to each other, thereby canceling the offset of the single-ended operational amplifier.

Abstract: An amplifier circuit block and a compensation circuit block are provided. The amplifier circuit block includes an analog adder for subtracting an output signal of the compensation circuit block from an input signal and an amplifier circuit operating in a wide band. The compensation circuit block includes an amplifier circuit with a low offset voltage and a low noise in a low frequency region, an analog adder block for subtracting an output signal of the amplifier circuit from an output signal of the amplifier circuit and generating a differential signal thereof, and a feedback circuit block for negatively feeding back the differential signal to the analog adder. The amplifier circuit block can reduce the offset voltage and the low-band noise by the negative feedback of the differential signal, and at the same time, the operation band of the entire amplifier circuit can be decided by the characteristic of the amplifier circuit.

Abstract: Techniques and circuitry are provided for programmably controlling signal offsets in integrated circuitry. In one embodiment, an integrated circuit includes a signal offset cancellation circuit that is programmably selected to control the offset of signals on either one input/output or another input/output of an amplifier circuit. In one embodiment, a logic circuit is used to selectively couple a bank of current sources to one input/output or another input/output of a differential amplifier through a switching circuit. The bank of current sources may employed to control the signal offset on either input/output, or may be decoupled from all of the inputs/outputs when signal offset cancellation is not required.

Abstract: An operational amplifier includes a first differential stage, a second differential stage, a second cascade amplifier stage, an output unit, a first switching control unit and a second switching control unit. When an external signal for stopping operation is input, the first switching control unit shuts off a connection between a non-inverting input terminal and a control electrode of one input transistor at each first and second differential stage, and shuts off a connection between an inverting input terminal and a control electrode of another input transistor at the first and second differential stages, and the second switching control unit connects the negative-side power supply voltage terminal to each control gate of the input transistors at the first and second differential stages and to the substrate gates of the input transistors at the first differential stage.

Abstract: A first gain stage and a second gain stage having different gains are linked in cascade to construct a wide range and high resolution programmable gain amplifier. The second gain stage can be used only for low gain and low power consumption. Furthermore, two pairs of chopper circuits are used to shift flicker noise when the programmable gain amplifier is operated.

Abstract: A preamplifier includes cascade-connected amplifying circuits, and at least one of the cascade-connected amplifying circuits includes a differential switch pair circuit, a comparator and energy storing elements. The differential switch pair circuit has a pair of differential inputs and a pair of differential outputs. The comparator outputs a comparison signal by comparing the differential outputs. The energy storing elements are respectively and selectively coupled to one of the differential outputs based on the comparison signal to adjust potential of the differential outputs. A method for calibrating offsets in a preamplifier is also disclosed herein.

Abstract: An offset canceling circuit includes a differential amplifier circuit configured to output a first output signal in response to a differential input signal; a latch circuit configured to hold a second output signal determined based on the first output signal; and an offset control circuit configured to supply a reference voltage to the differential amplifier circuit to adjust an offset of the differential amplifier circuit. The second output signal is a binary signal, and the latch circuit changes a signal level of the second output signal based on the first output signal. The offset control circuit acquires the second output signal from the latch circuit for every predetermined time and updates a voltage value of the reference voltage based on the signal levels of two of the second output signals which are acquired continuously in time series.

Abstract: Auto-gain correction in a precision amplifier provides continuous calibration of the gain of the two differential input stages relative to each other and thus significantly minimizes the effects of device mismatch and temperature. Auto-gain correction together with auto-zero minimizes the effects of common mode input voltage on the amplifier and eliminates the need for trim associated with the matching of the two differential input stages. Improved gain matching enhances the accuracy of the auto-zero, which further improves the accuracy of auto-gain correction, resulting in a synergy with both operating together. The implementation of the auto-zero using an input pair of series capacitors in conjunction with a common input reference and a feedback pair of series capacitors in conjunction with a common feedback reference provides for decoupling the common mode voltage of the input differential pair or feedback differential pair. Various features may be used in sub-combinations as desired.

Abstract: Provided is a switched-capacitor variable gain amplifier having high voltage gain linearity. According to the above amplifier, a sampling capacitor is shared and used at a sampling phase and an amplification phase, and thus a voltage gain error caused by capacitor mismatch can be reduced. Also, using a unit capacitor array enables circuit design and layout to be simplified. Further, in the amplifier, a voltage gain can be easily controlled to be more or less than 1, as necessary, and power consumption and kT/C noise can be reduced by a feedback factor that is relatively large, so that gain amplification performance can be improved.

Abstract: Disclosed is a digital-to-analog conversion circuit in which first and second serial DACs and an amplifier circuit for driving a data line are provided. In a first data period, the first serial DAC converts a first digital signal received in the first data period to a first signal, the second serial DAC holds a signal obtained by converting a digital signal received in a data period one period before the first data period, and the amplifier circuit amplifies and outputs the signal held in the second serial DAC, to the data line. In a second data period following after the first data period, the second serial DAC converts the second digital signal received in a second data period, the first serial DAC holds the first signal converted in the first data period, and an amplifier circuit amplifies and outputs the first signal held in the first serial DAC, to the data line.

Abstract: An amplifier system receives an input signal and generating therefrom an amplified output signal. The amplifier system is recited as comprising an input stage and an amplifier stage. The input stage is configured to receive the input signal and provide a level-shifted signal that has an average signal level that is shifted in regards a level shift value. The amplifier stage is configured to receive the level-shifted input signal from the input stage and generate therefrom the amplified output signal. The level shift value being selected to minimize a DC offset in the amplified output signal at least when the amplifier system is initially powered on. Since the amplified output signal has a minimal or zero DC offset, the amplifier system avoids generation of undesirable noises when it is initially powered on.

Abstract: A class D amplifier with output DC offset protection is disclosed. The DC offset protection receives a PWM input signals from the outputs and investigates the PWM output signals whether there is a large DC voltage difference is being reflected on the speaker load. If so, shutdown signal SD will be sent by the DC offset protection to the PWM control logic and gate driver, thus, shutting down the output of the class D system and preventing disastrous condition from being develop across the speaker.

Abstract: A switched-capacitor circuit performing two-phase operation with a sampling phase and an amplification phase comprising: an inverter having a common source type input transistor and a load transistor; a first capacitor whose first terminal is connected to a gate of the input transistor serving as an input of the inverter; a first switch which connects between the input (the gate of the input transistor) and the output of the inverter, which turns on during the sampling phase and turns off during the amplification phase; a second switch which connects a second terminal of the first capacitor to an input voltage terminal during the sampling phase, and connects the second terminal of the first capacitor to the output terminal of the inverter during the amplification phase; a second capacitor whose first terminal is connected to a gate of the load transistor of the inverter and whose second terminal is connected to the second terminal of the first capacitor; and a third switch which connects the first terminal of

Abstract: An SC amplifier arrangement and a method for measuring an input voltage are described.

Abstract: Fully differential amplifier circuits are described herein that set the common mode voltage as well as reduce the output offset voltage (offset cancellation). A circuit according to one embodiment includes a first section for generating first and second output signals on first and second outputs from first and second input signals, a first negative feedback loop coupled to the first section, and a second negative feedback loop coupled to the first section. A second section controls the first negative feedback loop for adjusting the first output signal towards a common mode voltage level, and for reducing an offset voltage of the first output signal in different loop bandwidths. A third section controls the second negative feedback loop for adjusting the second output signal towards the common mode voltage level, and for reducing an offset voltage of the second output signal in different loop bandwidths.

Abstract: Provided is a gain amplifier having a switched-capacitor structure capable of minimizing settling time, in which an input capacitor is connected to an input terminal during a first clock sampling an input signal, and thus an output terminal of the amplifier is reset in advance to an estimated output voltage value rather than 0 by the input capacitor. Accordingly, the slight move of the output terminal of the amplifier is sufficient to settle to a desired value in an amplification mode, so that slewing time can be reduced, and as a result, overall settling time and power consumption can be minimized.

Abstract: A first gain stage and a second gain stage having different gains are linked in cascade to construct a wide range and high resolution programmable gain amplifier. The second gain stage can be used only for low gain and low power consumption. Furthermore, two pairs of chopper circuits are used to shift flicker noise when the programmable gain amplifier is operated.

Abstract: A chopper-stabilized amplifier includes a main signal path having first and second chopping circuits at the inputs and outputs of a transconductance amplifier, and an auto-correction feedback loop. The feedback loop includes a transconductance amplifier connected to amplify the chopped output from the main signal path, a third chopping circuit which chops the amplified output, a filter which filters the chopped output to substantially reduce any offset voltage-induced AC component present in the signal being filtered, and a transconductance amplifier which receives the filtered output and produces an output which is coupled back into the main signal path. When properly arranged, the auto-correction feedback loop operates to suppress transconductance amplifier-related offset voltages and offset voltage-induced ripple that might otherwise be present in the amplifier's output.

Abstract: An active circuit includes (a) a first chopper circuit that receives an input signal and a chopping signal of a frequency higher than a base band of the input signal, and that provides a modulated input signal; (b) an amplifier that receives the modulated input signal and that provides an amplified signal resulting from amplifying the modulated input signal; and (c) a second chopper circuit that receives the amplified signal and the chopping signal to provide an output signal. The chopping signal has a frequency that may be dynamically adjusted to accommodate changes in impedance and signal spectrum as a result of the operations of the chopper circuits. The active circuit further includes a low pass filter that receives the output signal and that attenuates components of the output signal above the base band of the input signal. In this manner 1/f noise introduced by the amplifier is eliminated or reduced.

Abstract: In an offset fixing operational amplifier circuit, an operational amplifier circuit includes an input stage containing a first constant current source, a second constant current source, a first differential pair and a second differential pair. A bias circuit supplies a bias voltage to the operational amplifier circuit. An offset fixing circuit controls the input stage in accordance with an input voltage of the operational amplifier circuit.

Abstract: Sampling capacitors are connected respectively to a pair of differential input terminals of an operational amplifier. The sampling capacitors sample input signals. Source terminals and drain terminals of dummy switches are connected respectively to paths connecting the operational amplifier and the sampling capacitors, so that a common-mode voltage of differential input voltages to the operational amplifier is adjusted by gate-channel capacitances.

Abstract: According to one embodiment, a system, apparatus, and method for receiving high-speed signals using a receiver with a transconductance amplifier is presented. The apparatus comprises a transconductance amplifier to receive input voltage derived from an input signal, a clocked current comparator to receive output current from the transconductance amplifier, and a storage element to receive a binary value from the clocked current comparator.

Abstract: This disclosure describes a chopper stabilized instrumentation amplifier. The amplifier is configured to achieve stable measurements at low frequency with very low power consumption. The instrumentation amplifier uses a differential architecture and a mixer amplifier to substantially eliminate noise and offset from an output signal produced by the amplifier. Dynamic limitations, i.e., glitching, that result from chopper stabilization at low power are substantially eliminated through a combination of chopping at low impedance nodes within the mixer amplifier and feedback. The signal path of the amplifier operates as a continuous time system, providing minimal aliasing of noise or external signals entering the signal pathway at the chop frequency or its harmonics. The amplifier can be used in a low power system, such as an implantable medical device, to provide a stable, low-noise output signal.

Abstract: In one embodiment of the present invention, an operational amplifier circuit, a switching element is closed and a switching element is opened. A latch circuit DL latches an output voltage of an operational amplifier and supplies a Q output corresponding to the output voltage. A control circuit supplies an offset adjustment signal to an offset adjustment input terminal OR of the operational amplifier, thereby adjusting an offset of the output voltage. The latch circuit DL latches again the output voltage thus adjusted and minutely adjusts the offset adjustment signal so as to adjust the remaining offset. Weighting is carried out in accordance with how many times latching has been carried out, and the offset of the output voltage of the operational amplifier is quantized, thereby obtaining a binary logical signal and storing the signal in the control circuit.

Abstract: A method and an apparatus are described for an offset correction in a high gain amplifier. An embodiment of an amplifier circuit includes an amplifier to convert a current signal into a voltage signal, where the amplifier generates an offset voltage in the voltage signal. The amplifier circuit also includes a sampling component coupled with the amplifier, with the sampling component subtracting a first sample of the voltage signal from a second sample of the voltage signal to produce a difference value. The amplifier circuit further includes a gain component coupled with the sampling component to amplify the difference between the first sample and the second sample.

Abstract: An amplifier front-end comprises an input node for receiving a common-mode voltage Vcm, a differential transistor pair having first and second inputs and outputs, a capacitor, a reference voltage Vref, an error correction circuit, and a switching network. The switching network charges the capacitor to Vref; couples the capacitor to the differential pair's first input and couples Vref to the pair's second input such that the voltage at both inputs is ˜Vref; and couples the input node to the capacitor's other terminal such that the voltage at the first input is level-shifted to ˜(Vcm+Vref). The error correction circuit—typically an auto-zero circuit—is coupled to the differential pair's outputs and arranged to reduce charge injection error and kT/C noise components that would otherwise be present in the outputs due to the level shift.

Abstract: An embodiment may be described as a switched capacitor analog equalizer circuit with offset voltage cancellation, where an embodiment comprises an amplifier in which a feedback path from its output port to one of its input ports is provided during a reset phase, and where the amplifier's input port connected to the feedback path is also connected to one terminal of an offset-correction capacitor and one terminal of a sampling capacitor. The other terminal of the offset-correction capacitor is connected to a switch and the other terminal of the sampling capacitor is connected to an input port to receive a signal. During the reset phase, the switch is open, and during a sampling phase, the switch is closed so that the offset-correction capacitor and the sampling capacitor are connected in parallel. Other embodiments are described and claimed.

Abstract: A reference generation circuit provided according to an aspect of the present invention generates a reference potential at different levels in the hold phase of different cycles in an input path of a switched capacitor differential amplifier. In an embodiment, for each hold phase, the reference generator provides the reference potential with a magnitude that tracks the magnitude of the input signal applied in a corresponding (preceding) sample phase. In case of a single-ended output, the reference potential generated for each hold phase equals the magnitude of one of the inputs on the differential input path. As a result, the common mode voltage at the input terminals of an operational amplifier contained in the switched capacitor differential amplifier is maintained at a desired level.

Abstract: A programmable offset amplifier includes first (M1) and second (M2) input transistors having differentially connected sources and gates coupled to first (Vin+) and second (Vin?) input voltages. A tail current (Itail1) is shared between the first and second input transistors. First (M3) and second (M4) load devices are coupled between a reference voltage and drains of the first and second input transistors, respectively. An output stage (13) has a first input (+) coupled to the drain of the second input transistor and a second input (?) coupled to the drain of the first input transistor. Programmable voltage changes are produced on input elements of programmable input offset circuitry to cause changes in offset voltages associated with electrodes of the input transistors which are reflected back to the amplifier input to provide a large programmable input-referred offset voltage.

Abstract: Methods and systems for implementing an analog switch controller to improve linearity of analog switches are described.

Abstract: A receiver stage has an operational amplifier, a feedback resistor coupled between an output of the operational amplifier and an input of the operational amplifier, and a DC offset calibration circuit. The DC offset calibration circuit includes a plurality of resistors and a plurality of switches. Each resistor has a first end coupled to a supply voltage. First ends of each of the switches are coupled to second ends of each of the resistors, respectively, and second ends of the switches are coupled to the input of the operational amplifier.

Abstract: A bootstrapped class AB CMOS output circuit and method for generating a class AB output are disclosed. The bootstrapped class AB CMOS output circuit has a voltage offset circuit coupled to an NMOS transistor and a PMOS transistor. The voltage offset circuit has a capacitor bootstrapped between the NMOS transistor and the PMOS transistor to establish a voltage offset between the NMOS transistor and the PMOS transistor to effect a class AB output. The method for generating a class AB output in a semiconductor device having a capacitor coupled to the NMOS transistor and the PMOS transistor includes providing a voltage offset across the capacitor to effect a class AB output.

Abstract: Apparatuses and methods for providing offset compensation include a primary amplifier which includes a first output, a second output, a first load input, and a second load input, a first feedback loop connected to the primary amplifier and which includes a first switch located between the first output of the primary amplifier and the first load input, and a first sampling capacitor coupled to the first switch between the first switch and the first load input and a second feedback loop connected to the primary amplifier and which includes a second switch located between the second output of the primary amplifier and the second load input, and a second sampling capacitor coupled to the second switch between the second switch and the second load input.

Abstract: A linear programmable switch-capacitance gain amplifier (PGA) is described. The PGA divides the dB-gain curve into several parts by the concept of piece-wise linearity, and then simultaneously executes the dB-linear gain adjustment of MSB and the LSB at the same gain stage. Present invention achieves the PGA dB-linearity by setting up every capacitance of the sampling capacitor array and the holding capacitor array, then arranging the sampling capacitor array and the holding capacitor array by coordinating the switching of the capacitor switches.

Abstract: A switch-capacitor (“SC”) amplifier includes a two-stage operational amplifier (“OP-AMP”), an input SC network, and a feedback SC network. The two-stage OP-AMP includes a first OP-AMP stage having an output coupled to an input of a second OP-AMP stage. The input SC network is coupled to an input of the first OP-AMP stage. The feedback SC network is configured to selectively couple the output of the first OP-AMP stage to the input of the first OP-AMP stage during a first phase of operation of the SC amplifier and to couple an output of the second OP-AMP stage to the input of the first OP-AMP stage during a second phase of operation of the SC amplifier.

Abstract: A limiting amplifier with an input stage with dc offset cancellation, identical gain stages, an output buffer and a feedback filter. The input stage receives a differential input signal and outputs a first intermediate differential signal. The gain stages are cascaded to amplify the first intermediate differential signal and generate a second intermediate differential signal, amplified by the output buffer to produce an output signal. The feedback filter provides a dc offset voltage of the output signal to the input stage for the dc offset cancellation. The input stage comprises a resistor network coupled between a pair of input nodes and a power line and comprising a common resistor, a pair of load resistors and a shunt resistor. The load resistors share a common terminal connected to the common resistor that is connected to the power line. The shunt resistor has two terminals respectively connected to the load resistors.

Abstract: An integrated circuit including a circuit for calibration and offset compensation of an amplifier method is disclosed. In one embodiment, the method includes providing a reference input signal to the input of an amplifier, coupling the output signal of the amplifier to a comparator circuit as a first input signal, providing a target signal to the comparator circuit as a second input signal, and increasing or decreasing a control signal provided to amplifier VGA corresponding to the output of the comparator circuit by one adjustment process of small process size.

Abstract: Disclosed is a differential amplifier including: first and second transistors each having a first gate, a second gate, a source, and a drain open to a drain side, the first gate and the second gate being controlled independently, a differential input being supplied to between the first gates of the first and second transistors, and the sources of the first and second transistors being connected in common to a first reference potential; first and second load circuits each connected to each of drain sides of the first and second transistors; a detection circuit detecting a common-mode voltage between ones of drain sides of the first and second transistors; and a comparison and amplification circuit amplifying the common-mode voltage in comparison with a second reference potential and supplying an output signal thereof to both of the second gates of the first and second transistors.

Abstract: A chopper stabilized amplifier has differential inputs, an output, and a low frequency path and a high frequency path from the differential inputs to the output. Chopping occurs, at a chopping frequency, of a differential signal at differential inputs and outputs of an amplifier stage of the low frequency path to thereby produce a chopped differential signal that has a DC offset of the amplifier stage frequency shifted up to the chopping frequency. A continuous time filter embedded between a pair of further amplifier stages of the low frequency path is used to attenuate chopper frequency ripple resulting from the chopping at the chopping frequency. Additionally, a buffer is used to allow feedback through a compensation capacitor for the low frequency path, yet prevent chopper frequency ripple from feeding forward through the compensation capacitor to the output of the amplifier.

Abstract: A system and method for compensation of offset voltage in a digital differential input buffer driven by a terminated transmission line. Offset compensation currents are injected at the output of the first stage of the input buffer, which has a higher impedance than the terminated transmission line at the input of the buffer. The compensation current is determined by a network of MOS transistors, which saves die space compared to resistors. A pair of voltage multiplexers provides for compensation currents to correct offsets of either polarity. Offset correction currents are determined anew each time the system is powered up, compensating for component aging. The offset correction can also be performed while the input buffer is operating, during periods when the input is quiescent, and/or by adjusting the offset correction according to the duty cycle of the detected input.

Abstract: A ratio-independent switched capacitor amplifier includes a first sampling circuit configured to sample a first input voltage as a first sampling voltage and to double a level of the first sampling voltage during an interval in which the first input voltage is cut off; a second sampling circuit configured to sample a second input voltage as a second sampling voltage and to double a level of the second sampling voltage during an interval in which the second input voltage is cut off; and a differential amplifier circuit configured to output a difference between the first sampling voltage and the second sampling voltage.

Abstract: A preamplifier includes cascade-connected amplifying circuits, and at least one of the cascade-connected amplifying circuits includes a differential switch pair circuit, a comparator and current sources. The differential switch pair circuit has a pair of differential inputs and a pair of differential outputs. The comparator outputs a comparison signal by comparing the differential outputs. The current sources are respectively and selectively coupled to one of the differential outputs based on the comparison signal to adjust voltages of the differential outputs. A method for calibrating offset voltages in a preamplifier is also disclosed herein.

Abstract: A current generator, including a chopper stabilization operational amplifier, a transistor, and an impedance unit is provided. The chopper stabilization operational amplifier includes a first input terminal, a second input terminal, and an output terminal. The transistor includes a gate coupled to the output terminal of the chopper stabilization operational amplifier, a first source/drain coupled to the first input terminal of the chopper stabilization operational amplifier, and a second source/drain serving as a current output terminal of the current generator. The impedance unit includes a first terminal coupled to the first source/drain of the transistor, and a second terminal coupled to a first voltage.

Abstract: In an offset cancellation circuit according to the present invention, a first capacitance is connected to a gate of a first transistor of a first active load, and a second capacitance is connected to a gate of a second transistor of the first active load. A switch sets a first time period and a second time period in connection states between the first and second transistors and the first and second capacitances. The connection states between the first and second transistors and the first and second capacitances are set so that a gate voltage of the first transistor is supplied to the first capacitance, and a gate voltage of the second transistor is supplied to the second capacitance during the first time period; and so that the first and second capacitances can retain charges, and the second time period becomes an output time period of the operational amplifier during the second time period.

Abstract: DC offsets in high-gain amplifiers should be corrected to avoid the signal distortion that would result from amplifier saturation. A predominantly digital technique is described in which a digital algorithm observes patterns in the sign of the amplifier output and drives a digital-to-analog converter (DAC), which reduces the amplifier's offset.

Abstract: This disclosure describes a chopper stabilized instrumentation amplifier. The amplifier is configured to achieve stable measurements at low frequency with very low power consumption. The instrumentation amplifier uses a differential architecture and a mixer amplifier to substantially eliminate noise and offset from an output signal produced by the amplifier. Dynamic limitations, i.e., glitching, that result from chopper stabilization at low power are substantially eliminated through a combination of chopping at low impedance nodes within the mixer amplifier and feedback. The signal path of the amplifier operates as a continuous time system, providing minimal aliasing of noise or external signals entering the signal pathway at the chop frequency or its harmonics. The amplifier can be used in a low power system, such as an implantable medical device, to provide a stable, low-noise output signal.