Abstract: An offset voltage calibration method is disclosed, which is utilized for calibrating an offset voltage of an electronic device during a calibration period. The offset voltage calibration method includes generating a control signal according to an output signal of the electronic device, counting a count value and generating an offset indication signal according to the control signal, stopping counting and generating a final count value according to a compensation value after the output signal changes state, generating a calibration signal according to the count value or the final count value, and calibrating the offset voltage according to the offset indication signal and the calibration signal.

Abstract: A high dynamic range amplifier circuit for amplifying pixel signals of an imager device is disclosed. The amplifier circuit uses a read-out scheme based on a charge recycling approach, where a pixel signal is first amplified with a low gain during a first amplification phase T1, and then the amplifier output is immediately recycled and the pixel signal amplified with a higher gain during a second amplification phase T2.

Abstract: A switched capacitor system with output glitch reduction step charges the switched capacitor by switching it to a first voltage level in a first phase, to an intermediate voltage level of a pre-charge node in a pre-charge phase and to the voltage level of the output node of the amplifier stage in a settling phase; the pre-charge node can be implemented at the input of the amplifier stage, the output of a preceding stage or at any other pre-existing suitable node in the amplifier system.

Abstract: It was difficult to design an operational amplifier which can cancel an offset to drive a liquid crystal display. An operational amplifier includes: a first differential pair having a first transistor and a second transistor of a first conduction type; a second differential pair having a third transistor and a fourth transistor of a second conduction type; a first floating current source; a second floating current source; and an output stage having a fifth transistor and a sixth transistor, in which, when an input signal is applied to the first and third transistor, an electric current which flows into the fifth transistor and the sixth transistor is set by the first floating current source, and when the input signal is applied to the second and fourth transistor, an electric current which flows into the fifth transistor and the sixth transistor is set by the second floating current source.

Abstract: A direct-current-offset correction device includes a digital-to-analog converter that converts a digital signal into an analog signal, a modulator that modulates the analog signal to generate a modulated signal, a direct-current-offset correction value calculation unit that calculates a direct-current-offset correction value as a reverse characteristic component of a carrier leak occurring in the modulated signal based on a demodulated signal which is demodulated by feeding back the modulated signal, a direct-current-offset correction unit that corrects a direct-current-offset on the digital signal based on the direct-current-offset correction value, a correction value detection unit that detects whether or not the direct-current-offset correction value is zero or a neighboring value of zero, and an offset generation unit that superimposes a direct-current-offset component on the analog signal based on a detection result of the correction value detection unit.

Abstract: A commutating auto zero amplifier system, comprises a first amplifier (A1), a second amplifier (A2) and a switching arrangement which defines a two phase operation, with one amplifier in an output mode providing the output and the other amplifier in a zeroing mode during each phase. A capacitor arrangement (Cof1. Cot1) stores offset voltages, a buffer amplifier (B) couples the output from the amplifier in the output mode to an input of the amplifier in the zeroing mode. This eliminates voltage swings at the output of an amplifier as it switches between modes of operation.

Abstract: A limiting amplifier with an input stage with dc offset cancellation, identical gain stages, an output buffer and a feedback filter. The input stage receives a differential input signal and outputs a first intermediate differential signal. The gain stages are cascaded to amplify the first intermediate differential signal and generate a second intermediate differential signal, amplified by the output buffer to produce an output signal. The feedback filter provides a dc offset voltage of the output signal to the input stage for the dc offset cancellation. The input stage comprises a resistor network coupled between a pair of input nodes and a power line and comprising a common resistor, a pair of load resistors and a shunt resistor. The load resistors share a common terminal connected to the common resistor that is connected to the power line. The shunt resistor has two terminals respectively connected to the load resistors.

Abstract: Techniques and circuitry are provided for programmably controlling signal offsets in integrated circuitry. In one embodiment, an integrated circuit includes a signal offset cancellation circuit that is programmably selected to control the offset of signals on either one input/output or another input/output of an amplifier circuit. In one embodiment, a logic circuit is used to selectively couple a bank of current sources to one input/output or another input/output of a differential amplifier through a switching circuit. The bank of current sources may employed to control the signal offset on either input/output, or may be decoupled from all of the inputs/outputs when signal offset cancellation is not required.

Abstract: An amplifying circuit has an offset calibration mode and a normal mode. The amplifying circuit includes an amplifier having a non-inverting input and an inverting input for receiving, during the normal mode, a first input signal and a second input signal and an output for providing a high speed output signal, wherein the first input signal is a reference voltage or a high speed signal and the second input signal is a high speed signal. The amplifying circuit further includes a first transmission gate and a second transmission gate coupled in series between the non-inverting input and an inverting input that are enabled during the offset calibration mode. A benefit of this approach is that capacitance between the inverting and non-inverting inputs is reduced by the first and second transmission gates being in series. There is further benefit in reducing this capacitance by having each transmission gate receive an enable signal from a different source.

Abstract: A differential gain stage includes a plurality of programmable passive circuit component arrays operable to set a gain of the gain stage. The gain stage also includes an active switch gate control circuit and a passive switch gate control circuit. The active switch gate control circuit controls a gate voltage applied to transistor switch components of each programmable passive circuit component array as a function of the level of common mode disturbance input to the differential gain stage for common mode frequencies below a particular frequency threshold. The passive switch gate control circuit controls the gate voltage applied to the transistor switch components as a function of the level of common mode disturbance for common mode frequencies above the frequency threshold. The differential gain stage can for part of a receiver such as an xDSL receiver.

Abstract: A differential amplifier circuit includes an offset adjuster circuit for varying the active load to adjust the offset caused by the differential pair. The differential amplifier circuit includes fine adjustment cell sections including a plurality of transistors having the substantially same size, and shift cell sections including transistors, whose transistor size is larger than the transistors of the fine adjustment cell sections.

Abstract: Chopper stabilized operational amplifiers are in common use. One drawback of these amplifiers, however, is that there is an inherent tone present at the chopper frequency. Conventional circuits have attempted to reduce the effects of this tone by using various filtering schemes, such as a notch filter. Here, however, a track-and-hold circuit is used in conjunction with matched amplifiers to compensate for this tone.

Abstract: An operational amplifier capable of offset cancel in a shorter period, as well as a line driver capable of shortening one horizontal period and a liquid crystal display device are provided. In the operational amplifier of the invention, a time necessary for feed back control can be shortened than usual by a constitution that an output voltage VO in one horizontal period H1 which is one horizontal period before is defined as a reference voltage in an offset cancel preparatory period HC2, thereby changing the output voltage VO(2) only by the offset voltage VO(2) by the feed back control. In the line driver of the invention, the operational amplifier not used for the output of display data D1 to D6 conducts offset cancel operation and it is successively shifted on every one horizontal period. Since it is no more necessary to incorporate the offset cancel preparatory period in the output period, one horizontal period can be shortened further.

Abstract: A switched-capacitor amplifier arrangement and a method to amplify a signal are presented. A forward path has at least one switched capacitor (10) controlled by a clock signal, thus providing an amplification phase (1) of the forward path and an additional clock phase (2). A damping means (22) is connected to the forward path, the damping means being designed for attenuation of the signal peak at the beginning (2p) of the amplification phase. This avoids an undesired feed forward effect at the beginning of the amplification phase of an SC circuit.

Abstract: A transconductor circuit, particularly according to the multi-tanh principle, having a first input node and a second input node, a first differential amplifier coupled to the first and second input nodes, and having a first offset voltage, and a second differential amplifier coupled to the first and second input nodes, and having a second offset voltage different from the first offset voltage. A first resistance circuit is coupled between the first differential amplifier and at least one current source, and a second resistance circuit is coupled between the second differential amplifier and the at least one current source. Varying of the current sources enables control of the transconductance without degrading linearity.

Abstract: Variable gain commutating amplifier apparatus and methods for use in a polar modulator are described. The apparatus may include two or more commutating amplifier stages configured to be switched to an output load based on a desired amplitude and/or transmit power level. The amplifier stages may include cross-coupled differential pairs to cancel RF carrier feedthrough. An additional R-2R ladder circuit may be provided to further extend the dynamic range by reducing the output power at the lowest output stages.

Abstract: A differential amplifier circuit, an operational amplifier circuit, and a light-receiving amplifier circuit using the same are provided, by which the influence of an on resistance of an analog switch is reduced during the switching of gain resistances. An NPN transistor Q2 having an emitted connected in common is connected to an NPN transistor Q1 of a differential amplifier circuit including the NPN transistors Q1 and Q3, PNP transistors Q4 and Q5, and a constant-current source I1, and analog switches ASW-1c and ASW-2c are inserted and connected to the collectors of the NPN transistors Q1 and Q2 and connected to the base and collector of the PNP transistor Q4 and the base of the PNP transistor Q5. Further, analog switches ASW-1b and ASW-2b are connected to the bases of the NPN transistors Q1 and Q2, respectively.

Abstract: A sample-and-hold amplifier is provided. The sample-and-hold amplifier comprises a sample-and-hold circuit and a buffer circuit. The sample-and-hold circuit receives an input signal and transmits the input signal to a first node according to a control signal. The buffer circuit is coupled between a supply voltage source and a ground and controlled by the first node to provide an output signal at an output node. The buffer circuit comprises a native MOS transistor coupled to the output node.

Abstract: Provided is a switched capacitor circuit which prevents leakage current by equalizing voltages at nodes where leakage current tends to flow in a sampling mode, and prevents errors in an output signal by minimizing voltage drop caused by leakage current in an integrating mode.

Abstract: This disclosure describes a chopper stabilized instrumentation amplifier. The amplifier is configured to achieve stable measurements at low frequency with very low power consumption. The instrumentation amplifier uses a differential architecture and a mixer amplifier to substantially eliminate noise and offset from an output signal produced by the amplifier. Dynamic limitations, i.e., glitching, that result from chopper stabilization at low power are substantially eliminated through a combination of chopping at low impedance nodes within the mixer amplifier and feedback. The signal path of the amplifier operates as a continuous time system, providing minimal aliasing of noise or external signals entering the signal pathway at the chop frequency or its harmonics. The amplifier can be used in a low power system, such as an implantable medical device, to provide a stable, low-noise output signal.

Abstract: An amplifier with accurate input offset voltage is described. In one design, the amplifier includes first and second unbalanced differential pairs. The first unbalanced differential pair receives a differential input signal and provides a first differential current signal. The second unbalanced differential pair receives a differential reference signal and provides a second differential current signal, which is subtracted from the first differential current signal to obtain a differential output signal. The second differential current signal tracks an error current in the first differential current signal so that the differential output signal is zero when the differential input signal is equal to a target input offset voltage for the amplifier. For each unbalanced differential pair, one transistor is M times the size of the other transistor, with M being selected to obtain the target input offset voltage.

Abstract: Low-noise, low-power, low drift offset correction in operational and instrumentation amplifiers and amplifiers using the same are disclosed. The amplifiers disclosed use different combinations of chopping and auto-zero techniques. Also disclosed are amplifiers using on-off switches to affect the chopping and auto-zeroing, with unique circuits for driving the switches on the differential input to provide boot-strapped switch controls. Other features are disclosed.

Abstract: An apparatus includes a plurality of amplifier stages configured to receive an input voltage and generate an amplified output current. Each amplifier stage includes a transconductance stage configured to receive the input voltage and generate a first intermediate output current. Each amplifier stage also includes an auto-zeroing loop configured to generate a second intermediate output current that at least partially corrects for an offset of the transconductance stage, where the auto-zeroing loop operates at a first frequency. Each amplifier stage further includes chopping circuitry configured to reverse a polarity of the input voltage and a polarity of the amplified output current at a second frequency, where the second frequency is less than the first frequency. Each amplifier stage is configured to operate in auto-zeroing and amplification phases. At least one amplifier stage operates in the auto-zeroing phase when at least one other amplifier stage operates in the amplification phase.

Abstract: A differential amplifier (1D) includes circuitry (5,R1,R2,52) coupling a common mode component of an input voltage (Vin+?Vin?) to a maximum voltage selector circuit (53) that produces an internal voltage (VRAIL-TOP) equal to the larger of a first supply voltage (VREG) and the common mode component. An input amplifier circuit (46) of the differential amplifier is powered by the internal voltage. The input voltage (Vin+?Vin?) is coupled to inputs (41A,B) of the input amplifier circuit (46). Outputs (64A,B) of the input amplifier circuit (46) are amplified by an output amplifier (50).

Abstract: Amplifiers with power-on trim and methods using an amplifier system having an amplifier system input and an amplifier system output, an amplifier, a comparator, a successive approximation register having an input coupled to an output of the comparator, a first switch for switching an input of the amplifier from the amplifier system input to shorting the amplifier input, a second switch for switching an output of the amplifier from the amplifier system output to an input of the comparator, an output of the successive approximation register being coupled to an N bit digital to analog (D/A) converter, the D/A converter being a non-binary converter using a radix of less than 2 for at least the most significant bits, and an output of the D/A converter being coupled to the amplifier to control the input offset of the amplifier. Novel embodiments for the amplifier, comparator and D/A converter are disclosed.

Abstract: In a signal transmission system where an influence of the circuit characteristic variation of an input circuit on signal receiving operation cannot be ignored, there is provided a method of realizing a low-offset input circuit which is capable of conducting high-speed operation and always continuing signal receiving operation without increasing the number of terminals of a semiconductor integrated circuit and without the necessity of providing additional signal observing means and variation adjustment amount calculating means to the external of the semiconductor integrated circuit.

Abstract: An integrated buffer device for a switched capacitance circuit having a buffer with an output for an output voltage dependent upon an input voltage that can be supplied by a source to the buffer device; a capacitive switching component that can be switched between a first and second condition and connected, respectively, to the source and to the buffer to transfer the input voltage onto the output; the capacitive switching component provided with a terminal having an associated stray capacitance; a charging and discharging device configured to pre-charge the stray capacitance at a reference voltage before taking up the second condition and to pre-discharge the stray capacitance before taking up the first condition.

Abstract: A reference generation circuit provided according to an aspect of the present invention generates a reference potential at different levels in the hold phase of different cycles in an input path of a switched capacitor differential amplifier. In an embodiment, for each hold phase, the reference generator provides the reference potential with a magnitude that tracks the magnitude of the input signal applied in a corresponding (preceding) sample phase. In case of a single-ended output, the reference potential generated for each hold phase equals the magnitude of one of the inputs on the differential input path. As a result, the common mode voltage at the input terminals of an operational amplifier contained in the switched capacitor differential amplifier is maintained at a desired level.

Abstract: A low power, low noise amplifier system includes at least one amplifier having first and second differential input terminals, first and second differential output terminals and providing a differential output; first and second input capacitors interconnected with the first and second differential amplifier input terminals; first and second feedback circuits containing first and second feedback capacitors, respectively, interconnected with the amplifier differential input and output terminals; an input chopper switch circuit for receiving a low frequency differential input and selectively, alternately swapping those low frequency differential inputs through the input capacitors to the differential input terminals of the amplifier; an output chopper switch for receiving and selectively, alternately swapping the amplifier differential outputs synchronously with the input chopper switch circuit; and a low pass filter responsive to the swapped differential outputs for providing a low noise, low power amplification

Abstract: A switched-capacitor circuit includes a plurality of cascaded differential-input, single-ended-output amplifiers. A negative feedback path, from an output terminal of a last of the cascaded amplifiers to an input terminal of a first of the cascaded amplifiers, is configured to exclude, and not be shorted out by, any switches.

Abstract: In an offset cancellation circuit according to the present invention, a first capacitance is connected to a gate of a first transistor of a first active load, and a second capacitance is connected to a gate of a second transistor of the first active load. A switch sets a first time period and a second time period in connection states between the first and second transistors and the first and second capacitances. The connection states between the first and second transistors and the first and second capacitances are set so that a gate voltage of the first transistor is supplied to the first capacitance, and a gate voltage of the second transistor is supplied to the second capacitance during the first time period; and so that the first and second capacitances can retain charges, and the second time period becomes an output time period of the operational amplifier during the second time period.

Abstract: A bootstrapped class AB CMOS output circuit and method for generating a class AB output are disclosed. The bootstrapped class AB CMOS output circuit has a voltage offset circuit coupled to an NMOS transistor and a PMOS transistor. The voltage offset circuit has a capacitor bootstrapped between the NMOS transistor and the PMOS transistor to establish a voltage offset between the NMOS transistor and the PMOS transistor to effect a class AB output. The method for generating a class AB output in a semiconductor device having a capacitor coupled to the NMOS transistor and the PMOS transistor includes providing a voltage offset across the capacitor to effect a class AB output.

Abstract: Amplifier circuits and methods are implemented using a variety of different embodiments. According to one such embodiment, a method is implemented using a field-effect transistor (FET) having a gate node, a source node and a drain node. A first circuit state is implemented in which the gate node, the source node and the drain node are connected to inputs that generate a stored charge at the gate node, the amount of stored charge at the gate node being responsive to a first voltage level. A second circuit state is implemented in which the drain node is connected to a voltage source, the source node is connected to a load, and while charge at the gate node is preserved, current between the drain node to the source node drives a voltage level of the load to a proportionally amplified version of the first voltage level.

Abstract: An amplifier circuit is disclosed that includes a first input terminal; a second input terminal; a first differential amplifier circuit that samples signals input to the first and second input terminals and outputs signals obtained by applying a gain to the sampled input signals having different voltages; and a second differential amplifier circuit that supplies first and second reference voltages referred to when a sampling operation is performed in the first differential amplifier circuit to the first and second input terminals, respectively. A potential difference between the first and second reference voltages is equal to an offset voltage of the first differential amplifier circuit.

Abstract: A new offset canceling circuit for a differential circuit is disclosed whose input offset voltage may be cancelled independent of the variation of the input level, accordingly, enables the cut-off frequency of the canceling circuit unchanged. The offset canceller of the invention provides a buffer amplifier and a filter. The filter includes a capacitance multiplier including an operational amplifier (Op-Amp) operating in the inverting mode and a capacitor connected between the input and output of the Op-Amp. The Op-Amp operating in the inverting mode whose closed loop gain is solely determined by resistors, and the capacitance of the capacitor is multiplied by the closed loop gain of the Op-Amp by the Miller effect.

Abstract: A chopper-stabilized amplifier includes a main signal path having first and second chopping circuits at the inputs and outputs of a transconductance amplifier, and an auto-correction feedback loop. The feedback loop includes a transconductance amplifier connected to amplify the chopped output from the main signal path, a third chopping circuit which chops the amplified output, a filter which filters the chopped output to substantially reduce any offset voltage-induced AC component present in the signal being filtered, and a transconductance amplifier which receives the filtered output and produces an output which is coupled back into the main signal path. When properly arranged, the auto-correction feedback loop operates to suppress transconductance amplifier-related offset voltages and offset voltage-induced ripple that might otherwise be present in the amplifier's output.

Abstract: A circuit with an input acquisition loop and an output acquisition loop is used to compensate for the input offset voltage and bias current errors of an operational amplifier.

Abstract: An operational amplifier including: a differential pair of transistors coupled to a pair of input signals; and a pair of floating-gate transistors coupled to the differential pair of transistors, wherein the pair of floating-gate transistors are operable for reducing an offset voltage of the operational amplifier.

Abstract: A DC current reduction circuit of the present invention that reduces a DC component in an output current of a current output element in which an AC current and a DC current are superimposed includes a low-pass filter for extracting a current component of a frequency lower than a cutoff frequency from the output current and a reduction unit that reduces the extracted current component from the output current. The low-pass filter has a frequency changing unit that changes the cutoff frequency from higher to lower as a continuous function over time.

Abstract: An amplifier having DC offset compensation includes at least one input node and a pair of differential output nodes, a biasing circuit coupled to the input node; and a plurality of current sources.

Abstract: A chopping transconductor includes an transconductor input stage coupled with input signals of the chopping transconductor; a chopping switch coupled with an output of the transconductor input stage, the chopping switch having a switch output; and a cascode transistor, wherein the switch output is coupled to an output of the chopping transconductor through the cascode transistor. The chopping transconductor may be used in an analog-to-digital converter to isolate chopping switches from junctions with quantization noise.

Abstract: Method and device for adjusting or setting an electronic device (1) exhibiting at least one input for an external input signal and at least one output signal output, the value or the state of the output signal being a function of the values or of the state of the input signal. A memory circuit (9) for the value of an adjustment signal is linked to an adjustment input of the electronic device. A circuit (11) increments/decrements said adjustment value stored in said memory circuit. A switching circuit (12) switches said input of the electronic device to a predetermined state and links said output of the electronic device to said memory circuit via said incrementing/decrementing circuit. Said incrementing/decrementing circuit (11) is adapted for adjusting the value of said adjustment signal so that, when said input is switched to said predetermined state, the value or the state of said output signal tend to or attain a predetermined value or a predetermined state.

Abstract: A receiver stage has an operational amplifier, a feedback resistor coupled between an output of the operational amplifier and an input of the operational amplifier, and a DC offset calibration circuit. The DC offset calibration circuit includes a plurality of resistors and a plurality of switches. Each resistor has a first end coupled to a supply voltage. First ends of each of the switches are coupled to second ends of each of the resistors, respectively, and second ends of the switches are coupled to the input of the operational amplifier.

Abstract: The invention relates to analog integrated electronic circuits using differential pairs. The proposal is for a method of automatic correction of offset voltage. The inputs (V1, V2) of the differential circuit are short circuited during a calibration phase distinct from the normal usage phase. A capacitor is charged through the difference of the output currents of the branches of the differential pair in this phase. The voltage at the terminals of the capacitor is compared with at least one threshold. During the normal usage phase following the calibration phase, the result of the comparison is kept in memory. In the normal usage phase, a correction is applied depending on the result kept in memory to a current source of a follower stage upstream of the differential pair.

Abstract: A differential amplifier (10-1,2) includes an input stage (7) including first (M1) and second (M2) input transistors and first (4A) and second (4B) load devices. Sources of the first and second input transistors are connected together. Drains of the first and second input transistors are coupled by first (12) and second (13) conductors to the first and second load devices, respectively. Common mode feedback circuitry (6A) including first (M3), second (M4), and third (M5) transistors is combined with offset correction circuitry (8) including the second transistor and the third transistor. Sources of the first, second, and third transistors are coupled to a tail current source (11). Drains of the second and third transistors are coupled to the first and second conductors, respectively. A common mode voltage (VOCM) is applied to a gate of the first transistor. Offset trim voltages are applied to gates of the second and third transistors.

Abstract: An operational amplifier (1B) amplifies an input signal (Vin) to produce an output signal (Vout), and includes a 3-stage amplifier (1C) including a first amplifier stage (2) receiving the input signal, a second amplifier stage (3) driven by the first amplifier stage (2), and a third amplifier stage (4) driven by the second amplifier stage to produce the output signal. A slew detection current (Idetect) is generated when the input signal (Vin) exceeds a certain magnitude, and is converted to a control signal (41) that operates a switch (MN0) to short-circuit output conductors of the first amplifier stage to prevent signal charge from building up on capacitances associated with the output of the first amplifier stage during slewing. The three stage amplifier can be a chopper-stabilized, notch-filtered amplifier.

Abstract: A first to a fourth sampling switch (1a to 1d), a first to a fourth sampling capacitance (4 to 7), and a first and a second charge redistribution switch (2a, 2b) are provided on the input side of a differential amplifier (8). A first and a second reset switch (3a, 3b) are provided between inputs and outputs of the differential amplifier (8). A positive-polarity input signal voltage (Vinp), a negative-polarity comparison reference voltage (Vrefn), a positive-polarity comparison reference voltage (Vrefp), and a negative-polarity input signal voltage (Vinn) are applied via the first to fourth sampling switches (1a to 1d) to one ends of the first to fourth sampling capacitances (4 to 7), respectively. During a reset period, the reset of the differential amplifier (8) is released after sampling of the voltages. During a comparison period, the first and second charge redistribution switches (2a, 2b) are caused to be in a conduction state.

Abstract: A pseudo-differential switched-capacitor circuit using integrator-based common-mode stabilization technique is disclosed. A pseudo-differential switched-capacitor circuit with the differential floating sampling (DFS) technique has a common-mode gain value of one (1). An integrator is electrically coupled to the differential positive/negative outputs of the DFS circuit, and the integrator feeds back integrator output to the DFS circuit by detecting common-mode voltage disturbance at the differential positive output (Vout+) and negative output (Vout?), thereby stabilizing output common-mode level of the differential positive output (Vout+) and negative output (Vout?) at a desirable level.

Abstract: Disclosed are a sensor interface device and an amplifier used in a sensor system. The sensor interface device in one implementation has a first chopper configured to shift input signals of the sensor system from a baseband frequency to a first frequency, an instrumentation amplifier configured to amplify the shifted signals, a bandpass Delta-Sigma modulator configured to digitize the amplified signals, and a second chopper configured to shift the digitized signals from the a first frequency back to the baseband frequency. The instrumentation amplifier removes the DC offset generated from the first chopper and therefore all sources of DC offset are eliminated in this interface device without bandwidth limitation.

Abstract: Techniques and circuitry are provided for programmatically controlling signal offsets in integrated circuitry. In one embodiment, a buffer circuit having an offset cancellation circuit receives a signal and transmits the signal to programmable logic circuit. The programmable logic uses programmable resources and/or one or more algorithms to measure integrated circuit operations and/or operational errors associated with the offset. The control signal is fed back to an input of the offset cancellation circuit. In one embodiment, the offset cancellation circuit adjusts the offset of the signal in response to the magnitude of the offset cancellation signal received until changes associated with the offset and/or the magnitude of the operational errors are no longer attributable to the offset.