Abstract: Described herein is a circuit arrangement for processing a radio-frequency signal.

Abstract: An apparatus comprises a code generator configured to generate a coarse tuning signal and a reset signal based on a reference frequency and a phase difference signal. The apparatus also comprises a digital loop filter configured to generate a fine tuning signal based on the phase difference signal. The apparatus further comprises a voltage control oscillator configured to generate an output signal based on the coarse tuning signal and the fine tuning signal. The apparatus additionally comprises a divider configured to generate a divider frequency based on a divider control signal and the output signal. The phase difference signal is based, at least in part, on the divider frequency, and the divider is configured to be reset based on the reset signal.

Abstract: A superconducting integrated circuit, comprising a plurality of superconducting circuit elements, each having a variation in operating voltage over time; a common power line; and a plurality of bias circuits, each connected to the common power line, and to a respective superconducting circuit element, wherein each respective bias circuit is superconducting during at least one time portion of the operation of a respective superconducting circuit element, and is configured to supply the variation in operating voltage over time to the respective superconducting circuit element.

Abstract: A feedback module for preventing voltage controlled oscillator (VCO) runaway in a phase locked loop (PLL) circuit can include a first, a second, and a third input to receive a first output signal from a PLL circuit, a reference signal, and a first control signal. The feedback module may also include a feedback circuit to generate a second control signal, the second control signal being coupled to an input of the PLL circuit, wherein the feedback circuit generates the second control signal by comparing a number of cycles of the first output signal to a first threshold, and a number of cycles of the reference signal to a second threshold.

Abstract: Methods and apparatuses relating to error-tolerant memories are provided. In one example embodiment, output signals from at least three memory devices are supplied to an error correction device. The error correction device outputs a corrected data value in such a manner that, when the read data values match, this data value is output and, in at least one state in which the data values do not match, a previously output data value is retained.

Abstract: A data recovery circuit includes a comparator for providing a comparator output signal in response to a difference in voltage between a data input signal and the reference voltage, a sampling circuit for sampling the comparator output signal to provide a sample signal, a summing circuit for providing an up signal in response to an average of logic high values of the sample signal exceeding logic low values of the input samples signal, and a down signal in response to an average of the low logic values of the sample signal exceeding the logic high values of the sample signal, a counter for counting up in response to activations of the up signal and counting down in response to activations of the down signal to provide a count signal, and a reference voltage generator for generating the reference voltage in response to the count signal.

Abstract: A semiconductor integrated circuit includes a semiconductor substrate on which an oscillation circuit that generates an oscillation signal by oscillating a resonation element, and a plurality of output circuits that outputs signals based on the oscillation signal, are integrated. A package contains the semiconductor integrated circuit and the resonation element. In the semiconductor integrated circuit, an operation of a first output circuit and an operation of a second output circuit, among a plurality of output circuits, are controlled independently from each other.

Abstract: A method for detecting frequency offset of an oscillator includes: receiving an oscillation signal having an oscillation frequency; generating a self-mixing signal according to the oscillation signal; performing frequency division upon the self-mixing signal to obtain a down-converted self-mixing signal; obtaining a down-converted self-mixing frequency corresponding to a maximum power in a specific frequency range of the down-converted self-mixing signal; and computing a frequency offset of the oscillation frequency according to at least the oscillation frequency and the down-converted self-mixing frequency. A related circuit is also disclosed.

Abstract: An important component in digital circuits is a phase rotator, which permits precise time-shifting (or equivalently, phase rotation) of a clock signal within a clock period. A digital phase rotator can access multiple discrete values of phase under digital control. Such a device can have application in digital clock synchronization circuits, and can also be used for a digital phase modulator that encodes a digital signal. A digital phase rotator has been implemented in superconducting integrated circuit technology, using rapid single-flux-quantum logic (RSFQ). This circuit can exhibit positive or negative phase shifts of a multi-phase clock. Arbitrary precision can be obtained by cascading a plurality of phase rotator stages. Such a circuit forms a phase-modulator that is the core of a direct digital synthesizer that can operate at multi-gigahertz radio frequencies.

Abstract: A frequency component extracting unit (15) extracts a frequency component included in a control signal at a first frequency step size. A frequency detection unit (16) detects, from the extracted frequency component, a frequency corresponding to a natural frequency of a target object constituted of a motor (3) and a driven member (4). A frequency step size setting unit (17) sets a second frequency step size smaller than the first frequency step size. A center frequency changing unit (18) increases or decreases a center frequency of a variable bandstop filter (13) at the second frequency step size in order to output a control signal after the variable bandstop filter (13) removes a frequency component corresponding to the natural frequency after the change from the control signal.

Abstract: A time to digital converter with a successive approximation architecture (300) and a method thereof is provided. The time to digital converter (300) includes successive approximation analog to digital converter circuitry (310) configured for converting the differential voltage established in the digital to analog converter (305) of the successive approximation analog to digital converter circuitry (310) to a digital representation thereof, where the differential voltage corresponds to a measured time period representing a time difference between receipt of leading edges of two signals. Time to digital converter (300) may incorporate a current switching unit (340?) having a plurality of current switching circuits (303a-303n, 304a-304n) arranged in parallel to increase the precision of digital time output of time to digital converter (300). The plurality of current switching circuits (303a-303n, 304a-304n) can be selectively enabled to alter the sensitivity of the time to digital converter (300).

Abstract: A highly integrated monolithic self-compensated oscillator (SCO) with high frequency stability versus temperature variations is described, together with a cost effective single insertion point trimming (SPT) algorithm. The SPT is utilized to adjust the phase and frequency of the SCO to meet frequency stability versus temperature and frequency accuracy requirements for a reference clock. The techniques used in the SPT algorithm provide a robust, fast and low testing cost for the SCO. Moreover, the concepts and techniques utilized in the SCO SPT can be used effectively for any temperature compensated oscillator (TCO) including TCXO, MEMS, FBAR and RC oscillators. Additionally, the described SPT algorithm is capable of measuring the temperature sensitivity of any oscillator, estimating suitable temperature compensation parameters and adjusting the oscillator frequency to the required value simultaneously.

Abstract: System and methods are provided for communicating with multiple wireless networks using a mobile communication system. An example mobile communication system includes a first communication device configured to communicate with a first wireless network and generate a reference signal for determining a first frequency deviation between the first communication device and the first wireless network, and a second communication device configured to communicate with a second wireless network and determine a second frequency deviation between the second communication device and the second wireless network based at least in part on the reference signal.

Abstract: An analog phase-locked loop, PLL, (100, 200) is disclosed, comprising a voltage controlled oscillator (102, 202); a frequency divider (104, 204) having its input connected to an output of the VCO; a first phase detector (106, 206) arranged to detect a phase difference between an output signal of the frequency divider and a reference frequency signal and provide an output signal based on the phase difference, wherein the detectable phase difference is within one cycle of the reference frequency; a first charge pump (108, 208) connected to an output of the first phase detector and arranged to output a charge per detected phase error based on the output of the first phase detector; and an analog loop filter (110, 210) connected to the first charge pump and arranged to provide a voltage, based on the output of the first charge pump, to the VCO.

Abstract: A phase-locked loop (PLL) is provided. The PLL may include a local oscillator configured to generate an output signal, a feedback divider configured to generate a feedback signal in response to the output signal, a phase detector configured to operate the local oscillator based on a comparison between a reference signal and the feedback signal, and a reset controller in communication with each of the phase detector and the feedback divider. The reset controller may be configured to hold each of the phase detector and the frequency divider in reset, and enable each of the phase detector and the frequency divider such that at least the feedback signal is in substantial synchronization with the reference signal.

Abstract: A superconducting integrated circuit, comprising a plurality of superconducting circuit elements, each having a variation in operating voltage over time; a common power line; and a plurality of bias circuits, each connected to the common power line, and to a respective superconducting circuit element, wherein each respective bias circuit is superconducting during at least one time portion of the operation of a respective superconducting circuit element, and is configured to supply the variation in operating voltage over time to the respective superconducting circuit element.

Abstract: A clock data recovery circuit including a recovery unit and a loop control unit is provided. The recovery unit generates a recovery clock signal according to an original data signal. The recovery unit locks a frequency of the recovery clock signal to a correction frequency through a first loop, and locks the frequency of the recovery clock signal to a sampling frequency through a second loop. The correction frequency is smaller than the sampling frequency. The recovery unit adjusts the frequency of the recovery clock signal according to a reference clock signal and a first dividing signal in the first loop. The loop control unit switches the recovery unit to the first loop or the second loop according to a frequency difference between the reference clock signal and a second dividing signal.

Abstract: A phase locked loop circuit is provided which includes a bang-bang phase frequency detector configured to receive a reference signal and a feedback signal, detect a phase difference between the reference signal and the feedback signal, output a detection signal on the based on a result of the detection; an analog-digital mixed filter configured to receive the detection signal and output a control signal on the basis of the received detection signal; a voltage controlled oscillator configured to output an output signal in response to the control signal; and a divider configured to divide the output signal by n to output as the feedback signal. The detection signal is a digital signal, and the control signal is an analog signal.

Abstract: A circuit for implementing a control voltage mirror is provided. A filter includes a filter capacitor connected to a control voltage and a distal side of the capacitor connected to a voltage reference. The control voltage mirror includes an operational amplifier having a positive input connected to the control voltage, and a negative input is connected to an output and coupled to the distal side of the capacitor. Voltage across the capacitor is held to be near or at zero volts, substantially eliminating capacitor leakage current.

Abstract: An oscillator and a self-calibration method thereof are provided. The oscillator includes: an oscillation unit for generating an oscillation signal; a converting unit for converting frequency of the oscillation signal into a voltage signal; a comparison unit for comparing the voltage signal with a first voltage corresponding to a higher frequency and a second voltage corresponding to a lower frequency, and outputting a comparison result signal; an adjusting unit for storing a calibration value, adjusting the calibration value based on the comparison result signal and outputting a calibration signal corresponding to the adjusted calibration value; and a calibration unit for calibrating the frequency of the oscillation signal based on the calibration signal. Self-calibration for the frequency of the oscillation signal may be achieved, which may ensure the stability of the frequency of the oscillation signal.

Abstract: A controller for a converter is designed to receive from a measuring device measurement signals from an output line of the converter, and to analyze the measurement signals in order to generate a switching signal that has a switching frequency, wherein the controller comprises a sampler for generating a sample signal by sampling received measurement signals. The sampler is designed to perform the sampling at a sampling frequency that is less than three times the switching frequency. A converter comprises a controller in accordance with the invention.

Abstract: A slew rate enhancing system includes a first input configured to receive a first complementary signal of a differential pair and a second input configured to receive a second complementary signal of the differential pair. The slew rate enhancing system further includes a first switch configured to selectively connect the first input to an output in response to a voltage of the second input being greater than a first predetermined voltage. The slew rate enhancing system further includes a second switch configured to selectively connect the first input to the output in response to the voltage of the second input being less than a second predetermined voltage.

Abstract: A phase frequency detector realizes a highly linear conversion from noise-shaped ?? modulation into charge quantities without degradation of phase-locked loop (PLL) phase noise. The phase frequency detector may feature a construction of an Up signal output and a Down signal output, in which the Up signal rises when a divided VCO input rises, an Up signal falls when the divided VCO input falls, a Down signal rises when the divided VCO input rises, and a Down signal falls when a reference input rises. A mode selection input may be utilized for a fast lock-up PLL.

Abstract: Embodiments of the present invention enable a feedback-based VCO linearization technique. Embodiments include a frequency locked loop formed by feeding back a VCO's output into the VCO's input in negative phase by means of a frequency-to-voltage (F/V) converter. Embodiments enable constant VCO gain over a wide input tuning range and across PVT variations. Further, embodiments can be nested within a PLL, for example, with negligible area and power consumption overhead.

Abstract: A frequency synthesis device with a feedback loop includes: a phase-comparison control circuit; a frequency conversion unit voltage controlled by the control circuit; a feedback loop for supplying at least one signal issuing from the frequency conversion unit to the control circuit; at least one other control circuit for voltage control of the frequency conversion unit; and at least one other feedback loop for supplying at least one other signal issuing from the frequency conversion unit to the other control circuit.

Abstract: An output signal adjustment system includes a signal adjustment unit, a reference slope generating unit, a slope detecting unit, a voltage-to-current conversion unit, and a control unit. The slope detecting unit compares the slope of the rising and falling edges of the output signal of the reference slope generating unit with that of the signal adjustment unit and outputs a voltage signal. The voltage-to-current conversion unit converts the voltage signal into a current signal. Based on the current signal, the control unit outputs a control signal for controlling the adjustment of the signal adjustment unit to the slope of the rising and falling edges of the output signal. The output signal adjustment system can automatically adjust the slope of the rising and falling edges of the output signal, so that the output signal is insensitive to the packaging, the printed circuit board, the transmission line and other sender loads.

Abstract: Methods and systems for processing a signal with a corresponding noise profile are disclosed. Aspects of the method may comprise analyzing spectral content of the noise profile. At least one noise harmonic within the signal may be filtered based on said analyzed spectral content. The filtered signal may be amplified. The noise profile may comprise a phase noise profile. The signal may comprise at least one of a sinusoidal signal and a noise signal. At least one filter coefficient that is used to filter the at least one noise harmonic may be determined. The filtering may comprise low pass filtering. The signal may be modulated prior to filtering. The amplifying may comprise buffering. A non-linearity characteristic of the signal may be determined and a noise harmonic may be low-pass filtered within the signal based on the determined non-linearity characteristic.

Abstract: An exemplary calibration apparatus for calibrating timing mismatch of an edge rotator operating on multiple phases of an oscillator includes a capturing block arranged to capture phase error samples, and a calibrating block arranged to adjust timing of said edge rotator according to said phase error samples. An exemplary calibration method for calibrating timing mismatch of an edge rotator operating on multiple phases of an oscillator includes the following steps: capturing phase error samples, and adjusting timing of said edge rotator according to said phase error samples.

Abstract: A microwave synthesizer is disclosed that may generate low phase noise and high frequency resolution microwave signals The microwave synthesizer may include a coarse-tuning loop, the coarse-tuning loop may be adopted to generate a first signal with coarsely adjustable frequency. The coarse-tuning loop may have a first voltage controlled oscillator (VCO). An output loop, the output loop may be adopted to generate a second signal with finely adjustable frequency. The output loop may have a second VCO. A frequency mixer may be configured to couple the coarse-tuning loop and the output loop. A frequency mixer may be adopted to subtract the first and second signals. A reference frequency source may be coupled to the coarse-tuning loop and the output loop to provide reference signal for the microwave synthesizer.

Abstract: A signal receiver contains a VCO-based Analog-to-Digital Converter. As a result, some building blocks can be migrated into the digital domain.

Abstract: A semiconductor trimming circuit includes parallel coupled PMOS devices coupled in parallel with parallel coupled NMOS devices and an additional pair of dummy NMOS devices. The dummy NMOS devices are coupled in parallel with the NMOS devices. A trimming circuit for an internal clock source may be formed with an array of such switches for selecting one or more trimming capacitors of the trimming circuit. Such an array has a low leakage current and permits good trimming linearity.

Abstract: A method for processing a signal with a corresponding noise profile includes analyzing spectral content of the noise profile, filtering at least one noise harmonic within the signal based on the analyzed spectral content, and limiting the filtered signal. The noise profile may include a phase noise profile. The signal may include a sinusoidal signal and/or a noise signal. At least one filter coefficient that is used to filter the at least one noise harmonic may be determined. The filtering may include low pass filtering. The limiting may include hard-limiting of the filtered signal. A phase difference between the limited signal and a reference signal may be detected.

Abstract: In a phase-locked loop (PLL) calibration system and method, the PLL input reference clock is phase-modulated, the resulting PLL output modulation is measured, and PLL calibration signals, such as a PLL proportional path adjustment signal and a PLL integral path adjustment signal, are derived from the measured PLL output modulation.

Abstract: A reception circuit includes: an AD converter; an equalization circuit that equalizes an output of the AD converter; a determination circuit to which error information is input from the equalization circuit; and a controller that adjusts at least one of resolution and voltage range of the AD converter, in the circuit the determination circuit outputs a control signal to adjust at least one of resolution and voltage range to the controller based on the error information.

Abstract: Embodiments provide a reference-less frequency detector that overcomes the “dead zone” problem of conventional circuits. In particular, the frequency detector is able to accurately resolve the polarity of the frequency difference between the VCO clock signal and the data signal, irrespective of the magnitude of the frequency difference and the presence of VCO clock jitter and/or ISI on the data signal.

Abstract: A clock generating apparatus includes: a time-to-digital converter (TDC) arranged to convert a timing difference between a reference clock and a variable clock to generate a digital value; a calibrating device arranged to generate a control signal according to the digital value and the reference clock; a controllable oscillator arranged to generate an oscillating signal according to the control signal and the digital value; and a feedback device arranged to generate the variable clock to the TDC according to the oscillating signal, and the calibrating device calibrates the controllable oscillator to make the oscillating signal have a target oscillating frequency.

Abstract: Described herein is a self-biased oscillator. The self-biased oscillator comprises a first differentiator with adjustable resistance or capacitance, the first differentiator having an output node and an input node; and a second differentiator with adjustable resistance or capacitance, the second differentiator having an input node coupled to the output node of the first differentiator, and having an output node coupled to the input node of the first differentiator.

Abstract: A high frequency signal processing device is capable of carrying out high-accuracy modulation by a PLL circuit. A digital loop is configured in addition to an analog loop having, for example, a phase frequency detector, a charge pump circuit, and a loop filter. A digital calibration circuit is provided which searches for the optimal code set to a capacitor bank upon frequency modulation. Upon the search for the optimal code, a calibration controller first sets a division ratio based on a center frequency to a divider and determines the value of a voltage control signal using the analog loop. Then, the loop filter holds the value of the voltage control signal therein, and a division ratio corresponding to a “center frequency+modulated portion” is set to the divider, thereby operating the digital loop. The optimal code is obtained by a convergent value of the digital loop.

Abstract: An electronic circuit operating on a first clock signal includes a clock frequency overshoot detection circuit for detecting frequency overshoots in the first clock signal. The clock frequency overshoot detection circuit includes a shift register having an even number plurality of flip-flops. The flip-flops toggle to generate output bit patterns indicative of a frequency overshoot condition. A comparator connected to the shift register generates a comparison signal on detecting the frequency overshoot condition. A latch circuit connected to the comparator generates a frequency overshoot indication signal and the electronic circuit is shifted to a second (or safe) clock signal until the frequency of the first clock signal is rectified.

Abstract: Embodiments provide a reference-less frequency detector that overcomes the “dead zone” problem of conventional circuits. In particular, the frequency detector is able to accurately resolve the polarity of the frequency difference between the VCO clock signal and the data signal, irrespective of the magnitude of the frequency difference and the presence of VCO clock jitter and/or ISI on the data signal.

Abstract: A rubidium oscillator or a cesium oscillator is used as a high stability oscillator, and an OCXO being a metastable oscillator which is inferior in a long-term frequency stability compared with the above oscillators but has a high short-term frequency stability is used as a backup. There is prepared a table in which an elapsed time since an occurrence of an abnormality in the high stability oscillator and weighting (use ratio) of use of the both oscillators is corresponded, and by using this table, after the high stability oscillator recovers, an oscillation frequency of the metastable oscillator is used by 100% initially, but thereafter the weighting (use ratio) of use of the metastable oscillator is made smaller and the use ratio of the high stability oscillator is made larger in stages.

Abstract: A phase-locked loop for generating an output signal that has a predetermined frequency relationship with a reference signal, the phase-locked loop comprising a signal generator arranged to generate the output signal, a charge pump arranged to generate current pulses for controlling the signal generator, two control units for controlling a duration of the current pulses generated by the charge pump and a selection unit arranged to select either the first control unit or the second control unit to control the charge pump, wherein a first one of the control units is arranged to continuously monitor a phase-difference between the reference signal and a feedback signal formed from the output signal and to, when selected by the selection unit, control the charge pump to output a current pulse having a duration that is dependent on that phase-difference and a second one of the control units is arranged to, when selected by the selection unit, control the charge pump to output a current pulse of predetermined duratio

Abstract: A high-accuracy oscillator obtains initial control bits to generate an initial signal and generates adjacent control bits to generate an adjusted signal from the oscillator based on the adjacent control bits. Characteristics of the initial signal and the adjacent signal are compared to a preset value to determine which of the initial signal and the adjusted signal is closer to a target signal. The closer of the initial signal and the adjusted signal to the target signal is output from the oscillator.

Abstract: A reference assisted control system and method thereof are disclosed. The method comprises: receiving a first input signal and a second control signal; generating a first intermediate signal in accordance with a difference between the first input signal and the first output signal; filtering the second control signal to generate a second intermediate signal; performing a weighted sum of the first intermediate signal and the second intermediate signal to generate the control signal; and outputting the first output signal in accordance with the control signal.

Abstract: In an embodiment, an oversampled data converter includes a lowpass filter having a filter stage comprising a dynamic limiter, where the dynamic limiter having a limit set by an signal level at an input to the oversampled data converter. The oversampled data converter also includes a quantizing block comprising an input coupled to an output of the lowpass filter and an output coupled to an input of the lowpass filter.

Abstract: A PLL includes: a charge-pump equalizer which has a plurality of charge pumps generating charge currents according to phase-difference signals, each being generated by delaying the phase-difference signal by different times, adds and outputs the charge currents generated by the charge pumps; a replica circuit, having ideal characteristics of a loop filter and a voltage controlled oscillator, which input a digital value having phase difference of the phase-difference signals, and generates a replica output according to the ideal characteristics; and a coefficient generating circuit which smoothes correlation values of the difference signals and the phase-difference signals to generate charge pump coefficients, and negatively feeds back the same to the plurality of charge pumps. The charge pumps generate the charge currents each having current values corresponding to the charge pump coefficients.

Abstract: A phase-locked loop for generating an output signal that has a predetermined frequency relationship with a reference signal, the phase-locked loop comprising a signal generator arranged to generate the output signal, a charge pump arranged to generate current pulses for controlling the signal generator, two control units for controlling a duration of the current pulses generated by the charge pump and a selection unit arranged to select either the first control unit or the second control unit to control the charge pump, wherein a first one of the control units is arranged to continuously monitor a phase-difference between the reference signal and a feedback signal formed from the output signal and to, when selected by the selection unit, control the charge pump to output a current pulse having a duration that is dependent on that phase-difference and a second one of the control units is arranged to, when selected by the selection unit, control the charge pump to output a current pulse of predetermined duratio

Abstract: A phase lock loop is disclosed comprising a first phase detector configured to receive a first clock and a second clock and output a first detector output signal; a second phase detector configured to receive the first clock and the second clock and output a second detector output signal; a summing circuit to sum the first detector output signal and the second detector output signal into a control signal; a loop filter to filter the control signal into a refined control signal; and a controllable oscillator to generate the output clock in accordance with a control by the refined control signal.

Abstract: A digitally controlled circuit and method includes an error input coupled to a proportional path. The proportional path includes a selector which directly receives the error input as a select signal. The selector receives a proportional control weight from a location other than the proportional path wherein the proportional control weight is input to a digitally controlled oscillator (DCO).

Abstract: A phase locked loop has a controlled oscillator for outputting an oscillator signal depending on a control signal. A comparator generates a comparison result from a comparison between a reference frequency signal and a feedback signal derived from the oscillator signal. The phase locked loop also has a filter block for filtering the comparison result and for deriving the control signal from the comparison result, where the filter block has a loop filter and a rejection filter for the frequency-selective attenuation of at least one first interference frequency in the comparison result.