Abstract: A circuit comprising a plurality of phase locked loop circuits, a control circuit and a plurality of storage elements. Each of the plurality of phase locked loop circuits may present a recovered data signal and a recovered clock signal in response to one of a plurality of serial data streams, a clock signal and one of a plurality of indication signals. The control circuit may present a counter signal in response to the recovered clock signals. The plurality of storage elements may each be configured to present one of the indication signals in response to the clock signal, a select signal and the counter signal.

Abstract: A phase-locked loop of the type including a locking aid circuit providing a d.c. presetting signal representative of the carrier frequency of an input signal to set the quiescent frequency of a controlled oscillator of the phase-locked lop. The locking aid circuit includes a monostable latch clocked by the input signal to provide pulses of predetermined width, the presetting signal corresponding to the mean value of these pulses.

Abstract: A phase-lock loop (PLL) has an oscillator having a plurality of operating curves. During PLL auto-trim operations, the oscillator is automatically trimmed to an appropriate oscillator operating curve for use during normal PLL operations. In particular embodiments, the PLL is a charge-pump PLL having a phase/frequency detector (PFD) that generates error signals based on comparing an input signal and a PLL feedback signal; a charge pump that generates amounts of charge corresponding to the error signals; a loop filter that accumulates the amounts of charge to generate a loop-filter voltage; and a voltage-controlled oscillator (VCO), where the VCO output signal is used to generate the PLL feedback signal. During normal PLL operations, the loop-filter voltage is applied to the voltage input of the VCO.

Abstract: A phase synchronous circuit, in the process of locking an internal signal to an input signal by a PLL loop, makes a frequency of the internal signal stepwise approximate to a frequency of the input signal under digital PLL control at a first stage, and adjusting a phase under analog PLL control at a next stage, thus controlling a variable frequency oscillator at the two stages. A gain with which an analog PLL control system is burdened can be thereby reduced, and a gain of VCO may not be set larger than required even if a frequency of an output signal f.sub.out is high.

Abstract: A phase locked loop circuit for absorbing characteristic variations of phase comparator components beforehand in adjusting mode. With the variations thus adjusted and co-opted, any intrinsic error of the phase comparator is prevented from appearing as a phase difference upon transition from adjusting mode to normal operation mode. The scheme inhibits lock range deviations or capture range variations in normal operation mode, permitting a stable phase locked loop function.

Abstract: In an oscillating circuit, an oscillator generates an oscillation signal with a frequency, increases the frequency of the oscillation signal in response to a frequency increase signal and decreases the frequency of the oscillation signal in response to a frequency decrease signal. A detecting unit receives the oscillation signal and a reference signal. The detecting unit outputs the frequency increase signal to the oscillator when a ratio of the frequency of the oscillation signal to a frequency of the reference signal is smaller than a first predetermined value, and outputs the frequency decrease signal to the oscillator when a ratio of the frequency of the oscillation signal to the frequency of the reference signal is larger than a second predetermined value.

Abstract: In an information signal recording and reproducing apparatus, reproduced data is equalized by an equalizer and a clock signal synchronized in phase with the reproduced data is generated. An equalizing characteristic of the equalizer is controlled according to a difference in frequency between the clock signal and the reproduced data, and a generating operation for the clock signal is controlled according to a phase difference between the clock signal and the reproduced data. The clock signal thus can be stably generated without being affected by variations of temperature and variations due to aging. The equalizer thus has an adequate equalizing characteristic. The apparatus includes a recording mode and a reproduction mode. In the recording mode, a recording clock signal is generated by a clock signal generating circuit and a digital signal is recorded by using the recording clock signal.

Abstract: The present invention is directed to providing a phase detector capable of establishing phase-locked-loop operation in a highly accurate and reliable manner. For example, exemplary embodiments detect a phase difference between at least two input signals to phase lock the input signals to one another. Exemplary embodiments include two phase detectors each of which receives the two input signals (e.g., three-state phase detectors), and each of which is forced to operate outside of its dead-band region by introducing predetermined phase delays for its inputs. Each of the two phase detectors detects a phase difference between its respective inputs. The two phase differences are then combined to produce a composite output signal formed as a net charge proportional to the net phase difference detected by the two phase detectors.

Abstract: A universal synchronizer for use in a variety of telecommunications systems based on direct digital phase synthesis (DDPS) include digital and analog PLLs. The synchronizer may be used for wireless, optical, or wireline transmission systems and for a wide ranges of data rates. Digital phase detectors are used in the digital PLLs for comparing the phase of the local clock f.sub.L with the phase of a respective digital reference clock, and provides a respective phase error signal. A digital phase synthesis unit receives the phase error signal and a target phase error and produces a first and a second set of control signals for driving an error driver. The error driver generates the control voltage for adjusting the frequency of a VCXO that is used for all PLLs, to lock the respective PLL. The first set of control signal generates the control voltage for the digital PLLs, and the second set of control signals generates the control voltage for the analog PLLs and for the acquisition mode of operation of all PLLs.

Abstract: A lock circuit for indicating a locked/unlocked condition of phased lock loops circuits, which uses a reference clock signal input to a good-cycle counter and to a bad-cycle counter to signal a set/reset latch to output a signal indicating whether or not the phase of the output signal and input clock are in phase. Phase detector inputs are XOR gated to produce a pulse when the phase locked output clock is in a bad cycle indicated by the phase locked output clock not being in-phase with its input clock. Pulses on the XOR gate output on a bad cycle feed a single cycle counter reset circuit. The single cycle counter reset circuit on every cycle resets one of the bad and good counters based on its detection of a bad cycle pulse from the XOR gate. The good-cycle counter's output is to the SET input of the set/reset latch, and the bad-cycle counter's output is to the RESET input of the set/reset latch . We enable specific cycling of both the good and bad counters.

Abstract: An oscillator with higher frequency stability. The phase arator circuit 17 detects a phase difference between a second-interval reference pulse signal 16 outputted from a GPS receiver 15 and an almost second-interval pulse signal 14 obtained by dividing output of a voltage-controlled oscillator 11 with a counter circuit 13. The delay circuit 31 and the difference calculating circuit 32 determine changes in the phase difference every second, while the averaging circuit 35 determines the mean value of the changes. The control voltage is changed to decrease the mean value of the changes to first match the frequency of the pulse signal 14 with that of the reference pulse signal 16, and the voltage of the control signal at this moment is stored. The voltage of the control signal is then changed to match the phases. The voltage of the control signal is restored to the stored value when the phases match.

Abstract: Apparatus, and an associated method, for calibrating a device responsive to values of a reference signal. The reference signal may be subject to short-term disturbances. In one implementation, a cellular radio base station utilizes a Stratum-2 oscillator to which to phase-lock a base station VCO. Compensation is made for the aging of the Stratum-2 oscillator, thereby to provide a regulation signal causing the VCO to exhibit acceptable short-term and long-term frequency stability characteristics.

Abstract: A phase-locked loop includes a switched phase detector, a loop filter and an oscillator connected in series, as well as a device for technology compensation, in particular a course control device. An operating point is adjusted during a starting phase of the phase-locked loop through the use of the course control device in such a way that the damping and natural frequency of the phase-locked loop is independent of fluctuations in technology parameters.

Abstract: A PLL frequency synthesizer for realizing high-speed operation in a frequency synthesizer having a small channel interval .DELTA.f. There are provided n-number of phase comparators, feedback frequency dividers, and reference signal frequency dividers, and a timing generating section for outputting a signal causing each of the frequency dividers to become enabled every cycle of n.times..DELTA.f. An OR gate for superposing each phase comparison signal. Each phase comparison signal is sent to a charge pump after a cycle of n.times..DELTA.f, and the reference frequency is capable of being raised to n times the channel interval .DELTA.f. Further, a control section monitors lock detection of each phase comparator, thus implementing voltage control of each phase comparison system. When the synthesizer arrives at convergence-synchronization, the power sources to all systems are turned OFF except for the phase comparison system initiating the lock signal.

Abstract: The invention provides a demodulation PLL wherein: the first position of a switch, which is controlled by a control circuit, respectively connects the outputs of a mixer and a LP filter to high gain and low gain inputs of an oscillator when frequency signals at the inputs of the mixer have not converged sufficiently, i.e. during the PLLs tuning mode; the second position of the switch respectively connects the outputs of the mixer and the LP filter to the low gain and high gain inputs of the oscillator when the frequency signals at the inputs of the mixer and the signal levels on the input and output of the filter have converged sufficiently, i.e. during the PLLs demodulation mode.

Abstract: An A/D converter performs sampling of a reproduced signal from a reading device in synchronism with a clock signal from a PLL circuit and outputs the sampled value to a binary circuit and a phase comparator. The phase comparator detects a change from a positive sampled value to a negative one or from the negative sampled value to a positive one (zero-cross) and outputs a phase error signal corresponding to the zero-cross to a frequency comparator. The frequency comparator outputs a frequency error sensed in reference to a variation of the phase error signal to a switch through a low pass filter. The switch outputs the frequency error to an adder only when the PLL is not in a lock state. The adder outputs a sum of the frequency error and the phase error to a VCO through a loop filter. The VCO generates the clock signal with a frequency corresponding to the sum and supplies it to the A/D converter.

Abstract: According to the preferred embodiment, a phase-locked loop system is provided that overcomes the limitations of the prior art by providing the ability to switch output frequencies without a disruption in the phase lock of the output signal. The system uses a first phase-locked loop coupled with a second phase lock-loop such that their output signals are phase aligned and a switching mechanism for switching between the first phase lock output signal and the second phase lock loop output signal. The system is thus able to switch the frequency of its output without a disruption in the phase-lock of the signal.

Abstract: The present invention concerns apparatus and method for setting up the tuning frequency of a PLL, demodulator that includes a VCO. Frequency synthesizing circuitry controls the VCO via a first switched control path. Comparison circuitry provides a first signal that corresponds to the difference between the output frequency of the VCO and a reference frequency. Control circuitry is provided that is responsive to a plurality of signals including the first signal for operatively controlling the apparatus. The apparatus further includes: a ceramic resonator oscillator for providing the reference frequency; a non-volatile memory for storing the value of the first signal; and comparison circuitry for comparing a stored value of the first signal with a current value of the first signal so as to produce a second signal for adjusting the tuning frequency of the frequency synthesizing circuitry in response to the second signal.

Abstract: A horizontal synchronous circuit comprises a horizontal oscillator, an AFC portion operative to compare in phase a horizontal oscillation output signal from the horizontal oscillator with a horizontal synchronizing signal from the outside to produce a comparison output signal and to supply the horizontal oscillator with a control signal based on the comparison output signal for controlling a frequency of the horizontal oscillation output signal, a free-running frequency controller operative to produce a control signal corresponding to a frequency of the horizontal synchronizing signal from the outside and to supply the horizontal oscillator with the control signal for controlling a free-running frequency of the horizontal oscillator to be coincident with the frequency of the horizontal synchronizing signal from the outside, and a negative feedback control portion operative to produce an additional control signal based on the comparison output signal obtained from the AFC portion or the control signal supplied

Abstract: A variable frequency synthesis apparatus and method use a phase prediction signal to enable integer division in the feedback path of a phase-lock-loop to provide an output signal at a rational frequency multiple of an applied reference signal. A fixed integer divide ratio is maintained within each period of the reference signal. The output signal provided by a variable frequency oscillator is frequency divided and is phase compared to the reference signal. The phase comparison produces a predictable, time-varying phase difference signal based on a known frequency difference between the output signal and the reference signal. The phase prediction signal cancels the predictable phase difference signal and isolates an phase error signal used to steer, or adjust, the frequency of the oscillator to precisely equal the rational frequency multiple of the applied reference signal when the phase error signal is minimized.

Abstract: A phase-locked loop (PLL) includes a voltage controlled oscillator (VCO), a charge pump, a phase detector and a frequency detector. The phase detector detects the phase difference between an incoming signal and a VCO signal. The frequency difference between the incoming signal and a reference signal is detected by the frequency detector separately from the phase detector. During the process of attaining phase lock, the phase and frequency detectors operate simultaneously. The VCO signal is phase-locked to the incoming signal when it is present. When the incoming signal is absent, the VCO maintains a frequency close to an intended bit rate by frequency locking to a multiple of the reference signal. It, thus, avoids extreme system behavior and greatly assists rapid reliable phase lock when the incoming signal is applied following a period when it is absent.

Abstract: A phase lock loop system includes: a phase detecting circuit which operates on the basis of a signal waveform; a current output circuit for generating a current value from a phase difference detected by the phase detecting circuit; a filter which is constructed by only a resistor in a phase locked state by a synchronizing signal and by a capacitor and the resistor upon phase following state; and a voltage controlled oscillator for controlling an oscillation frequency by a voltage output of the filter. The phase lock loop system operates as a primary phase lock loop circuit in the phase locked state by the synchronizing signal and operates as a secondary phase lock loop circuit upon phase following state.

Abstract: A PLL circuit has a feedback loop including a plurality of feedback circuits in parallel and a combining circuit. The feedback circuits receives an output signal of the PLL circuit and produce feedback output signals, respectively. The combining circuit combines the feedback output signals into a feedback signal which is used to be compared to a reference signal. The feedback circuits in parallel each divide a frequency of the output signal by a predetermined number and the combining circuit performs logical OR of the feedback output signals.

Abstract: A frequency synthesizer (100) is utilized for producing an output signal (124) which is phase locked to a reference signal (110) operating at a reference frequency. The frequency synthesizer (100) comprises a main phase lock loop (PLL) (102), and a tracker PLL (128). The main PLL (102) includes a phase detector (112), two frequency dividers (108, 126), a loop filter (116), a notch filter (118), and a controlled oscillator (122). The tracker PLL (128) phase locks to the reference signal (110), and biases the notch filter (118) in order to maintain an accurate lock on the notch frequency which is proportional to the reference frequency. All circuits are integrated in the same monolithic device in order to track parametric tolerances such as transconductances of the operational transconductance devices included in the tracker PLL (128) and the notch filter (118).

Abstract: In a phase-locked oscillating circuit comprising a voltage-controlled oscillator responsive to a control voltage for generating an output signal having an output frequency and a variable gain amplifier having a controllable gain and supplying the voltage-controlled oscillator with the control voltage, a frequency fluctuation detecting circuit detects fluctuation in the output frequency of the output signal to control the controllable gain on the basis of magnitude of the fluctuation in the output frequency of the output signal. The phase-locked oscillating circuit may comprise a reference voltage generating circuit for supplying the variable gain amplifier with a controllable reference voltage in response to the control voltage.

Abstract: A biphase stable FPLL includes a lock switch, operated in response to a frequency lock condition, that forces a predetermined voltage on the input of the third multiplier to guarantee that the loop locks up in a phase that produces a desired polarity of demodulated signal. A frequency lock indicator operates the lock switch to force the predetermined voltage on the third multiplier irrespective of the actual lock up phase of the loop. If the lock up phase is wrong, the voltage reversal causes the VCO to slip 180.degree. in phase and the loop locks up in its other bistable state.

Abstract: A frequency detection circuit detects the frequency of a horizontal sync signal, and generates a mode switching signal corresponding to the detected frequency. A voltage-controlled oscillator constituting a PLL circuit has a plurality of oscillation modes obtained by dividing a frequency equal to an integer multiple of the frequency of the horizontal sync signal into a plurality of frequency ranges, and oscillates signals in the respective frequency ranges in accordance with control voltages output from a filter. The oscillation modes of the voltage-controlled oscillator are switched in accordance with the mode switching signal output from the frequency detection circuit. In the voltage-controlled oscillator, since the frequency range in each oscillation mode is narrow, the oscillation gain can be suppressed low, and a deterioration in jitter characteristics can be prevented.

Abstract: Jitter attenuators (100) with a phase detector (104) to control a crystal oscillator to remove jitter wherein the phase detector includes both a sequential phase/frequency detector (200) of low transistor count and an arrangement of two sequential phase/frequency detectors (198 and 200) to increase gain and two drivers for the crystal oscillator.

Abstract: A phase lock loop of a synthesizer (143) is controlled by applying (506) modern optimal control techniques for a predetermined period in a computing engine (222), in response to an error being introduced into a signal of the phase lock loop, and by utilizing (510) classical control techniques for controlling the phase lock loop after the predetermined period.

Abstract: A system (100) for distributing a clock signal to many points on an integrated circuit. The system includes using a delay lock loop with specific digital circuits to accomplish the phase error detection and delay element selection. In one embodiment, two flip-flops are used to detect a phase error. In another embodiment, both macro (202) and micro phase detectors (218) are used and the delay element selection is performed in two stages by using a shift register (210) in a first stage and a counter (220) in a second stage. Another feature of the present invention is, the ability to distribute the reference clock or a synchronized clock to different portions of the circuitry on an integrated circuit. Multiple clock distribution systems are provided which may be selected.

Abstract: A system for processing signals by utilizing a tracking loop that contains two or more detectors that operate simultaneously in order to detect a frequency shift in the locally generated reference signal. A correction can then be transmitted to the tracking loop filter to minimize the effect of the detected frequency shift. In this manner lock can be maintained without the expenditures associated with the use of temperature controlled or compensated oscillators.

Abstract: A sampled phase locked loop is phase-locked with support from a conventional phase locked loop (PLL). The support value from the PLL is locked with the aid of a sample and hold circuit. The locked support value is summed together with the control signal from the sampled loop in order to control a controlled oscillator which can suitably be a voltage-controlled oscillator. Accuracy of the support values depend on the PLL's resolution. The sampled loop is coupled in without any signal being built up in the sampled loop's loop filter.

Abstract: A phase frequency detecting circuit is designed to produce an output voltage which varies with respect to an input phase difference between a base phase and a reference phase. Herein, a first phase frequency comparator produces a first phase error signal which is proportional to the input phase difference. A first integration circuit performs integration on the first phase error signal to produce a control voltage. Next, a second phase frequency comparator receives a frequency-divided base phase and a frequency-divided reference phase to produce a second phase error signal. A second integration circuit performs integration on the second phase error signal to produce a frequency-divided control voltage. An offset voltage creating circuit creates an offset voltage. Herein, the offset voltage is created based on the frequency-divided control voltage; and a sign thereof is determined responsive to a relationship between the control voltage and frequency-divided control voltage.

Abstract: An apparatus for acquiring tuning for a tuning frequency at a high speed. In a receiver, a tuning control unit holds inputted tuning frequency information at a designated address in accordance with a storage designation signal supplied from a control unit and controls the frequency of a VCO based on the tuning frequency information held at a designated address in accordance with a read designation signal supplied from the control unit. Further, in a frequency comparison loop including a frequency comparator for acquiring a frequency difference between a target tuning frequency and the VCO frequency, a count time setting circuit sets the count time for measuring the VCO frequency, and the count time is increased whenever measurement of the VCO frequency is repeated.

Abstract: A protective circuit for a phase lock loop ensures that the VCO does not initiate a runaway condition when outputting a signal having a frequency higher than the feedback divider can respond to. During normal phase lock operation, a counter keeps track of the PLL input signal and is reset by the feedback divider. In the runaway condition the counter is not reset and triggers a control signal to the VCO. A second counter can be used to keep track of the feedback divider output and to reset the first counter. When the first counter far outruns the second counter the control signal is triggered.

Abstract: The method of providing a frame clock for data signals in a communications network includes determining phase positions (P1, P2, . . . ) of respective frame clock information (RT1, RT2, . . . ) of incoming data signals with respect to frame clock information (RTN) available at a switching point in at least one switching device (NK1, NK2, . . . ); storing in a memory device (SPN) in the at least one switching device (NK1, NK2, . . .

Abstract: The phase locked loop (PLL) control apparatus includes a selector which selects input signals, for an active system and a standby system having a clock signal and a frame pulse signal synchronized with the clock signal, by means of a line switching signal. The phase difference between the frame pulses before and after the line switching is output by a frame pulse phase comparator. On the other hand, accompanying the line switching, a frequency divided clock output from a frequency divider is branched in a PLL control circuit which carries out the phase matching of the clocks. The branched clock is converted to pseudo clocks with duty factors larger than and smaller than 50% by a duty factor controller. A clock selector which selects one out of the frequency divided clock and the pseudo clock in response to the phase difference of the frame pulses is installed between a clock phase comparator and a low-pass filter of the PLL control circuit.

Abstract: A biphase stable FPLL includes a polarity determination circuit that ascertains the lockup phase of the FPLL based upon the polarity of the pilot in the digital signal. A frequency lock indicator circuit determines from the recovered pilot when frequency lock has occurred and the polarity determination circuit is responsive thereto for inverting the phase of the incoming signal (or alternatively, of the outgoing signal) as determined in order to supply an output signal of predetermined polarity. The frequency lock indicator consists of a zero crossings detector and a latch that is sampled for a time period. The zero crossings detector is a delay and an exclusive OR gate. An optional confidence counter may be used with the latch to determine when frequency lock has occurred to provide the lock indicator signal.

Abstract: A frequency synthesizer having two atomic frequency standard inputs that is adapted to provide seamless switching or transition between the atomic frequency standard inputs with no change in the synthesizer output phase and frequency. The synthesizer includes a multichannel phase comparison system, each channel adapted for handling an atomic frequency standard input, a digital phase lock loop, a digital to analog converter, and a voltage controlled crystal oscillator which provides the synthesizer output. The phase comparison system is adapted to continually monitor the integrity of the atomic frequency standard inputs and to continually estimate the phase differences between the two atomic frequency standard inputs. The phase difference is used to estimate the proper phase and frequency offset between the primary and secondary inputs.

Abstract: A clock recovery circuit comprises first and second voltage-controlled oscillators having identical characteristics. The first oscillator is incorporated into a frequency synthesis loop in such a way as to oscillate, in response to a first control voltage, at a frequency equal to a reference frequency multiplied by a number N. The second voltage-controlled oscillator is incorporated into a phase tracking loop which, when activated, locks its oscillation phase relative to that of the received data signal. The second oscillator delivers the recovered clock signal. A comparator determines whether the frequency of the second oscillator, divided by N, satisfies the condition of not deviating from the reference frequency by more than a predetermined limit value. The phase tracking loop is activated only when the latter condition is satisfied, and the first control voltage is fed to the control input of the second oscillator when the condition is not satisfied.

Abstract: A multi-level demodulator has a VCO (32) and two reference frequency sources (50, 41). A relatively long time-constant loop (45, 47) has an input coupled to the VCO, an input coupled to one of the reference frequency sources (41) and an output coupled to the VCO. A relatively short time-constant loop (51, 30) has an input coupled to the VCO, an input coupled to the other reference frequency source (50) and an output coupled to the VCO.

Abstract: A PLL circuit is provided which has excellent quick response and noise resistance. A bias data memory circuit 7 previously stores frequency assignment data Da, for assigning the frequency of output signals S1 of VCO 1, as an address and the value, of a control voltage Vc corresponding to the assigned frequency, as bias data Db. A bias voltage production circuit 6 produces a bias voltage Vb of a voltage value provided by the bias data Db output from the bias data memory circuit 7. A switch control circuit 5 compares a phase difference voltage Vd, output from a phase comparison circuit 2, with the bias voltage Vb output from the bias voltage production circuit 6.

Abstract: A system and method for establishing the frequency of a voltage controlled oscillator ("VCO") within narrowly defined frequency bands. The resonant circuit of the VCO uses selectable elements, such as varactor diodes, to establish the operating frequency band. The control voltage of the VCO is varied within a voltage range to adjust the VCO output frequency. A phase detector compares the VCO output to a reference signal. If the phase detector determines that there is an imbalance between the VCO output and the reference signal, then it produces a signal which indicates whether the VCO frequency should be increased or decreased to match the reference signal frequency. If the control voltage is outside of the voltage range, then the system allows the operating frequency band to be changed by varying the number of selectable elements in response to the phase detector signal.

Abstract: A dynamic phase selector phase locked loop circuit includes: an A/D converter for receiving an input to be sampled; a phase detection circuit for determining the phase error between the input signal and a clock signal; a clock circuit, responsive to the phase detection circuit, for providing the clock signal to the A/D converter for timing the sampling of the input signal; the clock circuit including a delay circuit having a number of delay taps; and a phase selector circuit, responsive to the phase detection circuit, for initially gating the clock signals to the A/D converter from the clock circuit, and enabling one of the delay taps to dynamically adjust the phase of the clock signal and reduce the initial phase error.

Abstract: A hybrid analog-digital phase error detector (107) is utilized for detecting a phase error between first and second clock signals (132, 104). Digital and analog phase error detectors (108, 116) are connected to the first and second clock signals (132, 104), and are utilized for producing digital and analog phase error values (110, 118). The digital and analog controllers (112, 120) connected to the digital and analog phase error detectors (108, 116) execute digital and analog control algorithms based on the digital and analog phase error values (110, 118) to produce digital and analog control signals (114, 122). A summer (124) connected to the outputs of the digital and analog controllers (112, 120) combines the analog control signal (122) and the digital control signal (114) to produce a composite control signal (126) representing the phase error.

Abstract: The invention provides a demodulation PLL wherein: the first position of a switch, which is controlled by a control circuit, respectively connects the outputs of a mixer and a LP filter to high gain and low gain inputs of an oscillator when frequency signals at the inputs of the mixer have not converged sufficiently, i.e. during the PLLs tuning mode; the second position of the switch respectively connects the outputs of the mixer and the LP filter to the low gain and high gain inputs of the oscillator when the frequency signals at the inputs of the mixer and the signal levels on the input and output of the filter have converged sufficiently, i.e. during the PLLs demodulation mode.

Abstract: A high speed digital signal transceiver in CMOS technology, in which the receiver has a clock signal extraction circuit, which is capable of self-aligning on incoming data with no spurious locks. Utilizing the PLL technique, the circuit generates a clock signal locked to the incoming signal utilizing a local oscillator, voltage-controlled by two feedback loops, a main one for frequency and phase corrections and a secondary one for phase correction. Moreover, original circuit solutions for the phase detectors and the low-pass filters are also envisaged.

Abstract: A frequency detector of a phase-lock-loop circuit is used for measuring a frequency error between a frequency of an output signal of an oscillator and a frequency of a synchronizing signal. When the frequency error in each of 32 periods of the synchronizing signal exceeds a predetermined magnitude, the phase-lock-loop circuits begins operating in a coarse frequency correction mode. As long as the 32 periods have not lapsed, the phase-lock-loop circuit operates in an idle mode of operation and the oscillator is not corrected. As a result, during vertical retrace, when equalizing pulses occur, the phase-lock-loop circuit is not disturbed by a large frequency error.

Abstract: A phase-locked-loop circuit includes an oscillator having switched capacitors that are selectively coupled to a positive feedback path of the oscillator in a coarse frequency error correction mode of operation. When the frequency error is small, the circuit operates in a fine error correction mode without varying the selection of the switched reactive elements.

Abstract: A phase comparing circuit includes a first device for generating a detection signal in response to a multi-level signal. The detection signal represents whether or not the multi-level signal is in a given level. A second device connected to the first device is operative for generating a first control signal in response to the detection signal generated by the first device and a clock signal. The first control signal represents a time interval between a leading edge of a pulse in the detection signal and a strobe point of the clock signal which immediately follows the leading edge of the pulse in the detection signal. A third device connected to the first device is operative for generating a second control signal in response to the detection signal generated by the first device and the clock signal. The second control signal represents a time interval between the strobe point of the clock signal and a trailing edge of the pulse in the detection signal.