With Intermittent Comparison Controls Patents (Class 331/14)
  • Patent number: 10505555
    Abstract: A phase-locked loop (PLL) includes a time-to-digital converter (TDC) to receive a reference clock. The PLL also includes a digital loop filter coupled to the TDC. The digital loop filter repeatedly generates frequency control words. An analog phase-locked loop (APLL) includes a programmable frequency divider. A non-volatile memory device stores a value from the digital loop filter. The PLL includes a free-run control circuit. Upon a power-on reset process, the free-run circuit retrieves the value from the non-volatile memory to adjust a divide ratio of the programmable frequency divider based on the retrieved value. Upon a reference clock provided to the TDC, the free-run control circuit continues to adjust the divide ratio of the programmable frequency divider based on both the retrieved value from the non-volatile memory and a current frequency control word from the digital loop filter.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: December 10, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sinjeet Dhanvantray Parekh, Jayawardan Janardhanan, Christopher Andrew Schell, Arvind Sridhar
  • Patent number: 10396974
    Abstract: An apparatus includes signal control circuitry, a phase-locked loop (PLL), and a correlation circuit. The signal control circuitry provides a reference clock signal carrying pseudo-random phase noise and as derived from an application clock signal and pseudo-random noise. The PLL, responsive to the reference clock signal carrying the pseudo-random phase noise, provides an output signal that is related to the phase of the reference clock signal. The correlation circuit self-tests the PLL by cross-correlating a signal corresponding to the output signal from the phase detector with the pseudo-random noise and, in response, by assessing results of the cross-correlation relative to a known threshold indicative of a performance level of the PLL.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: August 27, 2019
    Assignee: NXP B.V.
    Inventors: Jan-Peter Schat, Ulrich Moehlmann
  • Patent number: 10312924
    Abstract: A timing signal generation device includes a GPS receiver, an atomic oscillator, a phase comparator, a loop filter, and a divider, a temperature sensor, a DDS, and a DSP. The GPS receiver outputs a reference timing signal. The atomic oscillator outputs a clock signal in accordance with an input voltage value. The phase comparator, the loop filter, and the divider adjust the voltage value in accordance with a synchronization status between the reference timing signal and the clock signal. The temperature sensor outputs a signal depending on the temperature of the atomic oscillator. The DDS converts the frequency of the clock signal and outputs a signal obtained by converting the frequency. The DSP controls the DDS based on an output of the temperature sensor.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: June 4, 2019
    Assignee: Seiko Epson Corporation
    Inventors: Yoshiyuki Maki, Hiroyuki Shimada
  • Patent number: 10290246
    Abstract: A display apparatus includes a plurality of pixels for receiving a plurality of gate signals, and a plurality of data voltages, a level shifter for receiving a gate driving voltage and a plurality of gate control clocks to generate a plurality of reference clocks, and for generating a plurality of control clocks by delaying the reference clocks by a predetermined time, a gate driver for outputting the gate signals in response to the control clocks, a short circuit protector for sensing a current of each control clock at each falling edge of each gate control clock to detect a static current of the each control clock, and for outputting a shut-down signal based on a count of the static current detection, and a voltage generator for providing the gate driving voltage to the level shifter, and shutting down in response to the shut-down signal.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: May 14, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jongjae Lee, Seokhwan Lee, Dae-sik Lee, Seyoung Heo
  • Patent number: 10126775
    Abstract: A method and apparatus for performing current control for an integrated circuit are described. In one embodiment the apparatus comprises core logic coupled to receive a first current; a clock generator to generate a first clock signal; and a closed loop current controller coupled to the clock generator and coupled to provide a second clock signal to the core logic based on the first clock signal, the current controller to control an amount of the first current received by the core logic by changing the first clock signal to generate the second clock signal.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: November 13, 2018
    Assignee: INTEL CORPORATION
    Inventors: Alexander Gendler, Kosta Luria, Arye Albahari, Ohad Nachshon
  • Patent number: 10063367
    Abstract: A method for clock recovery that may include obtaining an output signal from a phase locked loop (PLL) device. The method may further include determining, using a digital phase detector, the output signal, and a transmitter clock signal, an amount of phase difference between the output signal and the transmitter clock signal. The method may further include filtering, using a phase rotator and a digital accumulator, a portion of the amount of phase difference from the output signal to generate a filtered signal.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: August 28, 2018
    Assignee: Ciena Corporation
    Inventors: Sadok Aouini, Naim Ben-Hamida, Christopher Kurowski, Lukas Jakober
  • Patent number: 9991897
    Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for generating oscillating signals. For example, certain aspects of the present disclosure provide a phase-locked loop (PLL) having a first switch coupled to a sampling input node of the PLL, an integrator coupled to an output of the sampling circuit, and a voltage-controlled oscillator (VCO) having an input coupled to an output of the integrator. In certain aspects, the PLL may also include a feedback path coupled to an output of the VCO and a control input of the first switch.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: June 5, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Dongmin Park, Jong Min Park, Yiwu Tang
  • Patent number: 9836078
    Abstract: In some embodiments, a tight loop mode is provided in which most, if not all of, the clock distribution circuitry may be bypassed during an initial frequency lock stage.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: December 5, 2017
    Assignee: Intel Corporation
    Inventors: Allan Feldman, Nasser Kurd, Mark Neidengard, Vaughn Grossnickle, Praveen Mosalikanti
  • Patent number: 9819481
    Abstract: A method and apparatus for clock recovery is provided. The method begins when a reference pulse is extracted from a signal. This reference pulse is then compared with a clock signal. A phase of the extracted reference signal is then detected, and is done in relation to the clock signal. Phase differences between the extracted reference signal with respect to the clock signal are accumulated over a predetermined period of time. This accumulating continues until a predetermined number of phase differences has been accumulated. The accumulated phase differences are then averaged. The apparatus includes: a phase detector; a phase averaging unit in communication with a clock generator and a controller; a lock detector in communication with the phase averaging unit and a loop filter; at least one adder; at least one bypass filter; and at least one accumulator.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: November 14, 2017
    Assignee: MACNICA AMERICAS, INC
    Inventor: David Heath Culley
  • Patent number: 9812775
    Abstract: A system for rapidly steering a directive beam in an antenna is provided herein. The system includes: an antenna configured to produce a directive beam; means for steering the beam rapidly, along small angles; and means for steering the beam slowly, along large angles. According to one embodiment, the antenna is implemented as a phased array antenna, wherein the means for steering the beam rapidly, along small angles, is implemented as a phased array control, and wherein the means for steering the beam slowly, along large angles, is a mechanical mechanism implemented using gimbals. According to another embodiment, the antenna includes a main reflector and a sub reflector, and wherein the means for steering the beam rapidly, along small angles, mechanically controls the sub reflector, and wherein the means for steering the beam slowly, along large angles, mechanically controls the main reflector.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: November 7, 2017
    Assignee: Elbit Systems Ltd.
    Inventors: Dov Zahavi, Shaul Baruch Laufer
  • Patent number: 9806879
    Abstract: A burst mode clock data recovery device includes a clock data recovery loop, a frequency tracking loop, a frequency tracking loop, and a fast-locking unit. The clock data recovery loop receives a sampling clock signal and a data signal and uses the sampling clock signal to lock the data signal to generate a recovery clock signal. The frequency tracking loop tracks a frequency of the recovery clock signal to generate a frequency detection signal associated with the recovery clock signal. The phase lock loop receives the frequency detection signal and locks the recovery clock signal in a reference clock. The fast-locking unit generates a fast-locking signal according to the recovery clock signal and a first phase detection signal to allow the clock data recovery loop to quickly lock the data signal after the transition from a stall mode to the burst mode.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: October 31, 2017
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Lijun Gu, Ming Li, Ling Chen
  • Patent number: 9800250
    Abstract: Provided are a digitally controlled oscillator and an electronic device including the digitally controlled oscillator. The digitally controlled oscillator includes a digital control unit and a power control oscillation unit. The digital control unit compensates for a difference between a feedback signal of an output power and a reference power set based on an input digital control signal and outputting an output power. The power control oscillation unit receives a signal related to the output power, and generates an output clock having an oscillation frequency in response to the signal related to the output power.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: October 24, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Du-ho Kim
  • Patent number: 9612613
    Abstract: A method and apparatus for performing current control for an integrated circuit are described. In one embodiment the apparatus comprises core logic coupled to receive a first current; a clock generator to generate a first clock signal; and a closed loop current controller coupled to the clock generator and coupled to provide a second clock signal to the core logic based on the first clock signal, the current controller to control an amount of the first current received by the core logic by changing the first clock signal to generate the second clock signal.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: April 4, 2017
    Assignee: Intel Corporation
    Inventors: Alexander Gendler, Kosta Luria, Arye Albahari, Ohad Nachshon
  • Patent number: 9584303
    Abstract: An apparatus, comprising a first sampling circuit configured to sample a clock signal according to a data signal to produce a first sampled signal, a second sampling circuit configured to sample the clock signal according to a delay signal to produce a second sampled signal, and a control circuit coupled to the first sampling circuit and the second sampling circuit, wherein the control circuit is configured to perform a not-and (NAND) operation according to the first sampled signal and the second sampled signal to produce an activation signal for activating a frequency adjustment for the clock signal.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: February 28, 2017
    Assignee: Futurewei Technologies, Inc.
    Inventors: Liang Gu, Yuming Cao, Gong Lei, Yen Dang, Yifan Gu, Hungyi Lee, Mamatha Deshpande, Shou-Po Shih, Yan Duan
  • Patent number: 9553565
    Abstract: A method an apparatus for performing automatic frequency compensation (or control) is disclosed. A method and apparatus for performing automatic frequency compensation (or control) is disclosed. In one embodiment, a method includes a radio receiver receiving a radio signal and detecting a preamble in the radio signal. The method further includes freezing an automatic frequency compensation (AFC) loop responsive to detecting the preamble. A clock source of the AFC loop may be switched from a first clock signal to a second clock signal. The method further includes subsequently unfreezing the AFC loop.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: January 24, 2017
    Assignee: Silicon Laboratories Inc.
    Inventors: Hendricus de Ruijter, Wentao Li
  • Patent number: 9531401
    Abstract: The semiconductor integrated circuit device has: more than one analog port; an A/D conversion part operable to execute an A/D conversion process for converting an analog signal taken in through each analog port into a digital signal for each preset virtual channel; and an A/D conversion control part operable to control an action of the A/D conversion part. The A/D conversion control part includes: virtual channel registers on which correspondence between the virtual channel and the analog port can be set; and a scan-group-forming register on which a start position of a scan group and an end position thereof can be set. The A/D conversion control part controls the A/D conversion part to successively execute an A/D conversion process on a plurality of virtual channels from a virtual channel associated with the start pointer to a virtual channel associated with the end pointer.
    Type: Grant
    Filed: January 16, 2016
    Date of Patent: December 27, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Fumiki Kawakami, Naoki Yada, Hiroyuki Tsunakawa
  • Patent number: 9520881
    Abstract: A system for tuning an oscillator frequency. The system includes a trimmed calibration circuit comprising a comparator and trimmed delay element and calibration logic. The calibration logic is configured to receive an output of the comparator and control an on time and an off time of an oscillator based on the output of the comparator.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: December 13, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Abhijit Kumar Das, Krishnasawamy Nagaraj, Rahul Bhandarkar
  • Patent number: 9515603
    Abstract: A crystal oscillator start-up circuit capable of reducing a start-up time of a crystal oscillator is disclosed. The crystal oscillator start-up circuit is provided with a crystal oscillation unit including a crystal oscillator, a converter and an external oscillator. The crystal oscillation unit generates an output signal corresponding to the impedance characteristic of the crystal oscillator. The converter converts the output signal of the crystal oscillation unit to a voltage signal. The external oscillator outputs to the crystal oscillation unit an oscillation signal whose frequency is adjusted by the voltage signal to approach a resonance frequency of the crystal oscillator.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: December 6, 2016
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Yoshihiko Matsuo, Kimitoshi Niratsuka
  • Patent number: 9509322
    Abstract: An offset phase locked loop synthesizer comprising: an input; an output; a voltage controlled oscillator (VCO), the VCO output coupled to the synthesizer output; a phase frequency detector having a reference input, a feed-back input, and an output; a mixer having a first mixer input coupled to the synthesizer input and a second mixer input coupled to the VCO output; a first divider for frequency dividing a signal by a first value and having an input coupled to the mixer output and an output coupled to the second input of the phase frequency detector; a second divider for frequency dividing a signal by a second value and having an input coupled to the synthesizer input and an output coupled to the reference input of the phase frequency detector; and a low pass filter coupled between the output of the phase frequency detector and the VCO input.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: November 29, 2016
    Assignee: Nanowave Technologies Inc.
    Inventors: Walid Hamdane, Charles William Tremlett Nicholls
  • Patent number: 9484929
    Abstract: In order to develop a circuit arrangement and also a method for calibrating at least one activation signal provided for a voltage-controlled oscillator such that the expenditure of energy is as low as possible and the output frequency is as high as possible, it is proposed—that the respective number of clock cycles for at least one calibration oscillator and at least one reference oscillator associated with the calibration oscillator is counted by means of at least one clock cycle counter connected downstream of the calibration oscillator and the reference oscillator and a clock error resulting from the difference between these two numbers of clock cycles is integrated and—that the clock error is converted by means of at least one digital-to-analog converter connected downstream of the clock counter into analog tuning signals from which the calibrated activation signal is derived.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: November 1, 2016
    Assignee: Silicon Line GmbH
    Inventor: Heinz Werker
  • Patent number: 9484940
    Abstract: Techniques including methods and apparatus for calibrating a local clock are provided in an implantable medical device. The implantable medical device includes a telemetry module for receiving a remote signal transmitted by an external device. The received signal is provided to a clocking circuit having a clocking circuit for computation of a calibration factor based on a difference between phases of the clock signal generated by the local clock and transitions in the received remote signal. The calibration factor may be derived as a function of an edge of the clock signal lagging or leading relative to a corresponding edge of the remote signal.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: November 1, 2016
    Assignee: Medtronic, Inc.
    Inventor: Melvin P. Roberts
  • Patent number: 9464943
    Abstract: A temperature sensor includes a resonator; a first oscillation circuit to oscillate the resonator in a first oscillation mode; a second oscillation circuit to oscillate the resonator in a second oscillation mode different from the first oscillation mode; a switching circuit to connect the resonator to the first oscillation circuit or the second oscillation circuit; a control circuit to control the switching circuit so that the first oscillation circuit and the second oscillation circuit are alternately connected to the resonator; and a temperature information output circuit to generate information representing a frequency difference between a signal output from the first oscillation circuit kept in a status of being connected to the resonator and a signal output from the second oscillation circuit kept in the status of being connected to the resonator on the basis of these signals and to output the frequency difference information as temperature information on the resonator.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: October 11, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Masakazu Kishi, Masayuki Itoh
  • Patent number: 9374100
    Abstract: A local oscillator communicates a signal of relatively low frequency across an integrated circuit to the location of a mixer. Near the mixer, a frequency-multiplying SubHarmonically Injection-Locked Oscillator (SHILO) receives the signal and generates therefrom a higher frequency signal. If the SHILO outputs I and Q quadrature signals, then the I and Q signals drive the mixer. If the SHILO does not generate quadrature signals, then a quadrature generating circuit receives the SHILO output signal and generates therefrom I and Q signals that drive the mixer. In one advantageous aspect, the frequency of the signal communicated over distance from the local oscillator to the SHILO is lower than the frequency of the I and Q signals that drive the mixer locally. Reducing the frequency of the signal communicated over distance can reduce power consumption of the LO signal distribution system by more than fifty percent as compared to conventional systems.
    Type: Grant
    Filed: July 1, 2009
    Date of Patent: June 21, 2016
    Assignee: Qualcomm Incorporated
    Inventors: Dongmin Park, Jafar Savoj
  • Patent number: 9344094
    Abstract: In some embodiments, provided are AFC circuits and methods for calibrating a second setting of an oscillator while a first setting is controlled by a temperature compensated control.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 17, 2016
    Assignee: Intel Corporation
    Inventors: Jeffrey W. Waldrip, Yongping Fan, Jing Li
  • Patent number: 9343126
    Abstract: Clock signal generation circuitry. A frequency multiplier is coupled to receive a clock signal and to generate a frequency-multiplied clock signal. A switching circuit is coupled to receive at least two reference clock signals. The switching circuit provides one of the reference clock signals in response to a reference select signal. A phase locked loop (PLL) is coupled to receive the frequency-multiplied clock signal and the selected reference clock signal. The PLL generates an output clock signal.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: May 17, 2016
    Assignee: Intel Corporation
    Inventors: Harikrishna B. Baliga, Peter J. Smith, Joydeep Ray
  • Patent number: 9294103
    Abstract: A method and apparatus for achieving fast PLL lock when exiting a low power state is disclosed. In one embodiment, a method includes operating a PLL in a first state in which the PLL is locked to a first frequency. The method further includes programming the PLL to operate in a second state in which the PLL is locked to a second frequency. The programming may occur while the PLL is operating in the first state, and the PLL may continue operating in the first state after programming is complete. Thereafter, the PLL may be transitioned from the first state to a low power state. Upon exiting the low power state, the PLL may transition directly to the second state, locking to the second frequency, without having to transition to the first state or lock to the first frequency.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: March 22, 2016
    Assignee: Apple Inc.
    Inventors: Jong-Suk Lee, Shih-Chieh R. Wen, Toshinari Takayanagi, Wei-Han Lien
  • Patent number: 9197229
    Abstract: A ring oscillator clock automatic synchronization method of a panel driving circuit includes steps of: when a vertical blanking interval happens, a master driver generates a pulse signal to slave drivers respectively. A pulse width of the pulse signal equals to N times of a master ring oscillator clock, wherein N is larger than 0. When a slave driver receives the pulse signal, the slave driver uses its slave ring oscillator clock to count the pulse width of the pulse signal to obtain that the pulse width of the pulse signal equals to M times of the slave ring oscillator clock, wherein M is larger than 0. The slave driver compares M with N and automatically adjusts the slave ring oscillator clock according to the comparison result to make it achieve synchronization with the master ring oscillator clock.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: November 24, 2015
    Assignee: Raydium Semiconductor Corporation
    Inventors: Feng-Li Lin, Hung Li
  • Patent number: 9166775
    Abstract: A data communication system includes a unit that receives edge-encoded data from a data link. The unit includes a counter, a data bit reader, and a phase-locked loop. The counter counts at a sampling frequency between a minimum value and an end-count value. The data bit reader is connected to receive the edge-encoded data. The data bit reader samples the edge-encoded data at the sampling frequency to detect data bits of the edge-encoded data. The phase-locked loop updates the end-count value if consecutive bits of the data bits are detected prior to an expected iteration of the counter. The phase-locked loop also updates the end-count value if consecutive bits of the data bits are detected later than the expected iteration of the first counter.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: October 20, 2015
    Assignee: Hamilton Sundstrand Corporation
    Inventor: Paul J. Leblanc
  • Patent number: 9144885
    Abstract: An abrasive article can include a bonded abrasive body having abrasive particles comprising microcrystalline alumina (MCA) contained within a bond material. In an embodiment, the bonded abrasive body has a porosity of at least about 42 vol % of the total volume of the bonded abrasive body. Additionally, in an embodiment, the bonded abrasive body is capable of grinding a workpiece comprising metal at a speed of at least about 60 m/s at a material removal rate of at least about 0.4 in3/min/in (258 mm3/min/mm).
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: September 29, 2015
    Assignees: SAINT-GOBAIN ABRASIVES, INC., SAINT-GOBAIN ABRASIFS
    Inventors: Nilanjan Sarangi, Renaud Fix, Stephen Woods, Jim M. Gaffney, John Campaniello, John R. Besse, Stephen E. Fox
  • Patent number: 9083357
    Abstract: A frequency locking system for locking a clock frequency in a CDR circuit without crystal oscillator is provided. Reference data information is inputted into a first low-pass filter; the first low-pass filter is connected to a first swing detector; the first swing detector is connected to a non-inverting terminal of a comparator; an output terminal of the comparator is connected to a charge pump; the charge pump is connected to a first terminal of a capacitor; the capacitor is grounded. The capacitor is also connected to a voltage-controlled oscillator; the voltage-controlled oscillator is connected to a code pattern conversion generator; the code pattern conversion generator is connected to of a second low-pass filter; the second low-pass filter is connected to an input terminal of a second swing detector; an output terminal of the second swing detector is connected to an inverting terminal of the comparator.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: July 14, 2015
    Assignee: IPGoal Microelectronics (Sichuan) Co., Ltd.
    Inventor: Ziche Zhang
  • Publication number: 20150097626
    Abstract: A method for setting adjusting frequency of an electric oscillating circuit of a corona ignition device. The circuit is excited with a starting value (f1) of the excitation frequency and a reference value (IR) of a frequency-dependent variable is measured. The excitation frequency is incrementally changed. After every increment a value (I) of the frequency-dependent variable is measured and it is determined whether the measured value (I) deviates significantly from the reference value (IR). Depending upon the measured value (I) relative to the reference value, the value (f) of the excitation frequency is either set as the new starting value (f1) or stored as a boundary value. Further incremental changes to the excitation frequency are made in one of two directions and further comparisons of the values I and IR are performed. Ultimately, the excitation frequency can be set to a mean value between first and second boundary values.
    Type: Application
    Filed: October 6, 2014
    Publication date: April 9, 2015
    Inventors: Markus Kernwein, Torsten Schremmer
  • Patent number: 8988151
    Abstract: In one embodiment, the present invention includes a method of correcting the frequency of a crystal oscillator. The method includes establishing an operating baseline for the crystal oscillator using a frequency reference, storing information in memory, and adjusting the frequency according to the information. The information corresponds to the operating baseline. Adjusting the frequency occurs in response to a power-on event and the absence of the frequency reference.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: March 24, 2015
    Assignee: Jackson Labs Technologies Inc.
    Inventor: Gregor Said Jackson
  • Patent number: 8884671
    Abstract: A phase-locked loop system has a controlled oscillator that provides an output clock signal based on a oscillator control signal, a feedback path configured to provide a feedback signal based on the output clock signal, a phase detector configured to provide a phase dependent signal based on the feedback signal and a reference clock signal, a phase evaluation block configured to provide the oscillator control signal based on the phase dependent signal, a frequency detector that determines whether the frequency ratio between the output clock signal and the reference clock signal has a desired value, and a control logic. The control logic is configured to, during a start-up period, disable the phase evaluation block upon determination of the desired value of the frequency ratio; detect, after disabling the phase evaluation block, a subsequent clock edge of the reference clock signal; and enable, in response to the detection of the subsequent clock edge, the phase evaluation block.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: November 11, 2014
    Assignee: Synopsys, Inc.
    Inventor: Jan Grabinski
  • Patent number: 8884706
    Abstract: Embodiments of the invention include a method for use in a device having a local oscillator. The method includes performing, for the local oscillator that is disciplined by an external reference signal, while locked to the external reference signal, training at least two mathematical models of the oscillator to determine a predicted correction signal for each mathematical model based at least in part on a correction signal that is a function of the external reference signal and which is used to discipline drift in the oscillator. The method also includes selecting a mathematical model of the at least two mathematical models that results in a smallest time error when disciplining the oscillator to use when the external reference signal is unavailable and an alternative correction signal is to be used to discipline drift in the oscillator.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: November 11, 2014
    Assignee: BlackBerry Limited
    Inventors: Charles Nicholls, Philippe Wu
  • Patent number: 8847690
    Abstract: Aspects of the embodiments include a method for synchronizing a device having an oscillator to a reference signal. A correction signal can be determined based on the reference signal. A mathematical model of the oscillator can be trained based at least upon the correction signal. A predicted correction signal for the trained mathematical model can be determined. A time error using the predicted correction signal can be generated to assess suitability of the trained mathematical model for disciplining drift in the oscillator and synchronizing the device when the reference signal is not available.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 30, 2014
    Assignee: BlackBerry Limited
    Inventors: Charles Nicholls, Philippe Wu
  • Patent number: 8736394
    Abstract: To provide a reference frequency generating device that can output a highly accurate reference frequency signal even if a reference signal becomes unable to be acquired. The reference frequency generating device includes a synchronization circuit, a temperature sensor, and a controller. The synchronization circuit controls a reference frequency signal outputted from a voltage controlled oscillator, by a control signal obtained based on a reference signal. The temperature detector detects a temperature of the voltage controlled oscillator being used. When the reference signal is unable to be acquired, the controller corrects a voltage controlled signal in consideration of a distortion in the aging characteristic of the voltage controlled oscillator based on a rate of change with time in a slope of the oscillator temperature, and generates a holdover control signal based on corrected contents to control the voltage controlled oscillator.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: May 27, 2014
    Assignee: Furuno Electric Co., Ltd.
    Inventor: Shinya Kowada
  • Patent number: 8704603
    Abstract: A tunable Injection-Locked Oscillator (ILO) having a wide locking range is used in a Local Oscillator (LO) of a wideband wireless transceiver to generate differential signals. The ILO includes a resonator with an adjustable natural oscillating frequency. In one example, the ILO is part of a quadrature divider that can lock onto a Phase-Locked Loop (PLL) output signal in a wide frequency band while achieving lower power consumption and lower phase noise than a differential latch type divider. The ILO is tuned by disabling a Voltage-Controlled Oscillator (VCO) from driving the ILO, adjusting the natural oscillating frequency, making a measurement indicative of the natural oscillating frequency, and determining whether the measurement is within a predetermined range. If the measurement is below the predetermined range, capacitances of resonators within the ILO are decreased, whereas if the measurement is above the predetermined range, capacitances of the resonators are increased.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: April 22, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Mazhareddin Taghivand, Jeongsik Yang
  • Patent number: 8669817
    Abstract: A technique and corresponding circuitry are presented for a process independent, self-calibrating relaxation based clock source. The technique and circuitry presented here can reduce the time and cost needed for calibration significantly. The relaxation based clock source produces a clock signal whose frequency is dependent upon a trim value. Starting from an initial trim value, the clock signal is generated, its frequency is compared with a reference clock frequency value, and the trim value is correspondingly adjusted up or down a bit at a time. After this process has continued for a while, min-max logic is used to determine the maximum and minimum trim values and, based on these, the final trim value for the clock is set. This calibration process can also be used to extract whether, and by how much, the implementation on silicon of a particular chip lies in the fast or slow process corners.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: March 11, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Deepak Pancholi, Bhavin Odedara, Naidu Prasad, Srikanth Bojja, Srinivasa Rao Sabbineni, Jayaprakash Naradasi
  • Patent number: 8508308
    Abstract: Described embodiments provide a method of calibrating, by a calibration engine, a phase-locked loop (PLL) having one or more adjustable oscillators. The method includes entering a calibration mode of the PLL. The PLL is set to an initial state, thereby selecting one of the adjustable oscillators for calibration, an initial threshold window, and an initial tuning band of the selected adjustable oscillator. If the control signal of the selected adjustable oscillator is not within the initial threshold window, the calibration engine iteratively adjusts at least one of: (i) the selected tuning band of the selected adjustable oscillator, (ii) the selected adjustable oscillator, and (iii) the selected threshold window until the control signal of the selected adjustable oscillator is within the adjusted threshold window. If the control signal is within the threshold window, the one or more calibration settings of the PLL are stored and used to set the PLL operation.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: August 13, 2013
    Assignee: LSI Corporation
    Inventors: Yikui Jen Dong, Freeman Y. Zhong, Tai Jing, Chaitanya Palusa
  • Patent number: 8437701
    Abstract: A method and a terminal for acquiring a frequency difference are disclosed. The method includes acquiring a difference T1 between clock timing before dormancy and clock timing of a base station, recording a dormancy period T between dormancy start and dormancy end, acquiring a difference T2 between clock timing after dormancy and clock timing of the base station, and computing a frequency difference between a low speed clock and a base station clock according to normalization frequencies, T1, T, and T2.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: May 7, 2013
    Assignee: Huawei Device Co., Ltd.
    Inventor: Jianhai Shen
  • Patent number: 8432231
    Abstract: A clock system includes a digital phase/frequency detector (DPFD), a buffer, a digitally-controlled oscillator (DCO) including a sigma-delta modulator (SDM), an adder, a first frequency divider. The DPFD may have a first input for a reference input clock and a second input for a feedback signal, and outputting a difference signal representing a phase and/or frequency difference between the reference input clock and the feedback signal. The first frequency divider may have an input for a clock signal and a control input coupled to the adder. The system clock also may include a phase-locked loop (PLL) including a phase/frequency detector that has a first input coupled to the output of the DCO and a second input that is phase-locked to the first input, and a second frequency divider coupled from the second input of the PLL to the second input of the DPFD.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: April 30, 2013
    Assignee: Analog Devices, Inc.
    Inventors: Reuben Pascal Nelson, Dan Zhu
  • Patent number: 8362845
    Abstract: In one embodiment, the present invention includes a method of correcting the frequency of a crystal oscillator. The method includes establishing an operating baseline for the crystal oscillator using a frequency reference, storing information in memory, and adjusting the frequency according to the information. The information corresponds to the operating baseline. Adjusting the frequency occurs in response to a power-on event and the absence of the frequency reference.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: January 29, 2013
    Assignee: Jackson Labs Technologies Inc.
    Inventor: Gregor Said Jackson
  • Patent number: 8289057
    Abstract: A phase locked loop (PLL) which has a desired frequency characteristic even though a manufacturing process of a semiconductor integrated circuit has fluctuations. The semiconductor integrated circuit includes the PLL and a control unit. The PLL has a phase frequency detector, a loop filter, a voltage controlled oscillator (VCO) and a divider. The VCO comprises a voltage-current converter (VIC) and a ring oscillator. In response to a control voltage, the VIC generates a control current for setting each operating current of the ring oscillator. The control unit switches the PLL to a calibration operating period of its open loop and a normal operating period of its closed loop.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: October 16, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Takashi Kawamoto
  • Patent number: 8258970
    Abstract: A method of detection of the presence of a contactless communication element by a terminal emitting an electromagnetic field, in which an oscillating circuit of the terminal is excited at a frequency which is made variable between two values surrounding a nominal tuning frequency of the oscillating circuit; a signal representative of the load of the oscillating circuit being interpreted to detect that a reference voltage has not been exceeded, which indicates the presence of an element in the field. A presence-detection circuit and a corresponding terminal.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: September 4, 2012
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre Charles, Jérôme Conraux, Alexandre Malherbe, Alexandre Tramoni
  • Patent number: 8198943
    Abstract: An oscillation signal with a selectable frequency is generated with a phase locked loop (10, 12, 14). The oscillator (10) of the loop receives a feedback signal, to which an offset is added in order to reduce transient effects when a frequency modification is made. A first and second offset control value are used to control the offset successively. The first offset control value is controlled by a combination of the frequency settings before and after the modification. The second offset control value is controlled by the frequency settings after the modification. The first and second offset control values are used to control an offset of applying to a frequency control signal of an oscillator (10) of the phase locked loop (10, 12, 14). The offset controlled by the first control offset value is applied during a predetermined time interval before the offset controlled by the second control offset value is applied.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: June 12, 2012
    Assignee: NXP B.V.
    Inventors: Remco Cornelis Herman van de Beek, Jozef Reinerus Maria Bergervoet
  • Patent number: 8188796
    Abstract: A clock system includes a digital phase/frequency detector (DPFD), a buffer, a digitally-controlled oscillator (DCO) including a sigma-delta modulator (SDM), an adder, a first frequency divider. The DPFD may have a first input for a reference input clock, a second input for a feedback signal, the DPFD generating an output representing a difference between the reference input clock and the feedback signal. The buffer may be coupled to the DPFD for storing the difference signal over time. The SDM may have a control input coupled to the buffer. The adder may have inputs coupled to the SDM and a source of an integer control word. The first frequency divider may have an input for receiving an external clock signal and a control input coupled to the adder, the DCO generating an output clock signal having an average frequency representing a frequency of the external clock signal divided by (N+F/M).
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: May 29, 2012
    Assignee: Analog Devices, Inc.
    Inventors: Dan Zhu, Reuben Pascal Nelson, Timir Raithatha, Wyn Palmer, John Cavey, Ziwei Zheng
  • Patent number: 8183934
    Abstract: In a PLL circuit, a threshold discriminator generates a control signal indicating a relative level of a control voltage. A controller outputs a controlling value based on the control signal. If the control signal indicates a high level when the controlling value specifies a control voltage-to-oscillation frequency correspondence relation whose upper and lower limits of oscillation frequency are highest, and if the control signal indicates a low level when the controlling value specifies a correspondence relation whose upper and lower limits of oscillation frequency are lowest, the controller outputs a predetermined controlling value. An oscillator has the correspondence relations set therein such that the correspondence relations have respective different upper and lower limits of oscillation frequency and are correlated with the respective controlling values.
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: May 22, 2012
    Assignee: Fujitsu Limited
    Inventors: Tetsuji Yamabana, Kouichi Kanda
  • Patent number: 8154351
    Abstract: A VCO in a phase-locked loop (PLL) is arranged to receive low-pass data via a first input and high-pass data at a second input. The first input is coupled to a first set of varactors in the VCO. The second input is coupled to a second set of varactors in the VCO. The controller sets the input voltage at the first input and directs a charge pump to operate in a tri-state mode that opens the feedback loop of the PLL. The controller applies different voltages via the second input and measures the change in output frequency. A present gain of the VCO is determined from the ratio of the change in frequency and the change in voltage at the second input.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: April 10, 2012
    Assignee: Skyworks Solutions, Inc.
    Inventor: Shahrzad Tadjpour
  • Patent number: 8134392
    Abstract: A phase locked loop (PLL) which has a desired frequency characteristic even though a manufacturing process of a semiconductor integrated circuit has fluctuations. The semiconductor integrated circuit includes the PLL and a control unit. The PLL has a phase frequency detector, a loop filter, a voltage controlled oscillator (VCO) and a divider. The VCO comprises a voltage-current converter (VIC) and a ring oscillator. In response to a control voltage, the VIC generates a control current for setting each operating current of the ring oscillator. The control unit switches the PLL to a calibration operating period of its open loop and a normal operating period of its closed loop.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: March 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Takashi Kawamoto
  • Patent number: 8085099
    Abstract: A technique and corresponding circuitry are presented for a process independent, self-calibrating relaxation based clock source. The technique and circuitry presented here can reduce the time and cost needed for calibration significantly. The relaxation based clock source produces a clock signal whose frequency is dependent upon a trim value. Starting from an initial trim value, the clock signal is generated, its frequency is compared with a reference clock frequency value, and the trim value is correspondingly adjusted up or down a bit at a time. After this process has continued for a while, min-max logic is used to determine the maximum and minimum trim values and, based on these, the final trim value for the clock is set. This calibration process can also be used to extract whether, and by how much, the implementation on silicon of a particular chip lies in the fast or slow process corners.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: December 27, 2011
    Assignee: SanDisk Technologies Inc.
    Inventors: Deepak Pancholi, Bhavin Odedara, Naidu Prasad, Srikanth Bojja, Srinivasa Rao Sabbineni, Jayaprakash Naradasi