Abstract: A loop system capable of auto-calibrating an oscillating frequency range includes a frequency error detector, a voltage controlled oscillator (VCO), a voltage input unit, and a switch. The frequency error detector includes a rotational frequency detector, a state machine, and an up-down counter. The rotational frequency detector is used for comparing the reference frequency and the feedback frequency. The state machine is used for determining an auto-calibration state. The up-down counter is used for generating the second control signal or the coarse-lock-state signal. The VCO is used for selecting to operate at one of a plurality of frequency operating curves so as to generate an oscillating signal. The voltage input unit is used for providing a fixed voltage to the VCO. The switch is used for switching the VCO to couple to the voltage input unit or to couple to a fine frequency tuner.

Abstract: A phase lock loop (PLL) frequency synthesizer includes a reconfigurable voltage controlled oscillator (VCO) with three modes of operation: a Linear-High-gain, Zero-gain, and Low-gain mode. During the linear high gain mode, the VCO enables an analogue self-calibration of the PLL over a wide frequency tuning range. Control voltage at the input of the VCO is varied by the PLL to provide an output frequency. When the PLL is locked, the VCO is switched to the Zero-gain mode while maintaining the output.

Abstract: A novel apparatus for and a method of estimating, calibrating and tracking in real-time the gain of a radio frequency (RF) digitally controlled oscillator (DCO) in an all-digital phase locked loop (ADPLL). Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wideband frequency modulation that is independent of the ADPLL loop bandwidth. The gain calibration technique is based on a steepest descent iterative algorithm wherein the phase ADPLL error is sampled and correlated with the modulating data to generate a gradient. The gradient is then scaled and added to the current value of the DCO gain multiplier.

Abstract: Systems involving temperature compensation of voltage controlled oscillators are provided. In this regard, a representative system incorporates: a voltage controlled oscillator (VCO) having a tuning port and a phase-locked loop (PLL); and a temperature dependent voltage source. The VCO selectively exhibits one of a coarse tuning mode in which the temperature dependent voltage source is electrically connected to the VCO tuning port, and a locked mode in which the temperature dependent voltage source is not electrically connected to the VCO tuning port such that the PLL controls the frequency of the VCO.

Abstract: Apparatus and method for generating first, second and third carrier frequencies of 3432 MHz, 3960 MHz and 4488 MHz respectively, for use in a wireless transmission system deploy only first and second PLLs which are configured to generate 6336 MHz and 2640 MHz signals respectively with only in-phase components. Frequency dividers are employed for frequency-dividing the 6336 MHz signal severally by 2, 4, and 12 to obtain frequency-divided intermediate outputs with both in-phase and quadrature components. The intermediate output components and other intermediate signal components are selectively combined in a mixer (e.g., a single side-band mixer), for deriving the first, second and third carrier frequencies of 3432 MHz, 3960 MHz and 4488 MHz with both in-phase and quadrature components. The invention has application in UWB, WPAN, WLAN, or other wireless systems and has the simplicity and advantages of using only two PLLs instead of the prior art arrangements of three PLLs.

Abstract: An apparatus that presents an output signal that is modulated by input signal includes: (a) A signal source providing a signal at a reference frequency. (b) A frequency comparer coupled with the signal source and the output signal for comparing the extant output signal frequency with the reference frequency and generating an indicator representing the comparing. (c) Value storing units coupled with the frequency comparer to respond to an indicator and store a parameter associated with one of predetermined frequencies. (d) A selector coupled with the value storing units. (e) A signal controlled oscillator coupled with the selector. The selector responds to the input signal to couple a value storing unit with the oscillator for providing a parameter to the oscillator for effecting the modulation.

Abstract: A phase-locked loop (PLL) architecture (100) is provided that includes a voltage-controlled oscillator (VCO) (116). The PLL architecture (100) also includes a digital calibration loop (132) coupled to the VCO (116). The digital calibration loop (132) implements a digital filter (126) to provide a digital control to the VCO (116) for centering a VCO frequency output. The PLL architecture (100) also includes an analog calibration loop (130) coupled to the VCO (116). The analog calibration loop (130) provides an analog control to the VCO (116) for adjusting the centered VCO frequency output.

Abstract: A phase locked loop circuit comprises a voltage controlled oscillator with a control input to which a variable control voltage is applied and a phase-frequency discriminator with an output connected to a loop filter to produce the control voltage. To provide the phase locked loop circuit with a low loop gain and a wide frequency pulling range, a plurality of discrete capacitors is associated with the voltage controlled oscillator. A switch array selectively activates and deactivates each of the capacitors in the voltage controlled oscillator. Each number of currently activated capacitors determines one out of a plurality of partial ranges of frequencies through which the oscillator can be tuned by a variation of the control voltage in a range between predetermined upper and lower control voltage limits. A total frequency range through which the oscillator can be tuned is divided thus into a plurality of partial frequency ranges each defined by a different number of activated capacitors.

Abstract: The clock signal output device has a crystal oscillator for generating a reference clock signal and generating and outputting an output clock signal having a prescribed frequency on the basis of the reference clock signal. The device also has an atomic oscillator for generating a clock signal having higher precision than a crystal oscillator, an intermittent time management unit for intermittently driving the atomic oscillator, and a correction unit for receiving correction data for correcting the offset amount of the output clock signal on the basis of a clock signal each time the atomic oscillator is driven, and correcting the output clock signal on the basis of the correction data.

Abstract: An apparatus for generating an output signal having a particular frequency includes an oscillator, a first tuning module, and a second tuning module. The oscillator generates an output signal associated with an output frequency. When coupled to the oscillator, the first tuning module is capable of inducing, within a first amount of time, a change in the output frequency of a particular magnitude. When coupled to the oscillator, the second tuning module is capable of inducing, within a second amount of time, a change in the output frequency of the same magnitude. The second amount of time is greater than the first amount of time. The selector couples a selected one of the first tuning module and the second tuning module to the oscillator based on a difference between a frequency-divided version of the output signal and a reference signal.

Abstract: A signal generating apparatus is disclosed for generating a synthesized signal according to an input signal, the signal generating apparatus includes a phase-locked loop device for generating the synthesized signal; a control unit for controlling the control signal generator to adjust the control signal in a calibration mode to thereby adjust a frequency of the synthesized signal, wherein the phase/frequency detector does not output the detected signal to the control signal generator in the calibration mode; a detecting device for detecting the synthesized signal to generate a calibrating signal in the calibration mode; a filtering device for filtering the input signal and calibrating the input signal according to the calibrating signal to generate a filtered signal; and a modulating device for modulating the filtered signal to generate the dividing factor.

Abstract: A receiver circuit includes an oscillator circuit configured to generate a calibration tone and a phase locked loop (PLL) reference signal. An output frequency of the VCO may be divided by respective amounts to derive a desired calibration tone frequency and a desired PLL reference signal frequency. In addition to the oscillator circuit, the receiver circuit may further include a phase locked circuit configured to generate a PLL output signal that is phase locked in relation to the PLL reference signal. During a calibration mode, a quadrature generator may be used to generate quadrature mixer local oscillator signals dependent upon the PLL output signal, and an in-phase/quadrature mixer may be used to mix the calibration tone with the quadrature mixer LO signals.

Abstract: A PLL includes a charge pump, a loop filter, a VCO, and a calibration unit. The calibration unit performs coarse tuning to select one or multiple frequency ranges, performs fine tuning to determine an initial control voltage that puts the VCO near a desired operating frequency, measures the VCO gain at different control voltages, and derives VCO gain compensation values for the different control voltages. The calibration unit also pre-charges the loop filter to the initial control voltage to shorten acquisition time, enables the loop filter to drive the VCO to lock to the desired operating frequency, and performs VCO gain compensation during normal operation. For VCO gain compensation, the calibration unit measures the control voltage, obtains the VCO gain compensation value for the measured control voltage, and adjusts the gain of at least one circuit block (e.g., the charge pump) to account for variation in the VCO gain.

Abstract: In various embodiments, the invention provides a clock generator and/or a timing and frequency reference, with multiple operating modes, such power conservation, clock, reference, and pulsed modes. The various apparatus embodiments include a resonator adapted to provide a first signal having a resonant frequency; an amplifier; a temperature compensator adapted to modify the resonant frequency in response to temperature; and a process variation compensator adapted to modify the resonant frequency in response to fabrication process variation. In addition, the various embodiments may also include a frequency divider adapted to divide the first signal having the resonant frequency into a plurality of second signals having a corresponding plurality of frequencies substantially equal to or lower than the resonant frequency; and a frequency selector adapted to provide an output signal from the plurality of second signals.

Abstract: A phase locked loop includes a controlled oscillator for delivering an output signal at a determined output frequency, and a variable frequency divider for converting the output signal into a signal at divided frequency. The PLL is termed composite in that it includes at least one first loop having a loop filter for generating a first control signal for the oscillator on the basis of the signal at divided frequency, and a second loop having a loop filter, different from the loop filter of the first loop, for generating, on the basis of the signal at divided frequency, a second signal for additional control of the oscillator. The loop filter of the first loop and the loop filter of the second loop have different respective cutoff frequencies. The passband of the first loop, can be adapted to ensure the convergence and the stability of the PLL, while the second loop can afford extra passband increasing the speed of adaptation of the PLL in case of modification of the value of a preset for the output frequency.

Abstract: A Phase-Locked Loop (PPL) circuit includes a voltage controlled oscillator (VCO), a reference signal oscillator, first and second frequency dividers, a phase comparator, a charge pump and a loop filter. The VCO has a plural number of oscillation frequency boards and oscillates according to a control voltage in a selected band. The first frequency divider frequency divides the output signal of the VCO. The second frequency divider frequency divides the reference signal outputted from the reference signal oscillator. The phase comparator detects the phase difference between the output signal of the first and second frequency dividers and outputs a phase difference signal. The charge pump inputs and outputs a current generated by a gain that was set depending on the selected band based on the phase difference signal. The loop filter increases or decreases the voltage with a specified low pass filter.

Abstract: A semiconductor integrated circuit with a PLL (Phase Locked Loop) built therein is used in a semiconductor integrated circuit for wireless communication. The PLL circuit generates an oscillation signal having a predetermined frequency, which is combined with a receive signal or a transmit signal for wireless communication. The PLL circuit includes a VCO capable of switching an oscillation frequency band, a variable divider, a loop filter and a phase comparator. An oscillation frequency of the VCO is controlled according to the difference in phase between a signal obtained by dividing the output of the VCO and a reference signal, and a discrimination circuit makes a decision as to a lead or delay of the phase of an output of the variable divider with respect to a reference signal having a predetermined frequency. An auto band selection circuit generates a signal for selecting a frequency band for the VCO.

Abstract: A phase lock loop and the control method thereof. The phase lock loop adjusts operating states automatically to generate a feedback clock for tracing a reference clock. The control method generates the first and second clocks corresponding to the highest and lowest frequency oscillating clocks respectively generated by the phase lock loop when operating in one of select states. The frequencies of the first and second clocks are compared to the frequency of the reference clock respectively, thereby holding the select state of the phase lock loop when the first, second, and reference clocks are in a first predetermined condition or changing the select state of the phase lock loop when in a second predetermined condition.

Abstract: In one embodiment, a phase-locked loop system in a receiver samples received incoming data using a first clock and a second clock that have the same frequency but are out of phase with each other. A first control signal generated by a phase detector is used to control a charge pump, whose output may be filtered to drive a VCO circuit generating the first and second clocks. A frequency detector generates a second control signal based at least on phase relationships between the incoming data and the first and second clocks. A qualifier circuit determines if the first control signal is valid or invalid based at least on the second control signal. If the first control signal is invalid, the qualifier circuit prevents the first control signal from being used to adjust the frequency of the first and second clocks.

Abstract: A system and method for configuring a phased-lock loop (PLL) dividing ratio which does not require the phased-lock loop circuit to lock. In one embodiment, the method includes inducing a substantially minimum or a substantially maximum frequency output from a voltage-controlled oscillator (VCO), and configuring a divider with a corresponding dividing ratio. The method may include grounding an input voltage to the VCO. Alternately, the method may include manipulating inputs to a charge pump providing input to the VCO. The charge pump inputs may be manipulated directly or through a phase-frequency detector providing input to the charge pump and adapted to receive additional input signals.

Abstract: Disclosed is a PLL circuit having a voltage-controlled oscillator, to which a difference voltage across non-inverting and inverting input terminals is input as a control voltage, for oscillating at a frequency in accordance with the control voltage; a phase comparator for comparing the phase of an output signal obtained by frequency-dividing the output of the voltage-controlled oscillator by a frequency-divider, with the phase of an input signal and outputting the result of this phase comparison; first and second loop filters connected at output terminals thereof to the non-inverting and inverting input terminals, respectively, of the voltage-controlled oscillator; and a charge pump, which is responsive to receipt of an UP signal supplied from the phase comparator, for supplying a first charging current from a PMOS transistor to a capacitor of the first loop filter and supplying a first discharge current from an NMOS transistor to a capacitor of the second loop filter, and which is responsive to receipt of a

Abstract: A precharge circuit that initializes an electronic filter to a middle voltage level of an operational voltage includes a filter isolation device, a filter communication device, and an initializing device. The filter isolation device isolates the electronic filter from electronic circuits connected to an input and an output of the electronic filter to segregate the electronic filter from the electronic circuits connected to the input and the output of the electronic filter during a precharge time. The filter communication device allows communication between the precharge circuit and the electronic filter for initializing the charge state during the precharge time. The initializing device provides an initializing signal to the charge state of the electronic filter during the precharge time. The precharge circuit further has a biasing device in communication with the initializing device to provide a mid level control signal providing a reference level of the charge state.

Abstract: A phase-locked loop (PLL) locks onto an input signal to provide an output signal that is proportional in frequency to the input signal. The PLL also detects whether an input signal's frequency falls outside a predetermined range and, whenever the input signal's frequency falls outside of range, the PLL provides a stable output signal at a predetermined frequency. While the PLL is providing a stable output signal in this manner it also monitors the input signal to determine whether the input signal's frequency has returned to within a re-qualification frequency range. If the input signal's frequency does fall within the re-qualification range, the PLL proceeds to lock onto the input signal.

Abstract: A novel apparatus for and a method of estimating, calibrating and tracking in real-time the gain of a radio frequency (RF) digitally controlled oscillator (DCO) in an all-digital phase locked loop (ADPLL). Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wideband frequency modulation that is independent of the ADPLL loop bandwidth. The gain calibration technique is based on a steepest descent iterative algorithm wherein the phase ADPLL error is sampled and correlated with the modulating data to generate a gradient. The gradient is then scaled and added to the current value of the DCO gain multiplier.

Abstract: An offset related to a feedback system for a VCO is quantified and then a parameter of the feedback system is adjusted in response to the quantified offset to correct for the offset. Correcting for offset in a feedback system can improve the performance of a PLL by reducing phase drift between the input signal and the VCO signal. The reduced phase drift can have benefits such as, for example, reduced bit errors and/or improved phase tracking accuracy.

Abstract: Several open-loop calibration techniques for phase-locked-loop circuits (PLL) that provide a process, temperature and divider modulus independence for the loop bandwidth and damping factor are disclosed. Two categories of open-loop techniques are presented. The first method uses only a single measurement of the output frequency from the oscillator and adjusts a single PLL loop element that performs a simultaneous calibration of both the loop bandwidth and damping factor. The output frequency is measured for a given value of the oscillator control signal and the charge-pump current is adjusted such that it cancels the process variation of the oscillator gain. The second method uses two separate and orthogonal calibration steps, both of them based on the measurement of the output frequency from the oscillator when a known excitation is applied to the open loop signal path.

Abstract: A variable frequency synthesizer comprising a sigma-delta modulator is provided. Such synthesizers provide an exact average frequency whereas the instantaneous frequencies varies. The sigma-delta modulator comprises a plurality of accumulator stages being connected in cascade. At least one input value of an accumulator (51, 52, 53, 54) being part of the sigma-delta modulator has a second component which is equal to an overflow signal (of1, of2, of3, of4) multiplied by a factor. This feedback reduces the-maximum fluctuation of the instantaneous frequencies. Phase jitter generated by non-linearities of the phase detector, the charge pump and the VCO is therefore reduced.

Abstract: At a first step, in a synchronous clock generation circuit, the number of delay stages serving as a digital PLL circuit is increased/decreased, and an oscillation circuit performs an oscillation operation when an optimal number of delay stages is set. Thereafter, in an operation at a second step, a control voltage is controlled with the optimal number of delay stages being set for serving as an analog PLL circuit, thereby attaining a lock-in state. As the lock-in state is finally maintained under analog control, an excellent jitter characteristic can be obtained. Thus, ensuring a lock-in range that has been a problem in the analog PLL circuit is solved by varying the number of delay stages in the operation at the first step, and a high jitter characteristic that has been a problem in a digital PLL circuit can be solved by analog control in the operation at the second step.

Abstract: Disclosed is method of controlling an asymmetric waveform generator including the steps of providing a reference timer signal, and generating an asymmetric waveform as a combination of a first sinusoidal wave having a first frequency and a second sinusoidal wave having a second frequency approximately twice the first frequency. The generated asymmetric waveform is sampled to obtain a set of data points, which set of data points is indicative of the generated asymmetric waveform. The method includes analyzing the set of data points in terms of at least a first function relating to an ideal sinusoidal wave of the first frequency, to determine a first set of resultant values relating to the first sinusoidal wave, and analyzing the set of data points in terms of at least a second function relating to an ideal sinusoidal wave of the second frequency, to determine a second set of resultant values relating to the second sinusoidal wave.

Abstract: An FM transmitter that can control start/idle of each of such devices as a buffer amplifier without using a sample-and-hold circuit for moving a PLL into open loop control, wherein a controller that controls a charging pump in the PLL to start/idle the FM modulation is controlled with use of a closed/open loop select signal of the PLL, a start/idle signal of the buffer amplifier, and a preamble detection signal. The power consumption of the FM transmission can be reduced, since both the buffer amplifier and the PLL in the FM transmitter can be started/idled together in a ganged manner.

Abstract: A system or method for controlling a voltage controlled oscillator (VCO) or LO buffer includes an amplitude detector for detecting an amplitude value at a node corresponding to the at least one output line. A comparator compares the detected amplitude value with a predetermined amplitude value, and outputs a first digital value when the detected amplitude value is greater than the predetermined amplitude value, and a second digital value when the detected amplitude value is less than the predetermined amplitude value. An accumulator accumulates outputs of the comparator so as to provide an accumulated digital amplitude value. A digital-to-analog converter converts the accumulated digital amplitude value to an accumulated analog amplitude value. The analog accumulated amplitude value is provided as an updated bias control signal to the bias transistor of the VCO or LO buffer.

Abstract: A frequency detecting circuit 10 detects frequency of a sampling pulse SP, and outputs the detected frequency as a detection value VOUT. A current adjusting circuit 20 adjusts a power supply current Ivd to be supplied to an AD converter 30 in accordance with the detection value VOUT. The power supply current Ivd varies continuously so as to follow the sampling frequency. As a result, an optimum power supply current Ivd can always be supplied in accordance with the operating frequency of the AD converter 30. That is, power consumption of the AD converter 30 can be reduced. Since the power supply current Ivd can be adjusted in accordance with the sampling frequency, it is possible to form the AD converter 30 that has a wide frequency band and allows great versatility.

Abstract: A method for calibrating a phase locked loop begins by determining a gain offset of a voltage controlled oscillator of the phase locked loop. The processing then continues by adjusting current of a charge pump of the phase locked loop based on the gain offset.

Abstract: In one embodiment, the present invention provides a system including a varactor and a voltage generator. The varactor includes a set of substantially equal voltage-tunable capacitor cells, each having a capacitive range that varies with a first plurality of operating parameters and each providing a capacitance within the range based on a voltage level of a reference voltage. The voltage generator is configured to provide the reference voltage, wherein the voltage level of the reference voltage corresponds to a desired capacitance within the capacitive range and varies based on a second plurality of operating parameters which are substantially the same as the first plurality of operating parameters, and wherein the voltage level of the reference voltage causes each capacitor cell to provide the desired capacitance.

Abstract: A rubidium frequency standard control circuit which utilizes an initial sweep hand-off frequency locking process followed by a negative feedback loop for optimization of the stability of the voltage control oscillator employing the rubidium frequency standard.

Abstract: A phase-locked loop including an oscillator, controlled by a control signal generated by a comparison circuit comparing a reference frequency and the oscillator frequency and filtered by an integrator low-pass filter; a control and adjustment circuit for, with a predetermined frequency smaller than the reference frequency, taking into account the value of the filtered controlled signal and, if this value is out of a range of predetermined values, adjusting the operating range of the oscillator; and an inhibition circuit for deactivating the comparison circuit for a predetermined duration before taking into account the value of the filtered control signal.

Abstract: An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, the controller sinks current from a control node connected to a loop filter of the phase-locked loop. This, in turn, causes a bias voltage to increase until the phase-locked loop transitions from startup mode to a normal acquisition mode. The current sink is provided by a dummy charge pump and the startup condition is determined by detecting the end of a PLL disable state. If a yank condition is detected, a charge pump connected to a phase-frequency detector of the phase-locked loop controls the bias voltage until a feedback frequency becomes lower than a reference frequency. Methods for controlling a phase-locked loop during both modes of operation may use of the aforementioned apparatus.

Abstract: A clock recovery circuit capable of automatically adjusting the frequency range of a voltage-controlled oscillator (VCO). The clock recovery circuit includes a phase detector, a charge pump, a loop filter, a voltage-controlled oscillator, a frequency counter, and a frequency control unit. The phase detector receives an input signal, such as EFM clock, and a VCO clock and outputs a control signal according to phase differences between the EFM clock and the VCO clock. The charge pump controls the charge action according to the control signal. The loop filter is connected to the charge pump and outputs a voltage signal. The voltage-controlled oscillator receives the voltage signal from the loop filter and outputs the VCO clock. The frequency counter counts the frequency of the VCO clock and outputs an oscillation frequency.

Abstract: The frequency synthesizer circuit includes a phase-locked loop (PLL) circuit, a voltage controlled oscillator (VCO), a low pass filter (LPF), an input terminal for providing serial data provided from the exterior to the PLL circuit, an output terminal for providing an oscillation signal provided the VCO, and a testing unit providing a testing voltage with a binary value to the VCO, wherein, the PLL circuit, the VCO, the LPF, and the testing unit are mounted on a single chip, and usability of the frequency synthesizer circuit is determined based on the oscillation signal provided from the VCO via said output terminal according to the testing voltage with a binary value provided from said testing unit.

Abstract: A phase locked loop frequency (PLL) synthesizer in which the scaled output of a reference oscillator(24) is compared with the scaled output of a voltage controlled oscillator(VCO)(10) in a comparator(22) to provide an error voltage which is integrated to form a frequency control voltage for the VCO. When the VCO has stabilized, the PLL is interrupted by the opening of a switch(32) in the output circuit of the comparator(22) and de-energizing the reference oscillator(24), scalers(18,26) and the comparator(22). A capacitor(36) which has been charged by the frequency control voltage maintains the output frequency of the VCO. Periodically the de-energized stages are re-energized and the switch(32) is closed to restore the PLL thereby enabling the VCO(10) to stabilize again after which the cycle of operations is repeated. A technique is disclosed for avoiding a jump in the VCO frequency when the switch(32) is closed.

Abstract: A technique for generating carrier frequencies with fast hopping capability associated with multiband systems for ultra wideband applications. The technique employs a single VCO 20 that is locked in a PLL 30. The output of this VCO 20 is divided in the frequency domain. The divided frequencies thus obtained are combined in a single-sideband manner to obtain various other frequencies. The single-sideband combination requires open loop operations such as multiplication and addition or subtraction to implement, and hence is very fast. The VCO center frequency is not disturbed in the process. Since the required frequencies are generated in an open-loop fashion, instead of inside a PLL, the speed is increased by orders of magnitude.

Abstract: A PLL-controlled oscillator that can be suitably used for such purposes as a jitter filter in an optical transmission system includes an input voltage-switching control oscillator as a voltage-controlled oscillator (VCO). The input voltage-switching control oscillator includes: an oscillation closed loop that is provided with a variable-voltage capacitance element; and a switch for interchangeably selecting one of a plurality of voltages in accordance with a selection signal and applying the selected voltage as a control voltage to the variable-voltage capacitance element.

Abstract: Circuits and methods for tuning voltage-controlled oscillators. A control voltage is applied through an isolation resistor to a varactor. The varactor capacitance is AC coupled through a second capacitance. The control voltage may be analog or digital. In a specific embodiment, multiple tuning diodes, and both analog and digital control voltages are used. The isolation resistor is outside the VCO tank circuit for low phase noise, excessive Kvco is reduced, and the control and output voltages of the oscillator may swing over the entire supply range. The varactor capacitance may be junction, MOS, or other type of varactor.

Abstract: A system for coarsely tuning at least one voltage controlled oscillator (VCO) (211) in a phase locked loop (PLL) synthesizer (200) that includes a phase-frequency detector (PFD) for determining a phase difference between a VCO frequency and a reference frequency and providing an error signal if the VCO frequency and reference frequency are at least 2&pgr; radians out of phase. A monitor (215) is then used for tracking the number of error signals produced by the PFD. The free running frequency of the VCO may be coarsely tuned in the event the monitor circuit reaches some predetermined level. The invention offers great advantage in enabling a PLL to be coarsely tuned to enable the PLL's VCO to remain with an operational range despite operational factors that effect circuit operation.

Abstract: A timer circuit having an oscillator circuit that has low power consumption and a stable frequency of the output signal. Timer circuit 10 has highly stable oscillator 21, counter 22 and frequency dividing value controller 24. Highly stable oscillator 21 generates a standard signal at a prescribed frequency. Counter 22 determines the frequency ratio of the frequency of the internal signal to the frequency of the standard signal, and, corresponding to the frequency ratio, frequency dividing value controller 24 changes the frequency dividing value of frequency divider 12. Because the difference between the frequency of the internal signal and the frequency of the standard signal can be known from the frequency ratio, it is possible to perform control such that the frequency of the output signal is kept stable at a prescribed frequency.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a plurality of output clock signals and a first control signal in response to a reference clock signal and a feedback signal. The second circuit may be configured to select one of the plurality of output clock signals as the feedback signal in response to the first control signal.

Abstract: A tuning circuit for use in tuning multiple voltage-controlled oscillators (VCOs) of a phase-locked loop (PLL) is provided. A search algorithm is used to determine which VCO to use for a given frequency to be synthesized by the PLL. The tuning circuit provides a binary representation, associated with the frequency to synthesize, to the PLL. The PLL responds to this representation by attempting to synthesize the associated frequency. New binary representations are provided until an indication of a threshold frequency between multiple VCOs is determined. A record of the threshold frequency is stored. The binary representation of a frequency to be synthesized and the stored record of the threshold frequency are used to provide an indication of which VCO of the PLL to use to synthesize the desired frequency.

Abstract: A phase-locked loop (PLL) 1 is provided with means for changing the frequency of the output signal to a desired frequency. The PLL 1 is operated during a first period with a feedback frequency division ratio set to an initial value N′ which controls the conduction time of the charge pumps during a first period having a predetermined length to place an amount of charge on the loop filter 6 during the first period sufficient to produce a control voltage for controlling the voltage-controlled oscillator 10 to output an output signal substantially at the desired output frequency. At the end of the first period, the feedback loop 11 is opened by disabling the charge pump 5 for a second period to allow the control voltage output from the loop filter 6 to settle. Subsequently the feedback loop 6 is closed and the feedback frequency division ratio is set to a proper value N2 such that operation of the PLL 1 subsequent to the second period locks the output frequency to the desired frequency.

Abstract: A post-silicon technique for adjusting a current of a charge pump in a phase locked loop is provided. The technique involves use of an adjustment circuit operatively connected to the charge pump, where the adjustment circuit is controllable to facilitate an internal biasing of the charge pump. Such control of the charge pump current in a phase locked loop allows a designer to achieve desired PLL performance characteristics after the PLL has been fabricated.

Abstract: A phase lock loop to control phase error from a first input signal and a second input signal including a phase error detector to detect a phase error signal between the first input signal and the second input signal at a predetermined rate, a down-sampling circuit to down-sample the phase error signal and to output a down-sampled signal at a reduced rate with respect to the predetermined rate, a loop filter to filter the down-sampled signal to obtain a filtered signal, and an up-sampling circuit to up-sample the filtered signal at the predetermined rate.