Abstract: A frequency synthesizer includes first and second frequency dividers for receiving and frequency-dividing a signal generated by a voltage-controlled oscillator, a frequency mixer for mixing output signals of the first and second frequency dividers, and a third frequency divider for receiving and frequency-dividing a signal having one frequency of two frequencies that are output by the frequency mixer. The first, second third and frequency dividers and the frequency mixer are provided in a feedback loop within a PLL circuit between the voltage-controlled oscillator and the phase comparator. The phase comparator has a first input terminal to which a signal to which a signal that is output by the third frequency divider is input and a second input terminal to which a reference clock signal that is output by a reference signal generator is input. A loop filter supplies the voltage-controlled oscillator with a voltage that is based upon result of the phase comparison by a phase comparator.

Abstract: A local oscillation generator (LO-GEN) maintains a fixed bandwidth using a gain calibration module that compensates for variations in the voltage controlled oscillation (VCO) gain based on the oscillation frequency. During an open loop calibration of the LO-GEN, the gain calibration module adjusts the charge pump current to compensate for the VCO gain changes.

Abstract: Phase-locked loop circuitry includes charge pump circuitry, loop filter circuitry, and drag current circuitry. The charge pump circuitry generates a charge pump current based on a phase of an input signal. The loop filter circuitry receives the charge pump current. The drag current circuitry generates a drag current to draw charge in the opposite direction from the charging current from a loop filter integration capacitor in the loop filter circuitry that does not include voltage sensing circuitry.

Abstract: A synthesizer comprises a detector for detecting a parameter difference, a voltage controlled oscillator, at least one capacitor having one end connected to a node between the detector and the voltage controlled oscillator and means connected to an other end of the at least one capacitor for providing an electrical response in dependence on the detected parameter difference.

Abstract: A phase lock loop device further includes a probability shaping device provided between a phase detection device and charge pump and loop filter (CPLF) device. The probability shaping device operates to reduce the frequency of outputting up-index or down-index; thereby shaping probability distribution to reduce degradation due to mismatching of the CPLF device.

Abstract: Systems, methods and media for a fast locking phase locked loop (FLPLL) are disclosed. A FLPLL apparatus can include a voltage controlled oscillator (VCO) coupled to a phase frequency detector and can also include a frequency divider as part of a feedback loop. The VCO can accept a pull up voltage and a control signal from the phase frequency detector and provide an output clock signal to circuits that need synchronization. Such a configuration can greatly reduce the time the PLL requires to go from a dormant state to a fully operational state. During this start up mode, a frequency detection module can be utilized to detect an output frequency of the voltage controlled oscillator and when the VCO output frequency is not as high as a reference frequency, the frequency detection module can disabled the feedback loop during this start-up mode.

Abstract: A PLL system for generating an output signal according to a first reference signal is disclosed. The PLL system includes a clock generator to generate the output signal according to a phase difference between the first reference signal and the frequency-divided signal; and a phase-shift detector for detecting a position difference between the physical address and an updated logical address of the recording data to generate a phase adjusting signal. The PLL system also includes an adder for updating a detected logical address with a random value to output the updated logical address to the position difference detector; and a phase-controllable frequency divider for generating the frequency-divided signal and for receiving the phase adjusting signal to adjust the phase of the frequency-divided signal.

Abstract: In a DPLL circuit, when the size of a data value which is output from a data latch circuit and should be naturally set in a 11-bit down-counter becomes equal to or more than 12 bits, an overflow preventing circuit substitutes the 11-bit data for the data value.

Abstract: Generating an output signal having a frequency of 1/(M+F) of the frequency of the input signal, wherein M represents an integer and F represents a non-zero fraction. Assuming F equals (Q/R) in one embodiment, wherein Q and R are integers, R intermediate signals phase shifted by equal degree (relative to the one with closest phase shift) in one clock period of the input signal are generated. A selection circuit may select one of the intermediate signals in one clock cycle, select the successive signals with increasing phase shift in Q clock cycles, and leave the intermediate signal with the same shift as in the previous clock cycle in the remaining ones of the M clock cycles. A counter counts a change of state in the output of the selection circuit, and generates a pulse representing an edge of the output signal at the time instance when counter counts M.

Abstract: A voltage-controlled oscillator (VCO) according to an aspect of the present invention includes an oscillation unit and a delay time control unit. The oscillation unit generates an oscillation signal with a frequency determined by a VCO control signal. The delay time control unit adjusts a delay of the oscillation signal in response to a change of a power supply voltage. Such a VCO is advantageously used for minimizing signal skew in a phase-locked loop (PLL).

Abstract: The PLL circuit of the present invention includes a voltage-controlled oscillator, a loop filter, and a charge pump which controls a voltage of the loop filter while the voltage-controlled oscillator is not oscillating. Therefore, it is possible, even while the voltage-controlled oscillator is not oscillating, to control a voltage for the charge pump so that it is equal to a voltage when the voltage-controlled oscillator is oscillating at a predetermined frequency. Accordingly, by the loop filter outputting a voltage signal to the voltage-controlled oscillator when the PLL circuit is turned on, the pull-in time can be shortened.

Abstract: An all digital phase lock loop is disclosed, including a digitally controlled oscillator, a phase detector, and a loop filter. The digitally controlled oscillator is controlled by an oscillator tuning word to generate a variable signal. The oscillator tuning word includes a first tuning word and a second tuning word, where the frequency range of the digitally controlled oscillator, capable to be adjusted by the second tuning word, is broader than that capable to be adjusted by the first tuning word. The phase detector detects a phase error between the variable signal and a reference signal. The phase error is received by the loop filter to output the oscillator tuning word. The loop filter has several stages of the low pass filters and a modification circuit. The modification circuit detects two filter outputs from two low pass filters among the filters and accordingly adjusts the second tuning word.

Abstract: A PLL circuit for two point modulation includes a first loop filter, a second loop filter, a plurality of switching devices, and a calibration module. The first loop filter filters an output voltage of a charge pump during a gain calibration operation. The second loop filter filters the output voltage of the charge pump during a normal operation. The first loop filter has a bandwidth wider than that of the second loop filter to perform a fast calibration by reducing a lock time. The operation of the first loop filter, the operation of the second loop filter, and the opening of the first loop filter are determined by the switching operations of the switching devices. The calibration module adjusts a gain of analog modulation data based on a frequency error accumulated in the first loop filter after the first loop filter is open during the gain calibration operation.

Abstract: A system and method of operating a phase-locked loop frequency synthesizer is disclosed herein. The disclosed method includes defining a first set of operating parameters applicable to operation of a phase-locked loop of the synthesizer in a first mode and defining a second set of operating parameters applicable to operation of the phase-locked loop in a second mode. A first detection signal is generated so as to initiate transition of the phase-locked loop into the second mode. The method further includes configuring, at least in part in response to the first detection signal, the phase-locked loop to operate in accordance with the second set of operating parameters.

Abstract: A system and a method for self calibrating a voltage-controlled oscillator (VCO). In the system, a mode controller generates a control signal for each of an automatic band selection mode, an automatic gain tuning mode, and a phase-locking mode, from a frequency comparison result between a reference clock signal and a divided clock signal which is generated by dividing a frequency of an oscillation signal, and thereby controls the VCO, so that the VCO may generate the oscillation signal which is automatically phase-locked in a target frequency with an optimal state.

Abstract: A phase locked loop circuit includes a voltage controlled oscillator having an oscillating characteristic value changed by a switching signal. A characteristic controller supplies the switching signal to the voltage controlled oscillator to increase the oscillating characteristic value according to elapse of time. The voltage controlled oscillator oscillates according to both of the oscillating characteristic value and a frequency control signal. Even if the frequency control signal is equal to a power source level at the beginning of supplying electric power, the phase locked loop can be locked in a target frequency.

Abstract: A fractional frequency synthesizer, applied to a phase-locked loop, includes a phase detector, a loop filter, a controllable oscillator, a first frequency divider, and a sigma-delta modulator (SDM). The phase detector generates a phase difference signal according to a reference signal and a feedback signal. The loop filter filters the phase difference signal to generate a filtered signal. The controllable oscillator generates the frequency signal according to the filtered signal. The first frequency divider generates the feedback signal by dividing a frequency of the frequency signal according to a dividing factor. The SDM determines the dividing factor according to a control signal.

Abstract: A phase-locked loop (PLL) achieves initial lock using a course fractional-N divider driving a binary phase detector. Once frequency lock is achieved, this divider may be turned off, while an adaptive phase detector takes over control of the PLL front end. The adaptive phase detector (APD) receives input directly from the VCO and the reference clock, deriving digital control signals and a precision phase detector output. The APD operates at the update rate, generating a digital delta sigma modulator (DSM) data stream output at the update rate. The APD automatically locks to a digitally generated ramp corresponding to an expected difference between the VCO output and the reference clock, while adaptively correcting for DC errors and ramp cancellation errors.

Abstract: Systems and methods for enabling the determination of voltage controlled oscillator (VCO) linearity, duty cycle determination and duty cycle correction in phase locked loop circuits (PLL's.) One embodiment comprises a method including the steps of determining the frequency response of a PLL's VCO as a function of duty cycle, applying a signal based on the VCO output to the VCO input, measuring the resulting frequency of the VCO output signal, determining the duty cycle corresponding to the measured frequency, and configuring a duty cycle correction unit correct the duty cycle of the VCO output signal to about 50%. Determining the frequency response of the VCO may include, for each of several different duty cycle values between 0% and 100%, applying the VCO input signal to the VCO and determining the corresponding frequency of the VCO output signal. This may also be done for duty cycles of 0% and 100%.

Abstract: A low cost, low phase noise microwave synthesizer includes a DDS modulation circuit and a phase-locked loop. The DDS modulation circuit modulates the output of a DDS to a high frequency. The phase-locked loop downconverts the DDS output and locks the downconverted signal to a relatively low frequency, fixed reference.

Abstract: A nonlinearity-compensated section has a pre-set compensation table containing a measured value of a voltage vtc, outputted from a loop filter, which is changed accordingly with respect to a change in a voltage vtfc outputted from a frequency controlling section. The nonlinearity-compensated section sets, in the compensation table, the voltage vtfc of an oscillatory frequency oscillated by a VCO and the voltage vtc associated therewith as reference voltages, and creates a look-up table containing voltage differences obtained by subtracting the above-described reference voltages from the voltages vtfc and vtc, respectively. Thereafter, the nonlinearity-compensated section extracts a compensation value corresponding to the voltage vtc actually outputted from the loop filter by means of the look-up table, and adds the compensation value to an input modulated signal adjusted by a multiplier so as to be outputted.

Abstract: Correction of glitches output from a delta-sigma modulator is accomplished using an integer boundary crossing detector and a FIR filter. The detector monitors a portion of an input to the modulator. The detector recognizes a transition from an all 1's bit pattern to an all 0's bit pattern or vice versa as representative of potential for a glitch to be present on the output of the modulator. The detector responsively generates condition detection output. Receipt of such condition detection output triggers the generation of a correction signal by the filter. The correction signal is, at least substantially similar, in magnitude but opposite in sign from to the expected glitch at the output of the modulator. The correction signal is added to the output of the modulator to substantially eliminate the glitch.

Abstract: An auto-adjusting high accuracy oscillator is disclosed, which comprises: a frequency comparator, for comparing a synchronization signal obtained from a USB host with an oscillation signal obtain from a device; a control tuning circuit, further comprising a counter and an adder/sub circuit; and an oscillating element; wherein a variation is obtained by the counting of the counter while transmitting the variation to the adder/sub circuit to be encoded thereby into a digital code so as to enable the oscillating element to perform a frequency up/down operation accordingly for approaching the synchronization signal successively.

Abstract: A voltage control oscillator is provided in which a resistance voltage dividing circuit is formed by a switching element so as to arbitrarily change a gain and a reference value of a control voltage, an IC chip area is reduced, and reduction of a noise of an AFC voltage and improvement of C/N are realized. This voltage control oscillator 100 is provided with a reference bias voltage generating means 20 generating a reference bias voltage by adjusting a reference voltage; a gain adjustment circuit 21 adjusting a gain of a control voltage; and an oscillation circuit 22. The reference bias voltage generating means 20 includes resistances Rd, Re, Rf, Rg connecting between VREF and a ground in series; and switches SW_AR1, SW_AR2 respectively coupling to the resistance Rd and the resistance Re in parallel. The gain adjustment circuit 21 includes three resistances Ra, Rb, Rc; switches SW1 to SW6; and inverters INV1, INV2.

Abstract: A broadband integrated receiver for receiving input signals and outputting composite video and audio signals is disclosed. The receiver employs an up-conversion mixer and a down-conversion mixer in series to produce an intermediate signal. An intermediate filter between the mixers performs coarse channel selection. The down-conversion mixer may be an image rejection mixer to provide additional filtering.

Abstract: A system and a method for operating the same. The system includes a fractional-N phase-locked loop (PLL). The PLL includes a PLL input and a PLL output. The fractional-N PLL further includes a multiplexer. The multiplexer includes a multiplexer output electrically coupled to the PLL input. The multiplexer further includes M multiplexer inputs, M being an integer greater than 1. Two or more reference frequencies are applied to the inputs of the multiplexer, by the selection of one from the reference frequencies, the low spur can be reached.

Abstract: A MASH modulator. The MASH modulator receives a fractional input value, generates an integer output value, and comprises three cascaded first order sigma delta modulators (SDMs) each comprising an accumulator, a plurality of first multipliers, a second multiplier, a first adder, and a second adder. Each of the first multipliers is coupled to a corresponding accumulator. The first adder receives the fractional input value. The second multiplier is coupled between the first adder and the cascaded first order sigma delta modulators. The second adder is coupled to the cascaded first order sigma delta modulators to generate the integer output value.

Abstract: A method and enhanced phase-locked loop (PLL) circuit enable effective testing of the PLL. A phase frequency detector generates a differential signal, receiving a reference signal and a feedback signal of an output signal of the PLL circuit. A charge pump is coupled to the phase frequency detector receiving the differential signal. The charge pump applies either negative or positive charge pulses to a low-pass filter, which generates a tuning voltage input applied to a voltage controlled oscillator. A first divider is coupled to the voltage controlled oscillator receives and divides down the VCO output signal, providing the output signal of the PLL circuit. A second divider receives the output signal of the PLL circuit and provides the feedback signal to the phase frequency detector. The output signal of PLL circuit is applied to a clock distribution.

Abstract: A method for calibrating a phase locked loop begins by determining a gain offset of a voltage controlled oscillator of the phase locked loop. The processing then continues by adjusting current of a charge pump of the phase locked loop based on the gain offset.

Abstract: An oscillator, a PLL circuit, a receiver and a transmitter that allow the circuit scale to be reduced and that are suitable for integration. The electrostatic capacities of variable capacitance circuits 230, 230A are made variable, thereby varying the oscillation frequency of a voltage controlled oscillator 21. The variable capacitance circuit 230 comprises a plurality of variable capacitance elements 60-64 the electrostatic capacities of which can be continuously varied by use of a control signal; a plurality of capacitors 50-54 which are associated with the respective variable capacitance elements and the electrostatic capacities of which are fixed; and a plurality of switches 71-74, 81-84 that individually switch combinational circuits, each of which comprises one of the plurality of variable capacitance elements 60-64 and a respective associated one of the plurality of capacitors 50-54, for selective connections.

Abstract: A method of operating a phase lock loop includes generating a control voltage based on both an output signal of a voltage-controlled oscillator and a reference signal. An operating mode is selected from one of a high-gain mode, a zero-gain mode and a low-gain mode based on the control voltage. The phase lock loop is operated in the selected one of the high-gain mode, the zero-gain mode, and the low-gain mode. The control voltage is offset to generate an offset voltage based on the selected operating mode. The output signal is generated based on the offset voltage.

Abstract: A technique includes selectively coupling impedances to an oscillator to establish a first frequency of operation of the oscillator. The technique includes repeating the selective coupling in a feedback loop to cause the first frequency to be near a second frequency.

Abstract: A zero-delay clock generator has a phase-locked loop (PLL) that generates a feedback clock and receives a reference clocks. All clocks are differential and have a common-mode voltage. The common-mode voltage of an externally-generated reference clock can vary from the common-mode voltage of the internally-generated feedback clock. Differences in common-mode voltage of the reference clock and feedback clock cause delay variations resulting in static phase offsets of generated clocks. A common-mode sense and equalizer senses the common-mode voltages of the buffered reference and feedback clocks, and generates control voltages. The control voltages adjust the common-mode voltage and delay of differential buffers that receive the reference and feedback clocks. The control voltages adjust the differential buffers to match the common-mode voltages of the buffered reference and feedback clocks. The buffered clocks are then applied to a phase and frequency detector of the PLL.

Abstract: A phase locked loop (PLL) includes a detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO), a divider, and a frequency change module. The detector provides a phase difference based on a reference signal and a feedback signal. The charge pump provides a charge based on the phase difference. The loop filter provides a voltage based on the charge. The VCO provides an output signal based on the voltage received from the loop filter. The divider divides a frequency of the output signal by a value to provide the feedback signal. The frequency change module processes an input signal having a first frequency to provide a processed signal having a second frequency that is different from the first frequency. The frequency change module selects the input signal or the processed signal to provide as the reference signal to the detector. Changing the frequency of the reference signal can change a frequency of a spur.

Abstract: A frequency synthesizer (50, 70) including an edge-detection circuit (51, 60) for disabling elements of the frequency synthesizer (50, 70) prior to start-up. The edge-detection circuit detects a transition edge of a reference-clock signal (ref_clk) of the frequency synthesizer (50, 70) and enables elements of the frequency synthesizer (50, 70) upon the detection of the transition edge.

Abstract: A digital frequency multiplier circuit is disclosed. The digital frequency multiplier circuit includes a digitally controlled oscillator (DCO), a phase detector and a control circuit. The DCO generates an internal feedback signal. The phase detector detects a phase difference between the internal feedback signal and an external reference clock signal. Coupled between the phase detector and the DCO, the control circuit adjusts the DCO to align the internal feedback signal with the external reference clock signal after a phase difference between the internal feedback signal and the external reference clock signal has been detected. The control circuit also locks a modulation frequency of the DCO and monitors the state of the digital frequency multiplier circuit in order to maintain the lock.

Abstract: A XtalClkChip based on the application of hierarchical circuit and noise circuit design on the RF circuits of LC oscillation tank and the multi-phase fractional PLL are developed. The XtalClkChip combines both the XtalChip and multi-phase fractional PLL to provide the customer's clock to customer directly. This XtalChip will replace the crystal and the crystal circuit. The XtalClkChip will replace all the customer's clock circuit.

Abstract: An oscillation stabilization detecting circuit comprises a T flip flop receiving a pulse-type oscillation signal generated by oscillating a crystal oscillator and then dividing the oscillation signal to output; a pulse control unit including inverters and transistors, the pulse control unit converting the signal output from the T flip flop into a pulse-type signal starting from a high level and then outputting the converted signal; and an oscillation stabilization detecting unit including a capacitor charged with the signal output from the pulse control unit; and a plurality of transistors. The oscillation stabilization detecting unit controls charging time of the capacitor by adjusting a bias current and, after the charging time passes, outputs a stabilization signal to a CPU, the stabilization signal representing that the oscillation signal is stabilized.

Abstract: An apparatus providing a phase/frequency modulation system is disclosed herein. The apparatus includes a first circuit configured to introduce an offset to center a signal applied to a VCO. The apparatus further includes a second circuit configured to set a gain of the VCO. A frequency tracking network is configured to dynamically adjust one or both of the offset and the gain.

Abstract: A radio frequency modulator based on direct frequency/phase modulation of output signal of a controllable oscillator (724) that is a part of a phase locked loop (PLL) provides a direct modulator that is able to operate over a wide frequency range with a flat frequency response. A modulation signal is digitally processed (721, 730) before injection to a high-pass path of a direct modulator. Applicability of digital signal processing is based on the fact that the modulation signal is a base band signal. Therefore, the modulation signal (702) occupies such a band in the frequency domain so that a sufficient ratio of a sampling rate to an upper edge frequency of the modulation signal can be achieved. Digital processing is used for compensating an effect of non-flat high-pass PLL transfer function and/or to perform pre-distortion of the input signal of a controlled oscillator to compensate an effect of non-linearity of a controlled oscillator.

Abstract: A VCO circuit includes: a control portion to which a first voltage is inputted and from which a second voltage corresponding to the first voltage is outputted; a current source portion to which the second voltage is inputted and from which a current corresponding to the second voltage is outputted; and an oscillator circuit to which the current is inputted and from which a signal with a frequency in accordance with the current is outputted. The control portion includes an adjusting circuit which changes the second voltage in conjunction with fluctuation of a power supply voltage. Accordingly, fluctuation of the frequency Fo of an output signal of the VCO circuit can be suppressed even when the power supply voltage of the VCO circuit fluctuates.

Abstract: A delta-sigma modulated fractional-N PLL frequency synthesizer is provided. The frequency synthesizer includes a phase frequency detector for receiving a reference signal with a reference frequency (Fref) and an overflow signal to output a phase difference signal by detecting a phase and frequency difference between the reference signal and the overflow signal; a charge pump for generating an output current pulse in response to the phase difference signal; a loop filter for filtering the charge pump output current pulse and generating a corresponding control voltage; a VCO for generating a VCO output signal with a voltage controlled frequency (Fvco) in response to the control voltage; and a delta-sigma modulator, with a clock input terminal for receiving the VCO output signal, an overflow output terminal for generating the overflow signal and an integer input terminal, for determining the ratio of the VCO frequency (Fvco) and the reference frequency (Fref).

Abstract: A phase lock loop includes a calibration loop for calibrating a tank circuit for capacitance variation through process variations of manufacturing an integrated circuit including the phase lock loop. A capacitance profile for setting the frequency of the phase lock loop at a process corner, such as a typical process corner is stored in driver software or a host processor. At power up, or after an idle time, a calibration is performed at two frequencies. The capacitances of operating the phase lock loop at the two frequencies are determined and stored. During a frequency change, the capacitance of operating the phase lock loop is determined from the capacitance profile and stored capacitances. In one aspect, the capacitance of the phase lock loop is presumed to change linearly with frequency and the two stored capacitances are used to determine a difference capacitance at the selected frequency by linear interpolating between the two stored capacitances.

Abstract: All embodiments of the present invention basically include an upper transistor and a lower transistor connected in series between a power supply and ground. The upper transistor and the lower transistor have a shared source (or drain) terminal which becomes a single bidirectional node. They further comprise a sensing gate and a logic gate. The sensing inverter has a function of sensing a voltage at the single bidirectional node and comparing it with an input transition voltage since an input terminal of the sensing inverter is connected to the single bidirectional node. An initial voltage at the single bidirectional node of the filter-based lock-in circuit is almost the same as the input transition voltage of the sensing inverter, where the input transition voltage is an input voltage which causes an output voltage to be V DD 2 .

Abstract: In a portable dual mode receiver circuit, a dual modulus clock system is provided which can, by selective use of integer division on a multiplied master clock, select specific channels with two different channel spacings in several different bands, providing power and space savings and achieving simplicity of operation.

Abstract: The present invention relates to an oscillating apparatus. The oscillating apparatus includes a biasing circuit, a multi-vibrator, a detecting circuit, and a selecting circuit. The biasing circuit is for generating a bias signal, wherein the biasing circuit includes a connecting port for using an impedance device to control an oscillating frequency or for directly connecting to external clock source as a reference clock. The multi-vibrator coupled to the biasing circuit for generating the oscillating frequency according to the quantity of the biasing signal. The detecting circuit coupled to the connecting port for generating a detecting signal whether the connecting port is coupled to the impedance device or the external clock source. The selecting circuit includes an AND gate coupled to the multi-vibrator and the selection signal and an OR gate coupled to the AND gate and the connecting port.

Abstract: A charge pump circuit includes a first PMOS transistor, a first NMOS transistor connected with the first PMOS transistor at a CPOUT node that is configured to provide an output signal from the charge pump circuit, and a second PMOS transistor connected between a high-voltage supply terminal (VDD) and the first PMOS transistor. The second PMOS transistor can provide a current IUP to the first PMOS transistor. A capacitor is connected to VDD and the gate of the second PMOS transistor. The charge pump circuit also includes an operational amplifier having its negative input and its output connected to the gate of the second PMOS transistor, and its positive input connected to the CPOUT node.

Abstract: A PLL is provided, comprising a first divider, a PFD, a loop filter, a VCO, a second divider and a controller. The first divider receives a reference signal and divides the reference signal by R to obtain a divided signal. The PFD compares the divided signal and a feedback signal to generate a compared The VCO selects one of a plurality of operating curves for oscillation based on a selection signal, and generates an oscillation signal based on an operating voltage generated by signal the loop filter. The second divider divides the oscillation signal by N to obtain the feedback signal. The controller operates in an initial mode to recursively determine the selection signal by calculating differences of the feedback signal and the divided signal. When the selection signal converges to stable, the PLL switches to a normal mode to operate on the corresponding operating curve.

Abstract: A wide-band multimode frequency synthesizer using a Phase Locked Loop (PLL) is provided. The multiband frequency synthesizer includes a multimode prescaler, a phase detector/a charge pump, a swallow type frequency divider, and a switching bank LC tuning voltage-controlled oscillator having wide-band and low phase noise characteristics. The multimode prescaler operates in five modes and divides a signal up to 12 GHz. The wide-band frequency synthesizer can be used in various fields such as WLAN/HYPERLAN/DSRC/UWB systems that operate in the frequency range from 2 GHz to 9 GHz.

Abstract: The present invention provides a clock circuit to produce a Reference Clock Signal used to latch data between first bit stream(s) and second bit stream(s), wherein the number and bit rate of the first bit stream(s) and the second bit stream(s) differ. The VCO generates one of a number of inputs to a PLL within the clock circuit. At a minimum, these inputs include a first bit stream data clock. Additionally, these inputs may further include a Loop Timing Clock Signal, an External Reference Clock Signal, and/or a Reverse Clock Signal for the PLL. The input provided by the VCO make up a VCO Output Signal wherein a filtering circuit that circuit includes a capacitor and a resistor reduces noise contained within the VCO Output Signal.