Abstract: A phase recovery circuit for avoiding noise interfering with the clock signal generated from an oscillator is disclosed. The phase recovery circuit includes a noise detector, a phase detector, and a phase locker. The noise detector detects noise and accordingly generates a noise detecting signal. The phase detector is triggered by the noise detecting signal for detecting the phase of the clock signal and accordingly generating a phase detecting signal. The phase locker locks the phase of the clock signal to a predetermined phase within a predetermined period after the occurrence of the noise detecting signal, and after the predetermined period, the phase locker releases the clock signal. In this way, the phase of the clock signal is not affected by noise.

Abstract: A method of eliminating a runaway condition in a PLL includes the steps of: determining whether the PLL is locked to an input reference signal; when the PLL is not locked to the input reference signal, determining whether a frequency of an output signal generated by the PLL exceeds a prescribed maximum frequency; and when the frequency of the output signal generated by the PLL exceeds the prescribed maximum frequency, resetting the PLL to thereby eliminate the runaway condition.

Abstract: A device and a method are presented for generating an intermitted oscillating signal comprising a plurality of oscillating portions separated from each other in time. The device and method are suited for communication systems, in particular for Ultra-Wide Bandwidth (UWB) applications. The device comprises a variable oscillator for generating the oscillating portions; switching circuitry for switching on/switching off the variable oscillator at the beginning/end of each oscillating portion; and circuitry for setting initial conditions in the variable oscillator to impose a predefined transient and a characterizing frequency upon each start-up.

Abstract: The present invention relates to a control method for the operation modes of an oscillator and the apparatus thereof, for which the method and the apparatus can be applied to the electronic circuits with multi-operation modes of the oscillator so as to correctly choose the desirable oscillator operation mode. Furthermore, an oscillator checking circuit sets up the oscillation mode automatically and judges if the oscillator operates properly. Hence, there is no need for the user to set up the oscillator operation mode manually.

Abstract: An oscillation driver device includes a gain control amplifier, an automatic gain control circuit, and a mode setting circuit. When the mode setting circuit has switched a mode from a normal operation mode to a low power consumption mode, the automatic gain control circuit is disabled, and the gain in an oscillation loop that drives the vibrator changes from a state in which the gain in the oscillation loop is controlled to be unity by the automatic gain control circuit to a state in which the gain in the oscillation loop is set to be larger than unity. When the mode setting circuit has switched the mode from the low power consumption mode to the normal operation mode, the automatic gain control circuit resumes operation, and the gain in the oscillation loop changes from the state in which the gain in the oscillation loop is set to be larger than unity to the state in which the gain in the oscillation loop is controlled to be unity by the automatic gain control circuit.

Abstract: A low-power-consumption semiconductor device and a driving method thereof where a clock signal generation is controlled. A transmission and reception control circuit to control signal communication with an outside; a ring oscillator control circuit to detect an edge in a receiving signal and control a ring oscillator; a clock generation circuit to generate a clock signal based on the ring oscillator; and a logic circuit to operate based on a clock signal are included. During signal communication between the transmission and reception control circuit and the outside, the ring oscillator operates and a clock signal is output from the clock generation circuit when the ring oscillator control circuit detects an edge in a receiving signal, and the ring oscillator stops and output of the clock signal from the clock generation circuit stops when transmission of a reply signal from the transmission and reception control circuit to the outside is terminated.

Abstract: An L-C resonant circuit with an adjustable resonance frequency, having a capacitor and a first inductor electrically coupled together and a second inductor magnetically coupled to the first inductor. Additionally, there is a control circuit to sense a signal representing a first current flowing through the first inductor and to force through the second inductor a second current that is a replica of the first current for setting the adjustable resonance frequency of the L-C resonant circuit.

Abstract: An oscillator circuit may be used with controller circuits that are designed to operate with crystals, with no modifications to the pinout or firmware of the controller circuit. In some embodiments, the oscillator circuit includes an enable input that is responsive to low-amplitude transitions, which may be coupled to and driven by the crystal output signal of the controller circuit. When transitions are present on the crystal output signal, the oscillator circuit enables its clock output signal. When the controller circuit disables its crystal output signal, the oscillator circuit no longer detects transitions on the crystal output signal coupled to the oscillator circuit enable input, and disables the clock output signal.

Abstract: An oscillator circuit may be used with controller circuits that are designed to operate with crystals, with no modifications to the pinout or firmware of the controller circuit. In some embodiments, the oscillator circuit includes an enable input that is responsive to low-amplitude transitions, which may be coupled to and driven by the crystal output signal of the controller circuit. When transitions are present on the crystal output signal, the oscillator circuit enables its clock output signal. When the controller circuit disables its crystal output signal, the oscillator circuit no longer detects transitions on the crystal output signal coupled to the oscillator circuit enable input, and disables the clock output signal.

Abstract: A global positioning system and integrated circuit with a differential oscillator and with a starting circuit connected to the differential oscillator, wherein the differential oscillator has a current mirror for setting an operating current through each of the two branches, the starting circuit has at least one switch connected to the current mirror, and has a starting means connected to the at least one switch, and the current mirror, the at least one switch, and the starting means are wired in such a manner that the operating current in each of the two branches of the differential oscillator is increased during a starting phase, which phase is a function of the starting means.

Abstract: A high frequency signal detection circuit includes an input terminal for a high frequency signal to be detected, a switch transferring the high frequency signal as intermittent ringing signal to a first node in response to a pulse signal whose frequency is lower than that of the high frequency signal, a transistor amplifying the signal at the first node, and outputting to a second node, a bias generator generating a bias voltage by which the transistor is operated in its weak inversion region, a resonant circuit outputting the bias voltage to the first node, and resonating the high frequency signal, a capacitor removing a high frequency component of the signal at the second node; and a judgment circuit judging whether or not the high frequency signal is inputted by detecting the signal at the second node, which has the same frequency as the pulse signal.

Abstract: To determine performance degradation at functional module in a normal power state due to a power control device, voltages are applied to oscillators at a power diagnostic module. A first voltage is a supply voltage for the data processing device, and a second voltage is a supply voltage applied at a functional module of the data processing device. Counters are adjusted based on the oscillators to determine the oscillators' respective frequencies. In addition, the power diagnostic module can include a timer to measure the length of time that the functional module is in a low-power state, and an analog to digital converter to measure the voltage applied to the functional module during transitions to and from the low-power state.

Abstract: An apparatus, system and method are provided for low-latency start-up of a free-running harmonic oscillator. The exemplary apparatus embodiment comprises a first and second current sources to generate first and second currents; a bias current monitor adapted to detect a magnitude of the second current and to provide a control signal when the magnitude of the second current is equal to or greater than a predetermined magnitude; and a bias controller adapted to switch the first current from the oscillator and to switch the second current to the oscillator in response to the control signal. a reference voltage generator, a comparator, and a bias controller. Exemplary embodiments include reference voltage generator, a comparator, and a bias controller.

Abstract: An integrated circuit package includes a processing core and an internal oscillator. The processing core operates on a set of instructions to carry out predefined processes. The internal oscillator provides a system clock for the integrated circuit package. The internal oscillator has associated therewith an internal control register for controlling the operation of the internal oscillator responsive to control bits of the internal oscillator controlled by the processing core.

Abstract: There is provided an oscillator circuit capable of obtaining stable frequency by avoiding output having unstable frequency that is likely to occur to an operation/stop-control-feasible type oscillator circuit when oscillation begins. In such an oscillator circuit, an oscillation permitting signal (EN) sets an oscillator section in oscillation-operable state, whereby a controller section starts operation. The controller section that has stared its operation change an oscillation- frequency control signal (VR) into a signal value corresponding to predetermined oscillation frequency so as to set oscillation frequency at an oscillator section. Further on, the oscillator section outputs an oscillation signal in response to a detection signal (MON) that is outputted after a detector section compares a signal inputted therein with a predetermined signal value and detects that the inputted signal reaches a predetermined signal value.

Abstract: A startup circuit 200 and method 700 is provided for quickly starting up a resonator based oscillator. Tunable oscillator 201 provides an impetus signal to oscillator 205 through capacitor 202. The impetus signal has a frequency that is an estimate of the resonant frequency of resonator 205. The circuit measures the frequency of oscillator 204 and the frequency of tunable oscillator 201. The circuit then adjusts the frequency of tunable oscillator 201 such that the frequency of the tunable oscillator is substantially equal to the resonant frequency of the resonator 205 and stores a data state necessary for the tunable oscillator 201 to generate a signal with this target frequency in the future. During an ensuing startup cycle the stored data state causes the impetus signal delivered by tunable oscillator 202 to be substantially equal to the target frequency of oscillator 204 which improves startup performance.

Abstract: A radar oscillator has an oscillation unit and first and second switch circuits. The first switch circuit turns off an electric power supply to an amplifier in a non-input period of a pulse signal to set the oscillation unit in a non-oscillation state and turns on the electric power supply to the amplifier in an input period of the pulse signal to set the oscillation unit in an oscillation state. The second switch circuit turns on an electric power supply to an LC resonator in a period immediately before the pulse signal is input in a period in which the pulse signal is not input to supply a current to the LC resonator and turns off the electric power supply to the LC resonator at a timing at which the pulse signal is input, so that activation of an oscillation operation of the oscillation unit is accelerated.

Abstract: An internal voltage generator capable of reducing the variation width in the level of an internal voltage VPP, by performing charge pumping only a predetermined number of times in a period where an oscillator driving signal is at a logic HIGH level, and then stopping the charge pumping operation. The oscillator controller generates an oscillation control signal for stopping an oscillation operation of a ring oscillator by using an output signal of a level detector and an output signal of the ring oscillator. The ring oscillator does not generate an oscillation signal at a predetermined time point where an output signal of the level detector is at a HIGH level in response to the oscillation control signal. The charge pump circuit generates an internal voltage by performing a charge pumping operation only predetermined times in response to the oscillation signal, and then stopping the charge pumping operation.

Abstract: A noise removal circuit. The noise removal circuit comprises a crystal oscillator and a level decision module. The crystal oscillator generates an oscillating signal and an output clock signal. The level decision module detects the signal level of the oscillating signal and outputs the output clock signal when the signal level of the oscillating signal exceeds a first reference level.

Abstract: An oscillator includes an oscillating block for generating a control signal in response to an enable signal, wherein the control signal is periodically toggled and a feedback block for receiving the control signal to generate the enable signal in response to an oscillator enable signal wherein the enable signal operates so that the control signal is maintained to complete a last cycle period after an inactivation timing of the oscillator enable signal.

Abstract: Voltage controlled oscillator (VCO) circuitry with low phase noise and a wide range of operating frequencies is presented. The VCO circuitry includes circuitry with two or more VCO sub-circuits, each sub-circuit being optimized to produce output clock signals with low phase noise and with frequencies in a different range. Sub-circuits with gear inputs may be operative to produce output clock signals in a lower range of frequencies, while sub-circuits optimized for high speed operation may be used to produce output signals in a higher range of frequencies. A control circuit may be used to produce a control signal coupled to all sub-circuits. The control signal may set the operating frequency of the sub-circuits.

Abstract: A noise removal circuit. The noise removal circuit comprises a crystal oscillator and a level decision module. The crystal oscillator generates an oscillating signal and an output clock signal. The level decision module detects the signal level of the oscillating signal and outputs the output clock signal when the signal level of the oscillating signal exceeds a first reference level.

Abstract: A consumption current balance circuit reduces the layout area and suppresses the deterioration of accuracy of a delay time caused by a temperature variation due to a power variation of a delay circuit itself or caused by a load variation of a power supply. The consumption current balance circuit includes a delay circuit for giving a delay time to a timing pulse signal, a compensation circuit for interpolating the consumption current of the delay circuit, a ring oscillator provided in the same power supply area as the delay circuit; an output period counter for measuring the output period of the ring oscillator; and a heater circuit current amount adjusting circuit for adjusting the current amount of the heater circuit to minimize the difference in the output period between the stand-by state and the active state of the ring oscillator.

Abstract: Methods and apparatus for implementing stable self-starting and self-sustaining electrical nonlinear pulse (e.g., soliton, cnoidal wave, or quasi-soliton) oscillators. In one example, a nonlinear pulse oscillator is implemented as a closed loop structure that comprises a nonlinear transmission line, an improved high-pass filter, and a nonlinear amplifier configured to provide a self-adjusting gain as a function of an average voltage of the oscillator signal, to provide a pulse waveform having a desired target amplitude. In one implementation, the nonlinear amplifier and high pass filter functions are integrated in a two stage nonlinear amplifier/filter apparatus employing complimentary NMOS and PMOS amplification components and associated filtering and feedback circuitry configured to essentially implement an electric circuit analog of a saturable absorber via an adaptive bias control technique.

Abstract: An apparatus, system and method are provided for low-latency start-up of a free-running harmonic oscillator. The exemplary apparatus embodiment comprises a first and second current sources to generate first and second currents; a bias current monitor adapted to detect a magnitude of the second current and to provide a control signal when the magnitude of the second current is equal to or greater than a predetermined magnitude; and a bias controller adapted to switch the first current from the oscillator and to switch the second current to the oscillator in response to the control signal. a reference voltage generator, a comparator, and a bias controller. Exemplary embodiments include reference voltage generator, a comparator, and a bias controller.

Abstract: There is provided an oscillator circuit capable of obtaining stable frequency by avoiding output having unstable frequency that is likely to occur to an operation/stop-control-feasible type oscillator circuit when oscillation begins. In such an oscillator circuit, an oscillation permitting signal (EN) sets an oscillator section in oscillation-operable state, whereby a controller section starts operation. The controller section that has stared its operation change an oscillation-frequency control signal (VR) into a signal value corresponding to predetermined oscillation frequency so as to set oscillation frequency at an oscillator section. Further on, the oscillator section outputs an oscillation signal in response to a detection signal (MON) that is outputted after a detector section compares a signal inputted therein with a predetermined signal value and detects that the inputted signal reaches a predetermined signal value.

Abstract: An oscillator of a semiconductor memory device, wherein a reference voltage that flexibly shifts according to the shift in a power supply voltage is generated, and a reference clock is generated using the reference voltage. It is thus possible to generate the reference clock having a constant cycle regardless of the shift in the power supply voltage which can keep constant the duration period of internal control signals of devices, such as a timer and a pump circuit, which are synchronized to the reference clock.

Abstract: An integrated circuit includes an oscillator circuit, where a frequency of an oscillator output signal provided by the oscillator circuit is adjustable by either coupling a resistor to an input pin, or by applying an external clock signal to the input pin. The oscillator circuit includes a comparator, a follower, a current-controlled oscillator, and a switch circuit. The switch circuit is coupled between the input pin and a node that is coupled to the current-controlled oscillator. Also, the follower is arranged to cause the voltage at the node to be at a pre-defined voltage unless the voltage at the node is overdriven by an external clock signal. The comparator circuit is arranged to determine whether the signal at the input pin is a clock signal. If it is determined that the signal at the input pin is a clock signal, the switch circuit is opened.

Abstract: A system for synchronizing a portable transceiver to a network is disclosed. Embodiments of the system for synchronizing a portable transceiver to a network include a crystal oscillator, a frequency synthesizer adapted to receive an output of the crystal oscillator, logic coupled to the crystal oscillator, the logic configured to estimate a frequency error of a received signal; and a first control signal supplied from the logic to the frequency synthesizer, the first control signal configured to adjust the frequency synthesizer to compensate for the error.

Abstract: An oscillation-stop detection circuit includes a switching unit that repeats turning on and off based on a cycle of an oscillation signal from an outside; a capacitor that is charged when the switching unit is turned on, and discharged when the switching unit is turned off; a first MOS transistor that flows a discharge current of the capacitor when the capacitor is discharged; a discharge cutoff unit that cuts off a discharge path for the discharge current to flow, for a predetermined time right after a power is turned on; and a detecting unit that detects a status of the oscillation signal based on a voltage of the capacitor.

Abstract: A semiconductor device includes an external oscillation circuit connected to an external resonator, a self-exciting oscillation circuit, and an oscillation clock monitoring circuit, the oscillation clock monitoring circuit monitors an oscillation state of the external resonator using a clock signal generated by the self-exciting oscillation circuit, and when judged that the oscillation state has been stabilized, the terminating signal of the waiting time for stabilization of oscillation is outputted to terminate the waiting time for stabilization of oscillation of a microcomputer forcedly.

Abstract: An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input signal may be generated in a pulse generator to have an input pulse duration less than or equal to that of the oscillating signal. The oscillator circuit may be used as a filter to filter pulse width variations or to filter jitter from a reference clock. The oscillator circuit may also serve as a buffer by amplifying the input signal. Phase interpolation can be obtained by coupling at least one input signal with at least one oscillating signal.

Abstract: There is provided an oscillator circuit capable of obtaining stable frequency by avoiding output having unstable frequency that is likely to occur to an operation/stop-control-feasible type oscillator circuit when oscillation begins. In such an oscillator circuit, an oscillation permitting signal (EN) sets an oscillator section in oscillation-operable state, whereby a controller section starts operation. The controller section that has stared its operation change an oscillation-frequency control signal (VR) into a signal value corresponding to predetermined oscillation frequency so as to set oscillation frequency at an oscillator section. Further on, the oscillator section outputs an oscillation signal in response to a detection signal (MON) that is outputted after a detector section compares a signal inputted therein with a predetermined signal value and detects that the inputted signal reaches a predetermined signal value.

Abstract: A voltage controlled oscillator, such as a VCXO (Voltage Controlled Crystal Oscillator), for generating a desired reference frequency in a wireless terminal with a reduced start-up time is described herein. According to the present invention, the VCXO comprises an oscillator that generates the desired reference frequency based on a variable voltage applied to the oscillator by a voltage controller. In addition, the VCXO includes a start-up controller that applies a bias voltage to an oscillator input node to reduce a capacitance associated with the oscillator, and therefore, to reduce the start-up time without negatively impacting the DC current consumption or the tuning range of the VCXO.

Abstract: A switched capacitor circuit includes a capacitor; a switch element for selectively coupling a first node to a second node according to a control signal, wherein the first node is coupled to the capacitor; and a charge circuit coupled to the first node for coupling the first node to a third node and for controlling a first voltage difference across the first switch element in the off-state to be greater than a charge voltage. By ensuring the charge voltage is large enough to minimize a parasitic capacitance of the switch element, the clock feedthrough effect is eliminated, the locking period of the VCO is shortened, and the phase noise of the VCO is minimized.

Abstract: A means is provided to establish oscillations on a particular mode or resonance of a quartz crystal in a crystal oscillator and to discriminate against other modes. This is done by injecting a signal close in frequency to the desired mode until oscillation have been established and saturation of the active element has occurred. The limiting process then discriminates against the unwanted modes and holds the oscillation on the desired mode.

Abstract: A high accuracy crystal oscillator for generating a clock signal comprises a gain stage (2) controlled by a current from a current source (5), and a trimmable load capacitance (3, 4). To generate a low power clock signal, a mode control unit (7) is provided for disconnecting at least part of the load capacitance (3, 4) and activating an oscillation amplitude regulator (6) that is connected between the input terminal of the gain stage (2) and the current source (5) to reduce the current to the gain stage (2) to such a value that oscillation is maintained with a minimum amplitude.

Abstract: An oscillator circuit having an expanded operating range includes an amplifier portion amplifying an oscillating signal. A gain controlling portion controls the gain of the amplified oscillating signal. A switching circuit electrically connected across the gain controlling portion provides a low impedance electrical path in parallel with the gain controlling portion in response to a switch input signal. The switching circuit further includes a switch signal generator portion producing the switch input signal to switch the switching circuit ON or OFF when power supplied to the oscillator circuit reaches a first predetermined voltage level and to switch the switching circuit OFF or ON when power supplied to the oscillator circuit reaches a second predetermined voltage level. In this circuit design, the initiation of an oscillating signal by the oscillator circuit is unaffected by supply voltage variation or, in other words, fluctuation in the power supplied to the oscillator circuit.

Abstract: A self-biased phase locked loop (PLL) circuit includes a charge pump to generate a control voltage, a controlled oscillator coupled to the charge pump to generate the output signal based at least in part upon the control voltage, discharge circuitry coupled to the charge pump to discharge the control voltage, and frequency detection circuitry coupled to the controlled oscillator and the discharge circuitry to generate a digital feedback signal for terminating discharge of the control voltage by the discharge circuitry when the output signal reaches a threshold frequency that is a fraction of the target frequency.

Abstract: A power down system and method for an integrated circuit that enables a power down mode to be maintained for a predetermined time is described herein. The power down system comprises an oscillator, a low power oscillator and an oscillator control circuit controlling both the oscillator and the low power oscillator. The oscillator control circuit including at least one real time counter. The oscillator control circuit being so configured that the oscillator is energized when said oscillator control circuit is in a normal mode and that, when a power down signal is received: a) the oscillator control circuit measures an oscillation frequency of the low power oscillator, b) the oscillator control circuit uses the measured oscillation frequency of the low power oscillator to set the real time counter so as to maintain the power down mode for the predetermined time, c) the oscillator control circuit turns off the oscillator and uses the low power oscillator for the duration of the power down.

Abstract: An automatic gain control circuit for controlling a start-up time of an oscillator and a method thereof are provided. An oscillation detection unit is used to detect the start-up time of the oscillator. In addition, a control unit is used to move the start-up time of the oscillator forward when the start-up time of the oscillator is later than a first predetermined time point. Moreover, when the start-up time of the oscillator is earlier than a second predetermined time point, the start-up time of the oscillator is delayed.

Abstract: An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input signal may be generated in a pulse generator to have an input pulse duration less than or equal to that of the oscillating signal. The oscillator circuit may be used as a filter to filter pulse width variations or to filter jitter from a reference clock. The oscillator circuit may also serve as a buffer by amplifying the input signal. Phase interpolation can be obtained by coupling at least one input signal with at least one oscillating signal.

Abstract: Briefly, in accordance with embodiments of the invention, switched capacitors may be utilized to emulate resistors in a longer time constant feedback network for amplitude regulation of a crystal oscillator.

Abstract: An oscillation circuit including a resonating element such as a crystal, an inverting amplifier and a resistor that each span the resonating element terminals, and two capacitors that capacitively couple the resonating element terminals to ground. An AC current source such as a temperature compensated and properly trimmed ring oscillator generates a differential AC current when active. The differential AC current has a frequency that is within a tolerance of the resonant frequency of the resonant element for a given set of operating conditions. Two buffers connect the differential outputs of the AC current source to respective terminals of the resonating element to thereby shorten startup time. A control logic circuit carefully times the application of the differential AC current to the resonating element terminals such that the current is applied for a sufficient time such that startup would occur under any anticipated operating condition.

Abstract: An improved oscillator system has a control logic block which has an input from an external device to which clock is being provided. The input controls a counter which counts cycles from the oscillator. If some predetermined number of cycles has passed in the absence of a predetermined input condition, then the oscillator halts, thus reducing power consumption by the oscillator system. Later, upon the predetermined input condition, the oscillator resumes oscillation. The system has improved noise immunity and permits a continuous-oscillation mode without the need of an extra pin or memory bit. The control logic block may also employ a counter which counts the number of times the predetermined input condition has occurred, and only after some predetermined number of occurrences does the oscillator-halting activity take place.

Abstract: A rectifier (306) rectifies (402) an output signal of a VCO (302) to produce an envelope signal proportional to an amplitude of the output signal. An integrator (308) integrates (404) the envelope signal to produce a comparison signal, such that, in response to a change in the envelope signal, during a first mode of operation of the VCO, the comparison signal is allowed to change at a first rate, and, during a second mode of operation of the VCO, the comparison signal is allowed to change at a second rate different from the first rate. A comparator (310) compares (406) the comparison signal with a reference signal (316) to produce a bias signal, and controls (408) a gain of the VCO with the bias signal.

Abstract: A rectifier (306) rectifies (402) an output signal of a VCO (302) to produce an envelope signal proportional to an amplitude of the output signal. An integrator (308) integrates (404) the envelope signal to produce a comparison signal, such that, in response to a change in the envelope signal, during a first mode of operation of the VCO, the comparison signal is allowed to change at a first rate, and, during a second mode of operation of the VCO, the comparison signal is allowed to change at a second rate different from the first rate. A comparator (310) compares (406) the comparison signal with a reference signal (316) to produce a bias signal, and controls (408) a gain of the VCO with the bias signal.

Abstract: The present invention is made to resolve problems of the above described prior art. Prime object of the present invention is to provide an oscillator circuit capable of outputting oscillation signal with stable oscillation frequency, a semiconductor device and a semiconductor memory device provided with the oscillator circuit, and control method of the oscillator circuit. For achieving the prime object, there are taken the following countermeasures at the time of initiating oscillation where the inventive oscillator circuit can control to operate/stop oscillation. That is, the countermeasures to be taken are: (1) oscillation operation is stopped or an output of an oscillation signal is not permitted while transient oscillation frequency is unstable; or (2) a period that transient oscillation frequency is unstable is shortened.

Abstract: An oscillator includes a common logic circuit and a plurality of delay lines. Each delay line is configured to receive a state transition at its input terminal and to output a corresponding state transition at its output terminal after a corresponding delay. An output terminal of each delay line is in electrical circuit with a corresponding input terminal of the common logic circuit, and the input terminal of each of the delay lines is in selectable electrical circuit with the output terminal of the common logic unit. The common logic circuit is configured to output a state transition at its output terminal in response to a state transition at any one of the input terminals of the common logic circuit.

Abstract: An apparatus having a radio frequency resonator, which has a coil, a capacitor means and at least one switch means being associated with another capacitor means, a resistor means and a high voltage supply means, one end of the switch means being connected to a junction of the coil and the capacitor means where a radio frequency voltage is provided, another end of the switch means being connected to ground with said another capacitor means and to the high voltage power supply means with the resistor means.