Frequency Stabilization Patents (Class 331/175)
  • Patent number: 10924124
    Abstract: Techniques are disclosed relating to rapidly downshifting the output frequency of an oscillator. In some embodiments, the oscillator is configured to operate in a closed-loop mode in which negative feedback is used to maintain a particular output frequency (e.g., in a phase-locked loop (PLL)). In some embodiments, the negative feedback loop is configured to maintain the output of the oscillator at a particular frequency based on a reference clock signal and the output of the oscillator. The nature of a negative feedback loop may render rapid frequency changes difficult, e.g., because of corrections by the loop. Therefore, in some embodiments, the loop is configured to switch to an open-loop mode in which a control input to the oscillator is fixed. In some embodiments, the loop switches to open-loop mode in response to a trigger signal and control circuitry forces the oscillator to a new target frequency.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: February 16, 2021
    Assignee: Apple Inc.
    Inventors: Brian S. Leibowitz, Jared L. Zerbe, Sanjay Pant
  • Patent number: 10886901
    Abstract: A circuit includes multiple stages cascaded in a ring topology such that each stage has a preceding stage, a succeeding stage, an alternate-preceding stage, and an alternate-succeeding stage. Each stage includes a MOS transistor of a first type, a MOS transistor of a second type and a resistor. The MOS transistor of a first type receives a first input that is output from the preceding stage, and outputs a second output to the alternate-preceding stage. The MOS transistor of a second type receives a second input that is output from the alternate-succeeding stage, and outputs a first output to the succeeding stage. The resistor provides coupling and level-shifting between the first output and the second output.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: January 5, 2021
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 10727818
    Abstract: A circuit may comprise a first node, a ring oscillator, a regulator, and a Kvcc compensation circuit. The first node may be a supply node to provide a supply voltage for the circuit. The ring oscillator may be formed from inverters. The regulator may use a single transistor between the first node and a second node for powering the oscillator. The K compensation circuit may be used to provide to the oscillator a variable capacitive load that is dependent on the supply at the first supply node, and it may drag oscillator frequency down when the first node supply goes up.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Shenggao Li, Sujatha Gowder
  • Patent number: 10715153
    Abstract: Apparatus and associated methods relate to automatically generating a data structure representation of an on-chip inductive-capacitive (LC) tank circuit by determining parasitic inductances in each of the segments of conductive paths that connect a main inductor to one or more selectable VCO components such as capacitors and varactors, for example. In an illustrative example, one or more of the selectable VCO components may be arranged, when selected, to form a parallel resonant LC tank with the main inductor. A method may include defining nodes ai terminating each of the segments along the conductive paths between the main inductor terminals and a drive circuit. By modelling the paths as multi-port inductors and transformers, resonant frequency of the VCO may be more accurately predicted by simulation.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: July 14, 2020
    Assignee: XILINX, INC.
    Inventors: Adebabay M. Bekele, Parag Upadhyaya, Didem Z. Turker Melek, Jing Jing
  • Patent number: 10659013
    Abstract: A start-up circuit for a ring current-controlled oscillator (CCO) includes a replica CCO current generator, a replica ring CCO, and a buffer. The ring CCO is connected to a CCO driver and the buffer. The CCO driver generates a CCO current based on a reference current. The ring CCO generates a CCO output voltage at a first oscillating frequency based on the CCO current. The replica CCO current generator generates a replica CCO current based on a reference voltage. The replica ring CCO generates a replica CCO output voltage at a second oscillating frequency based on the replica CCO current. The buffer provides a first current to the ring CCO when the first oscillating frequency is lower than a desired oscillating frequency, and drains a second current from the ring CCO when the first oscillating frequency is greater than the desired oscillating frequency.
    Type: Grant
    Filed: January 1, 2019
    Date of Patent: May 19, 2020
    Assignee: NXP USA, Inc.
    Inventors: Yang Wang, Jianzhou Wu, Jie Jin, Jiawei Fu
  • Patent number: 10630300
    Abstract: Techniques are disclosed relating to rapidly downshifting the output frequency of an oscillator. In some embodiments, the oscillator is configured to operate in a closed-loop mode in which negative feedback is used to maintain a particular output frequency (e.g., in a phase-locked loop (PLL)). In some embodiments, the negative feedback loop is configured to maintain the output of the oscillator at a particular frequency based on a reference clock signal and the output of the oscillator. The nature of a negative feedback loop may render rapid frequency changes difficult, e.g., because of corrections by the loop. Therefore, in some embodiments, the loop is configured to switch to an open-loop mode in which a control input to the oscillator is fixed. In some embodiments, the loop switches to open-loop mode in response to a trigger signal and control circuitry forces the oscillator to a new target frequency.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: April 21, 2020
    Assignee: Apple Inc.
    Inventors: Brian S. Leibowitz, Jared L. Zerbe, Sanjay Pant
  • Patent number: 10630297
    Abstract: The present invention provides an oscillator circuit and associated oscillator device. The oscillator circuit comprises a negative-temperature-coefficient (NTC) bias current generating circuit and a set of oscillator sub-block circuits. The NTC bias current generating circuit is coupled between a supply voltage and a ground voltage, and is arranged to generate at least one NTC bias current. The set of oscillator sub-block circuits are coupled to each other to form an oscillator. Each oscillator sub-block circuit of the set of oscillator sub-block circuits comprises a plurality of transistors coupled between the supply voltage and a node within the NTC bias current generating circuit, wherein the NTC bias current generating circuit and the aforementioned each oscillator sub-block circuit share at least one transistor in the plurality of transistors.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: April 21, 2020
    Assignee: Artery Technology Co., Ltd.
    Inventors: Baotian Hao, Chao Li, Weitie Wang
  • Patent number: 10571940
    Abstract: An apparatus for generating a steady state positive voltage (PVS) signal and a steady state negative voltage (NVS) signal is presented. The apparatus includes a bias signal generation module for generating a steady state reference voltage signal (RVS) based on a varying supply voltage signal (VDD), the RVS having a voltage level less than the PVS. The apparatus further includes a positive signal generation module (PSGM) generating the PVS, the PSGM including a first capacitor, the PSGM employing the first capacitor to generate a portion of the PVS based on the RVS. The apparatus further includes a negative signal generation module (NSGM) generating the NVS, the NSGM including a second capacitor, the NSGM employing the second capacitor to generate a portion of the NVS based on the RVS.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: February 25, 2020
    Assignee: pSemi Corporation
    Inventors: Tae Youn Kim, Robert Mark Englekirk
  • Patent number: 10525187
    Abstract: The invention relates to an apparatus for extracorporeal removal of protein-bound toxins from blood plasma comprising a first line device, a second line device, a third line device and a fourth line device, a dialyzer or hemofilter arranged between the first line device and the second line device and/or an adsorber, means for generating a field, at least partially surrounding the first line device and/or the dialyzer or hemofilter and/or the adsorber, a controllable fluid conveyance device arranged in the first line device and/or the second line device, and at least one controllable body fluid conveyance unit arranged in the third line device and/or the fourth line device, a filter, wherein the permeate side of the filter is connected to the first line device and the second line device, and the side of the filter to be dialyzed is connected at its inlet to the third line device, which can be connected to a patient and is connected at its outlet to the fourth line device which can be connected to the patient,
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: January 7, 2020
    Assignee: FRESENIUS MEDICAL CARE DEUTSCHLAND GMBH
    Inventors: Ulrich Tschulena, Joachim Jankowski, Anselm Fabig
  • Patent number: 10284206
    Abstract: An oscillator includes: an oscillation stage circuit that is connected between a first electrode and a second electrode of a resonator and performs an oscillation operation; a variable capacitance element that is connected to the first or second electrode of the resonator and adjusts an oscillation frequency; a bandgap reference circuit that generates a reference voltage having magnitude, which changes depending on the temperature, by using a resistor inserted in a current path through which a current having magnitude, which changes depending on the temperature flows; and a bias current generating circuit that generates a bias current of the oscillation stage circuit based on the reference voltage, and that, thereby, reduces a change in the oscillation frequency due to the temperature dependence of the impedance of the resonator or the temperature dependence of the sensitivity of the variable capacitance element.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: May 7, 2019
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Yosuke Itasaka
  • Patent number: 10250269
    Abstract: An oscillator system includes a voltage controlled oscillator (VCO) circuit. The VCO circuit includes an output for providing an oscillation signal and input to receive a voltage that controls the frequency of the oscillation signal. The oscillator system includes a frequency to voltage circuit that receives the oscillation signal and produces a voltage that is dependent upon the frequency of the oscillation signal. The oscillator system includes a comparison circuit including an amplifier. The amplifier includes an inverting input, a non inverting input, and an output. During a first phase of the comparison circuit, the non inverting input receives a reference voltage and the inverting input is coupled to the output of the amplifier via a switch and to a capacitor wherein the capacitor samples the voltage of the output.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: April 2, 2019
    Assignee: NXP B.V.
    Inventors: Jos Verlinden, Sander Derksen, Dobson Paul Parlindungan Simanjuntak, Remco Cornelis Herman Van de Beek
  • Patent number: 10250266
    Abstract: An oscillator system for an integrated circuit includes a first oscillator circuit, a second oscillator circuit, and calibration system. During a sampling routine, the calibration system is used to determine a sampled value based on a comparison of the output of the second oscillator and an external clock signal. The sampled value is stored in a memory. During a calibration routine, the calibration system determines a comparison value based on a comparison of the output of the second oscillator circuit and the output of the first oscillator circuit. The calibration circuit compares the comparison value with the sampled value to generate a tuning value to tune the frequency of the first oscillator circuit.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: April 2, 2019
    Assignee: NXP B.V.
    Inventors: Anne-Johan Annema, Jos Verlinden
  • Patent number: 10230379
    Abstract: Techniques are disclosed relating to rapidly downshifting the output frequency of an oscillator. In some embodiments, the oscillator is configured to operate in a closed-loop mode in which negative feedback is used to maintain a particular output frequency (e.g., in a phase-locked loop (PLL)). In some embodiments, the negative feedback loop is configured to maintain the output of the oscillator at a particular frequency based on a reference clock signal and the output of the oscillator. The nature of a negative feedback loop may render rapid frequency changes difficult, e.g., because of corrections by the loop. Therefore, in some embodiments, the loop is configured to switch to an open-loop mode in which a control input to the oscillator is fixed. In some embodiments, the loop switches to open-loop mode in response to a trigger signal and control circuitry forces the oscillator to a new target frequency.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: March 12, 2019
    Assignee: Apple Inc.
    Inventors: Brian S. Leibowitz, Jared L. Zerbe, Sanjay Pant
  • Patent number: 10218336
    Abstract: A device and method can be used to manage the operation of a ring oscillator circuit. A master oscillator circuit generates a master supply voltage. The master supply voltage associated with a stable oscillation rate of the master oscillator circuit. The master oscillator circuit is supplied with current and is structurally identical to the ring oscillator circuit. A capacitive circuit is loaded with a load voltage originating from the master supply voltage. In response to a control signal, the ring oscillator circuit is supplied with a current controlled by a voltage delivered by the capacitive circuit, in such a way as to provide a stable oscillation rate for the ring oscillator circuit.
    Type: Grant
    Filed: February 19, 2017
    Date of Patent: February 26, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Francesco La Rosa
  • Patent number: 10114391
    Abstract: Embodiments of signal bias generators and regulators are described generally herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: October 30, 2018
    Assignee: pSemi Corporation
    Inventors: Tae Youn Kim, Robert Mark Englekirk
  • Patent number: 9973176
    Abstract: A circuit may comprise a first node, a ring oscillator, a regulator, and a Kvcc compensation circuit. The first node may be a supply node to provide a supply voltage for the circuit. The ring oscillator may be formed from inverters. The regulator may use a single transistor between the first node and a second node for powering the oscillator. The K compensation circuit may be used to provide to the oscillator a variable capacitive load that is dependent on the supply at the first supply node, and it may drag oscillator frequency down when the first node supply goes up.
    Type: Grant
    Filed: December 27, 2014
    Date of Patent: May 15, 2018
    Assignee: Intel Corporation
    Inventors: Shenggao Li, Sujatha B. Gowder
  • Patent number: 9843331
    Abstract: The invention relates to a method for operating a mechanical resonator in an electronic oscillator, comprising determining a state space description of the resonator, in which state variables are the mass, the stiffness or dimensions of components used in the crystal resonator; providing a table with frequency correction factors as a function of a state space of a resonator; finding a frequency correction factor corresponding to the determined state space; and multiplying the output frequency of the resonator with the correction factor, and to an electronic oscillator, comprising a mechanical resonator, wherein an output frequency of the oscillator is multiplied by a frequency correction factor, the frequency correction factor being obtained from determination of the state variables of the resonator, in particular dominant mechanical state variables.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: December 12, 2017
    Assignee: FRAPINVENTIONS B.V.
    Inventor: Antonius Johannes Maria Montagne
  • Patent number: 9819352
    Abstract: It is an object of the present invention to solve a problem that malfunction of communication is generated by varying a frequency of a clock due to noise from outside in a case where there is no supplied signal in a circuit which performs negative feedback control so that the supplied signal and the feedback signal can maintain a fixed phase relationship between the signals. The present invention provides a configuration including a PLL circuit and an oscillator circuit, where a switch for switching an output between a signal from the PLL circuit and a signal from the oscillator circuit to the signal output portion is provided to switch from a connection to the PLL circuit to a connection to the oscillator circuit in a case where there is no received signal.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: November 14, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Takeshi Osada
  • Patent number: 9778669
    Abstract: Embodiments of signal bias generators and regulators are described generally herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: October 3, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Tae Youn Kim, Robert Mark Englekirk
  • Patent number: 9577647
    Abstract: A voltage controlled oscillator arrangement is disclosed. The arrangement includes a voltage controlled oscillator and a bypass component. The voltage controlled oscillator has an output and a tuning port. The output provides an output signal at an operating frequency. The tuning port is configured to select the operating frequency according to an applied voltage. The voltage controlled oscillator has active portions and inactive portions. During the active portions, the output signal is at a non-zero value. The bypass component is configured to apply a bypass compensating signal to the tuning port during the active portions of the voltage controlled oscillator. The bypass compensating signal compensates for an oscillator temperature of the voltage controlled oscillator.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: February 21, 2017
    Assignee: Infineon Technologies AG
    Inventor: Johann Peter Forstner
  • Patent number: 9490744
    Abstract: Oscillator regulation circuitry is provided for regulating a frequency of an output signal generated by an oscillator. Oscillator regulation circuitry has frequency sensing circuitry for sensing the frequency of the output signal and generating a first signal depending on the frequency, and control circuitry which generates the oscillator control signal based on the comparison between the first signal and a non-oscillating reference signal. The frequency sensing circuitry includes at least one switched capacitor. This approach provides improved noise reduction, less sensitivity to process, temperature and voltage variations, and a more linear scaling of the frequency with the reference signal, compared to previous techniques.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: November 8, 2016
    Assignee: The Regents of the University of Michigan
    Inventors: Taekwang Jang, Dennis Michael Sylvester, David Theodore Blaauw
  • Patent number: 9429969
    Abstract: Embodiments of signal bias generators and regulators are described generally herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: August 30, 2016
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Tae Youn Kim, Robert Mark Englekirk
  • Patent number: 9397637
    Abstract: A low-power voltage controlled oscillator is provided. The voltage controlled oscillator includes (2n+1) first circuit components (n is an integer of one or more). An output terminal of the first circuit component in a k-th stage (k is an integer of one or more and 2n or less) is connected to an input terminal of the first circuit component in a (k+1)-th stage. An output terminal of the first circuit component in a (2n+1)-th stage is connected to an input terminal of the first circuit component in a first stage. One of the first circuit components includes a second circuit component and a third circuit component whose input terminal is connected to an output terminal of the second circuit component. The third circuit component includes a first transistor and a second transistor whose source-drain resistance is controlled in accordance with a signal input to a gate through the first transistor.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: July 19, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Munehiro Kozuma, Yoshiyuki Kurokawa, Takayuki Ikeda
  • Patent number: 9024699
    Abstract: Various techniques for generating an output clock based on a reference clock. This disclosure relates to generating an output clock signal based on a reference clock signal. In one embodiment, a method includes generating, using information received from a control circuit, an output clock signal using both a first number of edges or an input clock signal and a second, different number of edges of the input clock signal. In this embodiment, the control circuit runs at a frequency that is less than a frequency of the input clock signal. The received information may indicate, for a pulse of the output clock signal, whether the pulse should be generated using the first number of edges or the second number of edges. In some cases, the second number of edges may be the first number of edges plus one. The first and second number of edges may be programmable quantities.
    Type: Grant
    Filed: January 21, 2013
    Date of Patent: May 5, 2015
    Assignee: Apple Inc.
    Inventors: Kleanthes G. Koniaris, Erik P. Machnicki, Shane J. Keil
  • Patent number: 8994465
    Abstract: A method for reducing the phase noise of a oscillator includes monitoring a phase slope of a resonator, and controlling the resonator to operate the resonator at a high phase slope condition, wherein the resonator comprises a piezoelectric material, or piezoelectric quartz.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: March 31, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Randall L. Kubena, Richard J. Joyce, Harris P. Moyer
  • Patent number: 8988154
    Abstract: A voltage controlled oscillator includes a voltage-to-current converter and a current controlled oscillator, where the voltage-to-current converter is used for converting an input voltage to generate an output current, and the current controlled oscillator is used for generating an output frequency signal according to the output current. In addition, the voltage-to-current converter includes an input terminal, a resistor, a current mirror and a current generating circuit, where the input terminal is for receiving the input voltage; the resistor is coupled to the input terminal; the current mirror is coupled to the resistor, and is used for mirroring a reference current to generate a mirrored current, where the reference current is formed according to at least a current flowing through the resistor; and the current generating circuit is coupled to the current mirror, and is used for generating the output current according to at least the mirrored current.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: March 24, 2015
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventor: Huajiang Zhang
  • Patent number: 8975974
    Abstract: A wide frequency, low voltage oscillator includes multiple delay elements, in which each delay element includes two inverters coupled through a latching element into a differential-type configuration. Two current-source PMOS devices bias the latching element in a high-gain region at low-voltage. By coupling these current-source PMOS devices into the delay elements, the start-up voltage of the latching element is reduced. Each delay element is also biased using a replica bias circuit that scales the supply/control voltage of the oscillator and provides the scaled supply/control voltage to control the lower rail of oscillation amplitude. By coupling the replica bias circuit to the lower rail, the lower rail of the oscillation amplitude follows the changes to the supply/control voltage.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: March 10, 2015
    Assignee: QUALCOMM Incorporated
    Inventor: Sameer Wadhwa
  • Patent number: 8963650
    Abstract: A semiconductor device contrived to prevent a reference voltage and a reference current which are supplied to a high speed OCO from varying with a change in ambient temperature and/or a change in an external power supply voltage and to reduce the circuit area of a power supply module. The high speed OCO outputs a high speed clock whose magnitude is determined by the reference current and the reference voltage. A logic unit adjusts the values of the reference current and reference voltage, according to the reference voltage and reference current trimming codes related to detected ambient temperature and operating voltage.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: February 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Tsukasa Oishi, Katsuyoshi Mitsui, Naoki Otani
  • Patent number: 8963649
    Abstract: A voltage controlled oscillator (VCO) includes a current controlled oscillator, a voltage-to-current converter, and a sensing circuit. The sensing circuit includes a delay unit, and the sensing circuit is configured to generate a plurality of compensation control signals in response to a time delay of the delay unit. The voltage-to-current converter is configured to generate a current signal in response to a VCO control signal and the plurality of compensation control signals. The current controlled oscillator is configured to generate an oscillating signal in response to the current signal.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Matt Li, Min-Shueh Yuan, Chih-Hsien Chang
  • Patent number: 8963651
    Abstract: One embodiment relates to a method of compensating for crystal frequency variation over temperature. An example method includes obtaining an indication of temperature, computing a temperature compensation value based on the indication of temperature and a piecewise linear temperature compensation approximation, and compensating for a temperature offset in a crystal reference signal by adjusting a division ratio of a fractional divider in a phase-locked loop. The piecewise linear temperature compensation approximation can represent an approximation of frequency error in a crystal reference signal originating from a crystal over temperature. The piecewise linear temperature compensation approximation can be, for example, a linear approximation, a quadratic approximation, or a cubic approximation.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: February 24, 2015
    Assignee: Analog Devices, Inc.
    Inventors: Robert Timothy Edwards, Stephen Mark Beccue
  • Patent number: 8928423
    Abstract: A narrow band receiver or transceiver for processing electrical signals. The narrow band receiver or transceiver includes an amplifier, a voltage controlled oscillator and a tuning assembly comprising at least one control loop for tuning of the voltage controlled oscillator. At least a gain control of the amplifier is coupled to the control loop for simultaneously tuning the output amplitude of the voltage controlled oscillator and the gain of the amplifier. A compensation of the effect of variation on the gain of the amplifier, which includes an LC tank circuit, is performed by using an information in another LC tank circuit of the voltage controlled oscillator in the control loop.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: January 6, 2015
    Assignee: EM Microelectronic-Marin S.A.
    Inventors: Armin Tajalli, Marc Morin
  • Patent number: 8896389
    Abstract: The present disclosure relates to an oscillation circuit including a differential negative resistance element, a resonance circuit connected to the differential negative resistance element, and a stabilization circuit connected in parallel with the negative resistance element to suppress parasitic oscillation. The stabilization circuit includes a variable shunt resistor and an adjusting device for adjusting the shunt resistor.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: November 25, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasushi Koyama, Ryota Sekiguchi
  • Patent number: 8890633
    Abstract: According to an example embodiment, a device includes a resonant circuit configured and arranged to provide a peak current flow at a resonance frequency. A trimming circuit provides variable impedances to the resonant circuit and thereby changes the resonance frequency for the resonant circuit. A driver circuit is configured to generate a trimming signal that oscillates at a desired frequency. A switch circuit couples and decouples the driver circuit to the resonant circuit for driving the resonant circuit with the trimming signal. An amplitude detection circuit detects amplitudes for signals generated in response to the trimming signal being connected to the resonant circuit. A processing circuit correlates detected amplitudes from the amplitude detection circuit with different impedance values of the variable trimming circuit.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: November 18, 2014
    Assignee: NXP B.V.
    Inventor: Sven Simons
  • Patent number: 8884709
    Abstract: A phase-locked loop double-point modulator may include a frequency divider having a ratio which can be changed by a first modulation signal, and an oscillator, a frequency of which can be changed by a second modulation signal correlated to the first modulation signal. A calibration circuit may be configured, in a calibration mode, to match the gains of the first and second modulation signals based on frequency measurements of the oscillator for two different calibration values of the second modulation signal. The phase-locked double-point modulator may also include an attenuator having a constant ratio greater than 1 and placed in the path of the second modulation signal, and a selector switch configured to be controlled by the calibration circuit to reduce the ratio of the attenuator in the calibration mode.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: November 11, 2014
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Franck Badets, Serge Ramet, Michel Ayraud
  • Patent number: 8878615
    Abstract: The present application discloses a voltage-controlled oscillator device and a method of correcting the voltage-controlled oscillator. The voltage-controlled oscillator device comprises predistortion module, configured to predistort an input voltage to obtain a predistorted voltage; and a voltage-controlled oscillator, configured to generate an output signal with a corresponding oscillation frequency according to the predistorted voltage, wherein the predistortion module corrects a non-linear characteristic of the voltage-controlled oscillator, so that there is a linear relationship between the input voltage and the oscillation frequency of the output signal. The voltage-controlled oscillator device may be applied to a phase-locked circuit in a communication system.
    Type: Grant
    Filed: October 9, 2011
    Date of Patent: November 4, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Yuping Wu, Lan Chen
  • Patent number: 8866556
    Abstract: A phase shift phase locked loop (PSPLL) are described. The phase shift PLL includes a PLL and a phase adjusting circuit coupled to the inputs of the PLL. The phase adjusting circuit has a first input, a first output, a second input, a third input, and a second output. The first output and the second output are coupled to a first input and a second input of the PLL, respectively. The second input of the phase adjusting circuit receives a feedback signal and the third input of the phase adjusting circuit receives a control signal. The phase adjusting circuit receives a reference signal and sends a first output signal and a second output signal based on the reference signal to the PLL to adjust a phase of an output signal of the PLL in an increment less than a time period of the output signal of the PLL.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: October 21, 2014
    Assignee: Analog Bits, Inc.
    Inventor: Alan C. Rogers
  • Patent number: 8860517
    Abstract: An oscillator circuit including a first capacitor provided with a first terminal; a resistor provided with a reference terminal; a first current generator provided with a connection terminal; a second current generator provided with a second connection terminal. Further, the circuit includes a switching matrix between the first and second generators and resistor and the at least one first capacitor.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: October 14, 2014
    Assignee: STMicroelectronics S.R.L.
    Inventor: Mauro Giacomini
  • Patent number: 8836434
    Abstract: A digital frequency synthesizer with an automatic calibration system. The digital frequency synthesizer is calibrated by initiating a coarse tuning operation to rapidly reach a preliminary frequency that is proximate to the desired final frequency. A calibration procedure is then executed for adjusting gain in the frequency synthesizer based on the preliminary frequency. This test involves applying one or more test signals to the frequency synthesizer and measuring a signal generated in the frequency synthesizer. This measured signal corresponds to a gain response of the circuit at the preliminary frequency. When the expected gain is known, any difference relative to the gain of the measured signal is used to adjust the gain in a circuit of the frequency synthesizer such that the actual gain substantially matches the expected gain.
    Type: Grant
    Filed: September 8, 2009
    Date of Patent: September 16, 2014
    Assignee: Icera Inc.
    Inventors: Abdellatif Bellaouar, Ahmed R. Fridi, Sher Jiun Fang, Hamid Safiri
  • Patent number: 8816781
    Abstract: An all-digital frequency detector is provided, which includes a phase-frequency detector receiving a reference clock and an input clock, two sample/hold circuits sampling the phase-frequency detector outputs responsive to a ninety-degree phase shifted reference clock and a ninety-degree phase shifted input clock, a plurality of logical operators to generate an output frequency detection signal and a output clock responsive to the difference between the reference clock and the input clock.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: August 26, 2014
    Inventor: Phuong Huynh
  • Patent number: 8810329
    Abstract: An LC oscillator tank that generates a tank oscillation at a phase substantially equal to a temperature null phase. The oscillator further includes frequency stabilizer circuitry coupled to the LC oscillator tank to cause the LC oscillator tank to operate at the temperature null phase. In one aspect of the disclosure, a feedback loop may split the output voltage of the LC tank into two voltages having different phases, where each voltage is independently transformed into a current through programmable transconductors, The two currents may be combined to form a resultant current which is then applied to the LC tank. The phase of the resultant current is such that the LC tank operates at an impedance condition that achieves frequency stability across temperature.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: August 19, 2014
    Inventors: Nabil M. Sinoussi, Bassel Hanafi
  • Patent number: 8810323
    Abstract: In one embodiment, a voltage-controlled oscillator (VCO) is provided that includes: a plurality of differential inverters coupled to form a loop, each differential inverter having a differential pair of transistors configured to steer a tail current from a current source, the current source sourcing the tail current responsive to a bias voltage, wherein each transistor in the differential pair couples to a power source through a corresponding switching-capacitor circuit; and a bias circuit configured to generate the bias voltage such that a transconductance for each transistor in the differential pairs is proportional to a factor that is a function of a ratio of transistor widths within the bias circuit.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: August 19, 2014
    Inventor: Mohammad Ardehali
  • Patent number: 8775491
    Abstract: A method for reducing signal edge jitter in an output signal from a numerically controlled oscillator includes processing an input signal with a first accumulator to provide a first accumulator output signal and continuing to use a carry in the processing of the input signal with the first accumulator in the event of an overflow. The method further includes processing the input signal with a second accumulator to provide a second accumulator output signal and rejecting a carry in the processing of the input signal with the second accumulator in the event of an overflow. The method further includes outputting the second accumulator output signal at an output of the numerically controlled oscillator and synchronizing the second accumulator using the first accumulator output signal.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: July 8, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Alexander Buhmann, Marian Keck
  • Patent number: 8773211
    Abstract: An electrical circuit includes a circuit element and a common mode rejection circuit element. The circuit element is configured to operate at a selected frequency within a variable frequency range and the common mode rejection circuit element is configured to reject a common mode current through the circuit element, wherein the common mode rejection circuit element is adjustable.
    Type: Grant
    Filed: November 25, 2011
    Date of Patent: July 8, 2014
    Assignee: Intel Mobile Communications GmbH
    Inventor: Andreas Roithmeier
  • Patent number: 8704602
    Abstract: A modulation section including a feedback circuit configured to conduct feedback control of an output signal from a voltage controlled oscillator based on an inputted modulation signal, and a feed-forward circuit configured to calibrate the modulation signal and outputting the calibrated modulation signal to the voltage controlled oscillator; a signal output section configured to output, to the modulation section, a predetermined reference signal instead of the modulation signal when a calibration is conducted; and a gain correction section configured to, in a state where the feedback circuit is forming an open loop, calculate a frequency transition amount of the reference signal outputted by the voltage controlled oscillator, and correct a gain used for calibrating the modulation signal at the feed-forward circuit based on the calculated frequency transition amount.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: April 22, 2014
    Assignee: Panasonic Corporation
    Inventors: Kenji Miyanaga, Takayuki Tsukizawa
  • Publication number: 20140077891
    Abstract: A crystal oscillator emulator having a plurality of predetermined operating configurations. The crystal oscillator emulator includes a measurement circuit configured to measure a value of an impedance connected to a select pin of the crystal oscillator emulator, wherein the impedance is external to the crystal oscillator emulator, and generate an output having a value corresponding to the value of the impedance. The storage circuit is configured to store a plurality of values corresponding to the plurality of predetermined operating configurations and select one of the plurality of values based on the output of the measurement circuit. A controller is configured to set an output frequency of the crystal oscillator emulator based on the selected one of the plurality of values.
    Type: Application
    Filed: November 25, 2013
    Publication date: March 20, 2014
    Applicant: Marvell World Trade Ltd.
    Inventor: Sehat Sutardja
  • Patent number: 8674780
    Abstract: An oscillator includes a nominal frequency output unit, a frequency adjustment amount output unit, a gain output unit, a multiplier, and an adder. The nominal frequency output unit is configured to output a first digital value corresponding to the nominal frequency. The frequency adjustment amount output unit is configured to output a second digital value corresponding to a rate of frequency in order to set a frequency adjustment amount with respect to the nominal frequency using the rate of frequency. The gain output unit is configured to output a third digital value corresponding to a gain to be multiplied by the second digital value. The multiplier is configured to multiply the second digital value by the third digital value, thus outputting a fourth digital value. The adder adds the first digital value and the fourth digital value to output the added result as a setting signal of frequency.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: March 18, 2014
    Assignee: Nihon Dempa Kogyo Co., Ltd.
    Inventors: Kazuo Akaike, Tsukasa Kobata, Shinichi Sato, Mitsuaki Koyama
  • Patent number: 8674777
    Abstract: A method for compensating NCO jitter by changing a step value used to increment an accumulator in the NCO to make up for inaccuracies, or jitters. In one approach, a remainder in the accumulator may be monitored and a compensated clock close to the current edge of an ideal clock may be generated. In another approach, a compensated clock close to the next edge of the ideal clock may be generated after the current edge of the ideal clock is missed. The step value may be stored in a memory, which may be a register. A jitter compensator may include a comparator for monitoring the remainder in the accumulator or a detector for detecting whether an ideal clock has been missed. The jitter compensator may also change the step value to a step value for a faster clock to compensate jitter.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: March 18, 2014
    Assignee: Marvell International Ltd.
    Inventors: Robert Mack, Timothy Chen
  • Patent number: 8665030
    Abstract: A voltage-controlled oscillator circuit includes a first transistor, a second transistor, a first resonator circuit, a second resonator circuit, a first current path and a second current path. A drain of the first transistor is coupled to a gate of the second transistor and to a first end of the first resonator circuit. A source of the first transistor is coupled to the first current path and to a first end of the second resonator circuit. A drain of the second transistor is coupled to a gate of the first transistor and to a second end of the first resonator circuit. A source of the second transistor is coupled to the second current path and a second end of the second resonator circuit.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: March 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ta Lu, Hsien-Yuan Liao, Hsiao-Tsung Yen, Ho-Hsiang Chen, Chewn-Pu Jou
  • Publication number: 20140035690
    Abstract: The present invention relates to a voltage change compensation type oscillator and a method of compensating an error of an oscillator, which includes a voltage level detecting unit; a current level adjusting unit; and an oscillating core unit for generating and outputting a clock signal by receiving a power supply voltage and an output current of the current level adjusting unit, wherein the current level adjusting unit adjusts the output current in proportion to an increase of the voltage level detected by the voltage level detecting unit, thus remarkably reducing a frequency error of the clock signal in spite of changes in voltage.
    Type: Application
    Filed: December 6, 2012
    Publication date: February 6, 2014
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Soo Woong Lee
  • Patent number: 8643442
    Abstract: An oscillator circuit includes a signal generator having a compensation frequency output node that provides a compensation frequency signal at the compensation frequency output node. A pulse generator having a pulsed signal output node and a pulse generator input node is coupled to the compensation frequency output node and converts the compensation frequency signal into a series of compensation binary pulses having a constant pulse duration regardless of variations in the duty cycle of the compensation binary pulses. An oscillator module having at least two capacitors, an oscillator output node and a pulsed signal input node is coupled to the pulsed signal output node, and provides an output signal that is at a frequency dependent on charging rates of the capacitors. Drift variations in the capacitors are offset by variations in a duty cycle of the compensation binary pulses supplied in order to maintain constant charging rates of the capacitors.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: February 4, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Meng Wang